Revision 41db4607
| b/target-mips/translate.c | ||
|---|---|---|
| 429 | 429 |
static TCGv_ptr cpu_env; |
| 430 | 430 |
static TCGv cpu_gpr[32], cpu_PC; |
| 431 | 431 |
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC]; |
| 432 |
static TCGv cpu_dspctrl, btarget; |
|
| 433 |
static TCGv bcond;
|
|
| 432 |
static TCGv cpu_dspctrl, btarget, bcond;
|
|
| 433 |
static TCGv_i32 hflags;
|
|
| 434 | 434 |
static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32]; |
| 435 | 435 |
static TCGv_i32 fpu_fcr0, fpu_fcr31; |
| 436 | 436 |
|
| ... | ... | |
| 758 | 758 |
ctx->saved_pc = ctx->pc; |
| 759 | 759 |
} |
| 760 | 760 |
if (ctx->hflags != ctx->saved_hflags) {
|
| 761 |
TCGv_i32 r_tmp = tcg_temp_new_i32(); |
|
| 762 |
|
|
| 763 |
tcg_gen_movi_i32(r_tmp, ctx->hflags); |
|
| 764 |
tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags)); |
|
| 765 |
tcg_temp_free_i32(r_tmp); |
|
| 761 |
tcg_gen_movi_i32(hflags, ctx->hflags); |
|
| 766 | 762 |
ctx->saved_hflags = ctx->hflags; |
| 767 | 763 |
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
|
| 768 | 764 |
case MIPS_HFLAG_BR: |
| ... | ... | |
| 7555 | 7551 |
|
| 7556 | 7552 |
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
|
| 7557 | 7553 |
tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); |
| 7558 |
{
|
|
| 7559 |
TCGv_i32 r_tmp = tcg_temp_new_i32(); |
|
| 7560 |
|
|
| 7561 |
tcg_gen_movi_i32(r_tmp, ctx->hflags & ~MIPS_HFLAG_BMASK); |
|
| 7562 |
tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags)); |
|
| 7563 |
tcg_temp_free_i32(r_tmp); |
|
| 7564 |
} |
|
| 7554 |
tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); |
|
| 7565 | 7555 |
gen_goto_tb(ctx, 1, ctx->pc + 4); |
| 7566 | 7556 |
gen_set_label(l1); |
| 7567 | 7557 |
} |
| ... | ... | |
| 8413 | 8403 |
offsetof(CPUState, bcond), "bcond"); |
| 8414 | 8404 |
btarget = tcg_global_mem_new(TCG_AREG0, |
| 8415 | 8405 |
offsetof(CPUState, btarget), "btarget"); |
| 8406 |
hflags = tcg_global_mem_new_i32(TCG_AREG0, |
|
| 8407 |
offsetof(CPUState, hflags), "hflags"); |
|
| 8408 |
|
|
| 8416 | 8409 |
for (i = 0; i < 32; i++) |
| 8417 | 8410 |
fpu_fpr32[i] = tcg_global_mem_new_i32(TCG_AREG0, |
| 8418 | 8411 |
offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]), |
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