root / target-mips / exec.h @ 41db4607
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#if !defined(__QEMU_MIPS_EXEC_H__)
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#define __QEMU_MIPS_EXEC_H__
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//#define DEBUG_OP
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#include "config.h" |
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#include "mips-defs.h" |
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#include "dyngen-exec.h" |
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#include "cpu-defs.h" |
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register struct CPUMIPSState *env asm(AREG0); |
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#include "cpu.h" |
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#include "exec-all.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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void dump_fpu(CPUState *env);
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void fpu_dump_state(CPUState *env, FILE *f,
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int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
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int flags);
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void cpu_mips_clock_init (CPUState *env);
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void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
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static inline void env_to_regs(void) |
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{
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} |
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static inline void regs_to_env(void) |
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{
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} |
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static inline int cpu_halted(CPUState *env) |
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{
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if (!env->halted)
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return 0; |
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if (env->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
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env->halted = 0;
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return 0; |
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} |
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return EXCP_HALTED;
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} |
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static inline void compute_hflags(CPUState *env) |
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{
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env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
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MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
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MIPS_HFLAG_UX); |
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if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
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} |
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#if defined(TARGET_MIPS64)
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if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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(env->CP0_Status & (1 << CP0St_PX)) ||
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(env->CP0_Status & (1 << CP0St_UX)))
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env->hflags |= MIPS_HFLAG_64; |
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if (env->CP0_Status & (1 << CP0St_UX)) |
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env->hflags |= MIPS_HFLAG_UX; |
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#endif
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if ((env->CP0_Status & (1 << CP0St_CU0)) || |
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!(env->hflags & MIPS_HFLAG_KSU)) |
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env->hflags |= MIPS_HFLAG_CP0; |
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if (env->CP0_Status & (1 << CP0St_CU1)) |
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env->hflags |= MIPS_HFLAG_FPU; |
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if (env->CP0_Status & (1 << CP0St_FR)) |
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env->hflags |= MIPS_HFLAG_F64; |
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if (env->insn_flags & ISA_MIPS32R2) {
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if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
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env->hflags |= MIPS_HFLAG_COP1X; |
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} else if (env->insn_flags & ISA_MIPS32) { |
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if (env->hflags & MIPS_HFLAG_64)
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env->hflags |= MIPS_HFLAG_COP1X; |
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} else if (env->insn_flags & ISA_MIPS4) { |
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/* All supported MIPS IV CPUs use the XX (CU3) to enable
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and disable the MIPS IV extensions to the MIPS III ISA.
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Some other MIPS IV CPUs ignore the bit, so the check here
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would be too restrictive for them. */
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if (env->CP0_Status & (1 << CP0St_CU3)) |
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env->hflags |= MIPS_HFLAG_COP1X; |
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} |
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} |
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#endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |