root / target-mips / translate_init.c @ 41db4607
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/*
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* MIPS emulation for qemu: CPU initialisation routines.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2007 Herve Poussineau
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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/* CPU / CPU family specific config register values. */
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/* Have config1, uncached coherency */
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#define MIPS_CONFIG0 \
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((1 << CP0C0_M) | (0x2 << CP0C0_K0)) |
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/* Have config2, no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, no FPU */
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr (PABITS),
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no external interrupt controller, no vectored interupts,
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no 1kb pages, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
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(0 << CP0C3_SM) | (0 << CP0C3_TL)) |
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/* Define a implementation number of 1.
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Define a major version 1, minor version 0. */
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#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) |
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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enum mips_mmu_types {
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MMU_TYPE_NONE, |
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MMU_TYPE_R4000, |
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MMU_TYPE_RESERVED, |
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MMU_TYPE_FMT, |
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MMU_TYPE_R3000, |
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MMU_TYPE_R6000, |
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MMU_TYPE_R8000 |
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}; |
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struct mips_def_t {
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const char *name; |
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int32_t CP0_PRid; |
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int32_t CP0_Config0; |
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int32_t CP0_Config1; |
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int32_t CP0_Config2; |
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int32_t CP0_Config3; |
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int32_t CP0_Config6; |
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int32_t CP0_Config7; |
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int32_t SYNCI_Step; |
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int32_t CCRes; |
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int32_t CP0_Status_rw_bitmask; |
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int32_t CP0_TCStatus_rw_bitmask; |
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int32_t CP0_SRSCtl; |
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int32_t CP1_fcr0; |
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int32_t SEGBITS; |
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int32_t PABITS; |
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int32_t CP0_SRSConf0_rw_bitmask; |
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int32_t CP0_SRSConf0; |
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int32_t CP0_SRSConf1_rw_bitmask; |
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int32_t CP0_SRSConf1; |
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int32_t CP0_SRSConf2_rw_bitmask; |
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int32_t CP0_SRSConf2; |
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int32_t CP0_SRSConf3_rw_bitmask; |
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int32_t CP0_SRSConf3; |
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int32_t CP0_SRSConf4_rw_bitmask; |
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int32_t CP0_SRSConf4; |
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int insn_flags;
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enum mips_mmu_types mmu_type;
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}; |
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/*****************************************************************************/
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/* MIPS CPU definitions */
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static const mips_def_t mips_defs[] = |
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{
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{
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.name = "4Kc",
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.CP0_PRid = 0x00018000,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{
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.name = "4Km",
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.CP0_PRid = 0x00018300,
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/* Config1 implemented, fixed mapping MMU,
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no virtual icache, uncached coherency. */
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_FMT, |
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}, |
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{
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.name = "4KEcR1",
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.CP0_PRid = 0x00018400,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{
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.name = "4KEmR1",
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.CP0_PRid = 0x00018500,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_FMT, |
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}, |
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{
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.name = "4KEc",
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.CP0_PRid = 0x00019000,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{
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.name = "4KEm",
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.CP0_PRid = 0x00019100,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_FMT << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_FMT, |
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}, |
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{
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.name = "24Kc",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x1278FF1F,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{
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.name = "24Kf",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{
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.name = "34Kf",
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.CP0_PRid = 0x00019500,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), |
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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/* No DSP implemented. */
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.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
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(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
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(0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
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(1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
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(0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
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(0xff << CP0TCSt_TASID),
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
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.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
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.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
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(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
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.CP0_SRSConf1_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
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(0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
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.CP0_SRSConf2_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
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(0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
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.CP0_SRSConf3_rw_bitmask = 0x3fffffff,
|
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.CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
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(0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
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.CP0_SRSConf4_rw_bitmask = 0x3fffffff,
|
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.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
|
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(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
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.mmu_type = MMU_TYPE_R4000, |
| 289 |
}, |
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#if defined(TARGET_MIPS64)
|
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{
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| 292 |
.name = "R4000",
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.CP0_PRid = 0x00000400,
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/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
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.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
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/* Note: Config1 is only used internally, the R4000 has only Config0. */
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.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 298 |
.SYNCI_Step = 16,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x3678FFFF,
|
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/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
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.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 303 |
.SEGBITS = 40,
|
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.PABITS = 36,
|
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.insn_flags = CPU_MIPS3, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
| 308 |
{
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.name = "VR5432",
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| 310 |
.CP0_PRid = 0x00005400,
|
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/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
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.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
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.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 314 |
.SYNCI_Step = 16,
|
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.CCRes = 2,
|
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.CP0_Status_rw_bitmask = 0x3678FFFF,
|
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/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
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.CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 319 |
.SEGBITS = 40,
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.PABITS = 32,
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.insn_flags = CPU_VR54XX, |
| 322 |
.mmu_type = MMU_TYPE_R4000, |
| 323 |
}, |
| 324 |
{
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| 325 |
.name = "5Kc",
|
| 326 |
.CP0_PRid = 0x00018100,
|
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
| 328 |
(MMU_TYPE_R4000 << CP0C0_MT), |
| 329 |
.CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
|
| 330 |
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 331 |
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 332 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 333 |
.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
|
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.CCRes = 2,
|
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.CP0_Status_rw_bitmask = 0x32F8FFFF,
|
| 338 |
.SEGBITS = 42,
|
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.PABITS = 36,
|
| 340 |
.insn_flags = CPU_MIPS64, |
| 341 |
.mmu_type = MMU_TYPE_R4000, |
| 342 |
}, |
| 343 |
{
|
| 344 |
.name = "5Kf",
|
| 345 |
.CP0_PRid = 0x00018100,
|
| 346 |
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
| 347 |
(MMU_TYPE_R4000 << CP0C0_MT), |
| 348 |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
| 349 |
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 350 |
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 351 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 352 |
.CP0_Config2 = MIPS_CONFIG2, |
| 353 |
.CP0_Config3 = MIPS_CONFIG3, |
| 354 |
.SYNCI_Step = 32,
|
| 355 |
.CCRes = 2,
|
| 356 |
.CP0_Status_rw_bitmask = 0x36F8FFFF,
|
| 357 |
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
|
| 358 |
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
| 359 |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 360 |
.SEGBITS = 42,
|
| 361 |
.PABITS = 36,
|
| 362 |
.insn_flags = CPU_MIPS64, |
| 363 |
.mmu_type = MMU_TYPE_R4000, |
| 364 |
}, |
| 365 |
{
|
| 366 |
.name = "20Kc",
|
| 367 |
/* We emulate a later version of the 20Kc, earlier ones had a broken
|
| 368 |
WAIT instruction. */
|
| 369 |
.CP0_PRid = 0x000182a0,
|
| 370 |
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
| 371 |
(MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
|
| 372 |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
| 373 |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 374 |
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 375 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 376 |
.CP0_Config2 = MIPS_CONFIG2, |
| 377 |
.CP0_Config3 = MIPS_CONFIG3, |
| 378 |
.SYNCI_Step = 32,
|
| 379 |
.CCRes = 1,
|
| 380 |
.CP0_Status_rw_bitmask = 0x36FBFFFF,
|
| 381 |
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
|
| 382 |
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 383 |
(1 << FCR0_D) | (1 << FCR0_S) | |
| 384 |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 385 |
.SEGBITS = 40,
|
| 386 |
.PABITS = 36,
|
| 387 |
.insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
| 388 |
.mmu_type = MMU_TYPE_R4000, |
| 389 |
}, |
| 390 |
{
|
| 391 |
/* A generic CPU providing MIPS64 Release 2 features.
|
| 392 |
FIXME: Eventually this should be replaced by a real CPU model. */
|
| 393 |
.name = "MIPS64R2-generic",
|
| 394 |
.CP0_PRid = 0x00010000,
|
| 395 |
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 396 |
(MMU_TYPE_R4000 << CP0C0_MT), |
| 397 |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| 398 |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 399 |
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 400 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 401 |
.CP0_Config2 = MIPS_CONFIG2, |
| 402 |
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
|
| 403 |
.SYNCI_Step = 32,
|
| 404 |
.CCRes = 2,
|
| 405 |
.CP0_Status_rw_bitmask = 0x36FBFFFF,
|
| 406 |
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 407 |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 408 |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 409 |
.SEGBITS = 42,
|
| 410 |
/* The architectural limit is 59, but we have hardcoded 36 bit
|
| 411 |
in some places...
|
| 412 |
.PABITS = 59, */ /* the architectural limit */ |
| 413 |
.PABITS = 36,
|
| 414 |
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
| 415 |
.mmu_type = MMU_TYPE_R4000, |
| 416 |
}, |
| 417 |
#endif
|
| 418 |
}; |
| 419 |
|
| 420 |
static const mips_def_t *cpu_mips_find_by_name (const char *name) |
| 421 |
{
|
| 422 |
int i;
|
| 423 |
|
| 424 |
for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
| 425 |
if (strcasecmp(name, mips_defs[i].name) == 0) { |
| 426 |
return &mips_defs[i];
|
| 427 |
} |
| 428 |
} |
| 429 |
return NULL; |
| 430 |
} |
| 431 |
|
| 432 |
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
| 433 |
{
|
| 434 |
int i;
|
| 435 |
|
| 436 |
for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
| 437 |
(*cpu_fprintf)(f, "MIPS '%s'\n",
|
| 438 |
mips_defs[i].name); |
| 439 |
} |
| 440 |
} |
| 441 |
|
| 442 |
#ifndef CONFIG_USER_ONLY
|
| 443 |
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
| 444 |
{
|
| 445 |
env->tlb->nb_tlb = 1;
|
| 446 |
env->tlb->map_address = &no_mmu_map_address; |
| 447 |
} |
| 448 |
|
| 449 |
static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
| 450 |
{
|
| 451 |
env->tlb->nb_tlb = 1;
|
| 452 |
env->tlb->map_address = &fixed_mmu_map_address; |
| 453 |
} |
| 454 |
|
| 455 |
static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
| 456 |
{
|
| 457 |
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
| 458 |
env->tlb->map_address = &r4k_map_address; |
| 459 |
env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
| 460 |
env->tlb->helper_tlbwr = r4k_helper_tlbwr; |
| 461 |
env->tlb->helper_tlbp = r4k_helper_tlbp; |
| 462 |
env->tlb->helper_tlbr = r4k_helper_tlbr; |
| 463 |
} |
| 464 |
|
| 465 |
static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
| 466 |
{
|
| 467 |
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
|
| 468 |
|
| 469 |
switch (def->mmu_type) {
|
| 470 |
case MMU_TYPE_NONE:
|
| 471 |
no_mmu_init(env, def); |
| 472 |
break;
|
| 473 |
case MMU_TYPE_R4000:
|
| 474 |
r4k_mmu_init(env, def); |
| 475 |
break;
|
| 476 |
case MMU_TYPE_FMT:
|
| 477 |
fixed_mmu_init(env, def); |
| 478 |
break;
|
| 479 |
case MMU_TYPE_R3000:
|
| 480 |
case MMU_TYPE_R6000:
|
| 481 |
case MMU_TYPE_R8000:
|
| 482 |
default:
|
| 483 |
cpu_abort(env, "MMU type not supported\n");
|
| 484 |
} |
| 485 |
env->CP0_Random = env->tlb->nb_tlb - 1;
|
| 486 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
| 487 |
} |
| 488 |
#endif /* CONFIG_USER_ONLY */ |
| 489 |
|
| 490 |
static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
| 491 |
{
|
| 492 |
int i;
|
| 493 |
|
| 494 |
for (i = 0; i < MIPS_FPU_MAX; i++) |
| 495 |
env->fpus[i].fcr0 = def->CP1_fcr0; |
| 496 |
|
| 497 |
memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
| 498 |
#if defined(CONFIG_USER_ONLY)
|
| 499 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
| 500 |
env->hflags |= MIPS_HFLAG_FPU; |
| 501 |
#ifdef TARGET_MIPS64
|
| 502 |
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
| 503 |
env->hflags |= MIPS_HFLAG_F64; |
| 504 |
#endif
|
| 505 |
#endif
|
| 506 |
} |
| 507 |
|
| 508 |
static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
| 509 |
{
|
| 510 |
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
|
| 511 |
|
| 512 |
/* MVPConf1 implemented, TLB sharable, no gating storage support,
|
| 513 |
programmable cache partitioning implemented, number of allocatable
|
| 514 |
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
|
| 515 |
implemented, 5 TCs implemented. */
|
| 516 |
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
| 517 |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
| 518 |
// TODO: actually do 2 VPEs.
|
| 519 |
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
|
| 520 |
// (0x04 << CP0MVPC0_PTC);
|
| 521 |
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
| 522 |
(0x04 << CP0MVPC0_PTC);
|
| 523 |
#if !defined(CONFIG_USER_ONLY)
|
| 524 |
/* Usermode has no TLB support */
|
| 525 |
env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
| 526 |
#endif
|
| 527 |
|
| 528 |
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
|
| 529 |
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
|
| 530 |
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
| 531 |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
| 532 |
(0x1 << CP0MVPC1_PCP1);
|
| 533 |
} |
| 534 |
|
| 535 |
static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def) |
| 536 |
{
|
| 537 |
env->CP0_PRid = def->CP0_PRid; |
| 538 |
env->CP0_Config0 = def->CP0_Config0; |
| 539 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 540 |
env->CP0_Config0 |= (1 << CP0C0_BE);
|
| 541 |
#endif
|
| 542 |
env->CP0_Config1 = def->CP0_Config1; |
| 543 |
env->CP0_Config2 = def->CP0_Config2; |
| 544 |
env->CP0_Config3 = def->CP0_Config3; |
| 545 |
env->CP0_Config6 = def->CP0_Config6; |
| 546 |
env->CP0_Config7 = def->CP0_Config7; |
| 547 |
env->SYNCI_Step = def->SYNCI_Step; |
| 548 |
env->CCRes = def->CCRes; |
| 549 |
env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask; |
| 550 |
env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask; |
| 551 |
env->CP0_SRSCtl = def->CP0_SRSCtl; |
| 552 |
env->current_tc = 0;
|
| 553 |
env->SEGBITS = def->SEGBITS; |
| 554 |
env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1); |
| 555 |
#if defined(TARGET_MIPS64)
|
| 556 |
if (def->insn_flags & ISA_MIPS3) {
|
| 557 |
env->hflags |= MIPS_HFLAG_64; |
| 558 |
env->SEGMask |= 3ULL << 62; |
| 559 |
} |
| 560 |
#endif
|
| 561 |
env->PABITS = def->PABITS; |
| 562 |
env->PAMask = (target_ulong)((1ULL << def->PABITS) - 1); |
| 563 |
env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask; |
| 564 |
env->CP0_SRSConf0 = def->CP0_SRSConf0; |
| 565 |
env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask; |
| 566 |
env->CP0_SRSConf1 = def->CP0_SRSConf1; |
| 567 |
env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask; |
| 568 |
env->CP0_SRSConf2 = def->CP0_SRSConf2; |
| 569 |
env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask; |
| 570 |
env->CP0_SRSConf3 = def->CP0_SRSConf3; |
| 571 |
env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask; |
| 572 |
env->CP0_SRSConf4 = def->CP0_SRSConf4; |
| 573 |
env->insn_flags = def->insn_flags; |
| 574 |
|
| 575 |
#ifndef CONFIG_USER_ONLY
|
| 576 |
mmu_init(env, def); |
| 577 |
#endif
|
| 578 |
fpu_init(env, def); |
| 579 |
mvp_init(env, def); |
| 580 |
return 0; |
| 581 |
} |