Revision 42a623c7 cpu-exec.c
| b/cpu-exec.c | ||
|---|---|---|
| 23 | 23 |
#include "kvm.h" |
| 24 | 24 |
#include "qemu-barrier.h" |
| 25 | 25 |
|
| 26 |
#if !defined(CONFIG_SOFTMMU) |
|
| 27 |
#undef EAX |
|
| 28 |
#undef ECX |
|
| 29 |
#undef EDX |
|
| 30 |
#undef EBX |
|
| 31 |
#undef ESP |
|
| 32 |
#undef EBP |
|
| 33 |
#undef ESI |
|
| 34 |
#undef EDI |
|
| 35 |
#undef EIP |
|
| 36 |
#include <signal.h> |
|
| 37 |
#ifdef __linux__ |
|
| 38 |
#include <sys/ucontext.h> |
|
| 39 |
#endif |
|
| 40 |
#endif |
|
| 41 |
|
|
| 42 | 26 |
#if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
| 43 | 27 |
// Work around ugly bugs in glibc that mangle global register contents |
| 44 | 28 |
#undef env |
| ... | ... | |
| 48 | 32 |
int tb_invalidated_flag; |
| 49 | 33 |
|
| 50 | 34 |
//#define CONFIG_DEBUG_EXEC |
| 51 |
//#define DEBUG_SIGNAL |
|
| 52 | 35 |
|
| 53 | 36 |
int qemu_cpu_has_work(CPUState *env) |
| 54 | 37 |
{
|
| ... | ... | |
| 74 | 57 |
env->exception_index = -1; |
| 75 | 58 |
longjmp(env->jmp_env, 1); |
| 76 | 59 |
} |
| 77 |
|
|
| 78 |
#else |
|
| 79 |
|
|
| 80 |
void cpu_resume_from_signal(CPUState *env1, void *puc) |
|
| 81 |
{
|
|
| 82 |
#ifdef __linux__ |
|
| 83 |
struct ucontext *uc = puc; |
|
| 84 |
#elif defined(__OpenBSD__) |
|
| 85 |
struct sigcontext *uc = puc; |
|
| 86 |
#endif |
|
| 87 |
|
|
| 88 |
env = env1; |
|
| 89 |
|
|
| 90 |
/* XXX: restore cpu registers saved in host registers */ |
|
| 91 |
|
|
| 92 |
if (puc) {
|
|
| 93 |
/* XXX: use siglongjmp ? */ |
|
| 94 |
#ifdef __linux__ |
|
| 95 |
#ifdef __ia64 |
|
| 96 |
sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL); |
|
| 97 |
#else |
|
| 98 |
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
|
| 99 |
#endif |
|
| 100 |
#elif defined(__OpenBSD__) |
|
| 101 |
sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); |
|
| 102 |
#endif |
|
| 103 |
} |
|
| 104 |
env->exception_index = -1; |
|
| 105 |
longjmp(env->jmp_env, 1); |
|
| 106 |
} |
|
| 107 | 60 |
#endif |
| 108 | 61 |
|
| 109 | 62 |
/* Execute the code without caching the generated code. An interpreter |
| ... | ... | |
| 713 | 666 |
cpu_single_env = NULL; |
| 714 | 667 |
return ret; |
| 715 | 668 |
} |
| 716 |
|
|
| 717 |
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
|
| 718 |
|
|
| 719 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
|
| 720 |
{
|
|
| 721 |
CPUX86State *saved_env; |
|
| 722 |
|
|
| 723 |
saved_env = env; |
|
| 724 |
env = s; |
|
| 725 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
|
|
| 726 |
selector &= 0xffff; |
|
| 727 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
|
| 728 |
(selector << 4), 0xffff, 0); |
|
| 729 |
} else {
|
|
| 730 |
helper_load_seg(seg_reg, selector); |
|
| 731 |
} |
|
| 732 |
env = saved_env; |
|
| 733 |
} |
|
| 734 |
|
|
| 735 |
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32) |
|
| 736 |
{
|
|
| 737 |
CPUX86State *saved_env; |
|
| 738 |
|
|
| 739 |
saved_env = env; |
|
| 740 |
env = s; |
|
| 741 |
|
|
| 742 |
helper_fsave(ptr, data32); |
|
| 743 |
|
|
| 744 |
env = saved_env; |
|
| 745 |
} |
|
| 746 |
|
|
| 747 |
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32) |
|
| 748 |
{
|
|
| 749 |
CPUX86State *saved_env; |
|
| 750 |
|
|
| 751 |
saved_env = env; |
|
| 752 |
env = s; |
|
| 753 |
|
|
| 754 |
helper_frstor(ptr, data32); |
|
| 755 |
|
|
| 756 |
env = saved_env; |
|
| 757 |
} |
|
| 758 |
|
|
| 759 |
#endif /* TARGET_I386 */ |
|
| 760 |
|
|
| 761 |
#if !defined(CONFIG_SOFTMMU) |
|
| 762 |
|
|
| 763 |
#if defined(TARGET_I386) |
|
| 764 |
#define EXCEPTION_ACTION \ |
|
| 765 |
raise_exception_err(env->exception_index, env->error_code) |
|
| 766 |
#else |
|
| 767 |
#define EXCEPTION_ACTION \ |
|
| 768 |
cpu_loop_exit() |
|
| 769 |
#endif |
|
| 770 |
|
|
| 771 |
/* 'pc' is the host PC at which the exception was raised. 'address' is |
|
| 772 |
the effective address of the memory exception. 'is_write' is 1 if a |
|
| 773 |
write caused the exception and otherwise 0'. 'old_set' is the |
|
| 774 |
signal set which should be restored */ |
|
| 775 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
|
| 776 |
int is_write, sigset_t *old_set, |
|
| 777 |
void *puc) |
|
| 778 |
{
|
|
| 779 |
TranslationBlock *tb; |
|
| 780 |
int ret; |
|
| 781 |
|
|
| 782 |
if (cpu_single_env) {
|
|
| 783 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
|
| 784 |
} |
|
| 785 |
#if defined(DEBUG_SIGNAL) |
|
| 786 |
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
| 787 |
pc, address, is_write, *(unsigned long *)old_set); |
|
| 788 |
#endif |
|
| 789 |
/* XXX: locking issue */ |
|
| 790 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
|
| 791 |
return 1; |
|
| 792 |
} |
|
| 793 |
|
|
| 794 |
/* see if it is an MMU fault */ |
|
| 795 |
ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
|
| 796 |
if (ret < 0) {
|
|
| 797 |
return 0; /* not an MMU fault */ |
|
| 798 |
} |
|
| 799 |
if (ret == 0) {
|
|
| 800 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
|
| 801 |
} |
|
| 802 |
/* now we have a real cpu fault */ |
|
| 803 |
tb = tb_find_pc(pc); |
|
| 804 |
if (tb) {
|
|
| 805 |
/* the PC is inside the translated code. It means that we have |
|
| 806 |
a virtual CPU fault */ |
|
| 807 |
cpu_restore_state(tb, env, pc); |
|
| 808 |
} |
|
| 809 |
|
|
| 810 |
/* we restore the process signal mask as the sigreturn should |
|
| 811 |
do it (XXX: use sigsetjmp) */ |
|
| 812 |
sigprocmask(SIG_SETMASK, old_set, NULL); |
|
| 813 |
EXCEPTION_ACTION; |
|
| 814 |
|
|
| 815 |
/* never comes here */ |
|
| 816 |
return 1; |
|
| 817 |
} |
|
| 818 |
|
|
| 819 |
#if defined(__i386__) |
|
| 820 |
|
|
| 821 |
#if defined(__APPLE__) |
|
| 822 |
#include <sys/ucontext.h> |
|
| 823 |
|
|
| 824 |
#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip)) |
|
| 825 |
#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno) |
|
| 826 |
#define ERROR_sig(context) ((context)->uc_mcontext->es.err) |
|
| 827 |
#define MASK_sig(context) ((context)->uc_sigmask) |
|
| 828 |
#elif defined(__NetBSD__) |
|
| 829 |
#include <ucontext.h> |
|
| 830 |
|
|
| 831 |
#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) |
|
| 832 |
#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) |
|
| 833 |
#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) |
|
| 834 |
#define MASK_sig(context) ((context)->uc_sigmask) |
|
| 835 |
#elif defined(__FreeBSD__) || defined(__DragonFly__) |
|
| 836 |
#include <ucontext.h> |
|
| 837 |
|
|
| 838 |
#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) |
|
| 839 |
#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) |
|
| 840 |
#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) |
|
| 841 |
#define MASK_sig(context) ((context)->uc_sigmask) |
|
| 842 |
#elif defined(__OpenBSD__) |
|
| 843 |
#define EIP_sig(context) ((context)->sc_eip) |
|
| 844 |
#define TRAP_sig(context) ((context)->sc_trapno) |
|
| 845 |
#define ERROR_sig(context) ((context)->sc_err) |
|
| 846 |
#define MASK_sig(context) ((context)->sc_mask) |
|
| 847 |
#else |
|
| 848 |
#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) |
|
| 849 |
#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
|
| 850 |
#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
|
| 851 |
#define MASK_sig(context) ((context)->uc_sigmask) |
|
| 852 |
#endif |
|
| 853 |
|
|
| 854 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 855 |
void *puc) |
|
| 856 |
{
|
|
| 857 |
siginfo_t *info = pinfo; |
|
| 858 |
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) |
|
| 859 |
ucontext_t *uc = puc; |
|
| 860 |
#elif defined(__OpenBSD__) |
|
| 861 |
struct sigcontext *uc = puc; |
|
| 862 |
#else |
|
| 863 |
struct ucontext *uc = puc; |
|
| 864 |
#endif |
|
| 865 |
unsigned long pc; |
|
| 866 |
int trapno; |
|
| 867 |
|
|
| 868 |
#ifndef REG_EIP |
|
| 869 |
/* for glibc 2.1 */ |
|
| 870 |
#define REG_EIP EIP |
|
| 871 |
#define REG_ERR ERR |
|
| 872 |
#define REG_TRAPNO TRAPNO |
|
| 873 |
#endif |
|
| 874 |
pc = EIP_sig(uc); |
|
| 875 |
trapno = TRAP_sig(uc); |
|
| 876 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 877 |
trapno == 0xe ? |
|
| 878 |
(ERROR_sig(uc) >> 1) & 1 : 0, |
|
| 879 |
&MASK_sig(uc), puc); |
|
| 880 |
} |
|
| 881 |
|
|
| 882 |
#elif defined(__x86_64__) |
|
| 883 |
|
|
| 884 |
#ifdef __NetBSD__ |
|
| 885 |
#define PC_sig(context) _UC_MACHINE_PC(context) |
|
| 886 |
#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) |
|
| 887 |
#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) |
|
| 888 |
#define MASK_sig(context) ((context)->uc_sigmask) |
|
| 889 |
#elif defined(__OpenBSD__) |
|
| 890 |
#define PC_sig(context) ((context)->sc_rip) |
|
| 891 |
#define TRAP_sig(context) ((context)->sc_trapno) |
|
| 892 |
#define ERROR_sig(context) ((context)->sc_err) |
|
| 893 |
#define MASK_sig(context) ((context)->sc_mask) |
|
| 894 |
#elif defined(__FreeBSD__) || defined(__DragonFly__) |
|
| 895 |
#include <ucontext.h> |
|
| 896 |
|
|
| 897 |
#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) |
|
| 898 |
#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) |
|
| 899 |
#define ERROR_sig(context) ((context)->uc_mcontext.mc_err) |
|
| 900 |
#define MASK_sig(context) ((context)->uc_sigmask) |
|
| 901 |
#else |
|
| 902 |
#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) |
|
| 903 |
#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
|
| 904 |
#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
|
| 905 |
#define MASK_sig(context) ((context)->uc_sigmask) |
|
| 906 |
#endif |
|
| 907 |
|
|
| 908 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 909 |
void *puc) |
|
| 910 |
{
|
|
| 911 |
siginfo_t *info = pinfo; |
|
| 912 |
unsigned long pc; |
|
| 913 |
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) |
|
| 914 |
ucontext_t *uc = puc; |
|
| 915 |
#elif defined(__OpenBSD__) |
|
| 916 |
struct sigcontext *uc = puc; |
|
| 917 |
#else |
|
| 918 |
struct ucontext *uc = puc; |
|
| 919 |
#endif |
|
| 920 |
|
|
| 921 |
pc = PC_sig(uc); |
|
| 922 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 923 |
TRAP_sig(uc) == 0xe ? |
|
| 924 |
(ERROR_sig(uc) >> 1) & 1 : 0, |
|
| 925 |
&MASK_sig(uc), puc); |
|
| 926 |
} |
|
| 927 |
|
|
| 928 |
#elif defined(_ARCH_PPC) |
|
| 929 |
|
|
| 930 |
/*********************************************************************** |
|
| 931 |
* signal context platform-specific definitions |
|
| 932 |
* From Wine |
|
| 933 |
*/ |
|
| 934 |
#ifdef linux |
|
| 935 |
/* All Registers access - only for local access */ |
|
| 936 |
#define REG_sig(reg_name, context) \ |
|
| 937 |
((context)->uc_mcontext.regs->reg_name) |
|
| 938 |
/* Gpr Registers access */ |
|
| 939 |
#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) |
|
| 940 |
/* Program counter */ |
|
| 941 |
#define IAR_sig(context) REG_sig(nip, context) |
|
| 942 |
/* Machine State Register (Supervisor) */ |
|
| 943 |
#define MSR_sig(context) REG_sig(msr, context) |
|
| 944 |
/* Count register */ |
|
| 945 |
#define CTR_sig(context) REG_sig(ctr, context) |
|
| 946 |
/* User's integer exception register */ |
|
| 947 |
#define XER_sig(context) REG_sig(xer, context) |
|
| 948 |
/* Link register */ |
|
| 949 |
#define LR_sig(context) REG_sig(link, context) |
|
| 950 |
/* Condition register */ |
|
| 951 |
#define CR_sig(context) REG_sig(ccr, context) |
|
| 952 |
|
|
| 953 |
/* Float Registers access */ |
|
| 954 |
#define FLOAT_sig(reg_num, context) \ |
|
| 955 |
(((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) |
|
| 956 |
#define FPSCR_sig(context) \ |
|
| 957 |
(*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) |
|
| 958 |
/* Exception Registers access */ |
|
| 959 |
#define DAR_sig(context) REG_sig(dar, context) |
|
| 960 |
#define DSISR_sig(context) REG_sig(dsisr, context) |
|
| 961 |
#define TRAP_sig(context) REG_sig(trap, context) |
|
| 962 |
#endif /* linux */ |
|
| 963 |
|
|
| 964 |
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
|
| 965 |
#include <ucontext.h> |
|
| 966 |
#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) |
|
| 967 |
#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) |
|
| 968 |
#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) |
|
| 969 |
#define XER_sig(context) ((context)->uc_mcontext.mc_xer) |
|
| 970 |
#define LR_sig(context) ((context)->uc_mcontext.mc_lr) |
|
| 971 |
#define CR_sig(context) ((context)->uc_mcontext.mc_cr) |
|
| 972 |
/* Exception Registers access */ |
|
| 973 |
#define DAR_sig(context) ((context)->uc_mcontext.mc_dar) |
|
| 974 |
#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) |
|
| 975 |
#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) |
|
| 976 |
#endif /* __FreeBSD__|| __FreeBSD_kernel__ */ |
|
| 977 |
|
|
| 978 |
#ifdef __APPLE__ |
|
| 979 |
#include <sys/ucontext.h> |
|
| 980 |
typedef struct ucontext SIGCONTEXT; |
|
| 981 |
/* All Registers access - only for local access */ |
|
| 982 |
#define REG_sig(reg_name, context) \ |
|
| 983 |
((context)->uc_mcontext->ss.reg_name) |
|
| 984 |
#define FLOATREG_sig(reg_name, context) \ |
|
| 985 |
((context)->uc_mcontext->fs.reg_name) |
|
| 986 |
#define EXCEPREG_sig(reg_name, context) \ |
|
| 987 |
((context)->uc_mcontext->es.reg_name) |
|
| 988 |
#define VECREG_sig(reg_name, context) \ |
|
| 989 |
((context)->uc_mcontext->vs.reg_name) |
|
| 990 |
/* Gpr Registers access */ |
|
| 991 |
#define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
|
| 992 |
/* Program counter */ |
|
| 993 |
#define IAR_sig(context) REG_sig(srr0, context) |
|
| 994 |
/* Machine State Register (Supervisor) */ |
|
| 995 |
#define MSR_sig(context) REG_sig(srr1, context) |
|
| 996 |
#define CTR_sig(context) REG_sig(ctr, context) |
|
| 997 |
/* Link register */ |
|
| 998 |
#define XER_sig(context) REG_sig(xer, context) |
|
| 999 |
/* User's integer exception register */ |
|
| 1000 |
#define LR_sig(context) REG_sig(lr, context) |
|
| 1001 |
/* Condition register */ |
|
| 1002 |
#define CR_sig(context) REG_sig(cr, context) |
|
| 1003 |
/* Float Registers access */ |
|
| 1004 |
#define FLOAT_sig(reg_num, context) \ |
|
| 1005 |
FLOATREG_sig(fpregs[reg_num], context) |
|
| 1006 |
#define FPSCR_sig(context) \ |
|
| 1007 |
((double)FLOATREG_sig(fpscr, context)) |
|
| 1008 |
/* Exception Registers access */ |
|
| 1009 |
/* Fault registers for coredump */ |
|
| 1010 |
#define DAR_sig(context) EXCEPREG_sig(dar, context) |
|
| 1011 |
#define DSISR_sig(context) EXCEPREG_sig(dsisr, context) |
|
| 1012 |
/* number of powerpc exception taken */ |
|
| 1013 |
#define TRAP_sig(context) EXCEPREG_sig(exception, context) |
|
| 1014 |
#endif /* __APPLE__ */ |
|
| 1015 |
|
|
| 1016 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1017 |
void *puc) |
|
| 1018 |
{
|
|
| 1019 |
siginfo_t *info = pinfo; |
|
| 1020 |
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
|
| 1021 |
ucontext_t *uc = puc; |
|
| 1022 |
#else |
|
| 1023 |
struct ucontext *uc = puc; |
|
| 1024 |
#endif |
|
| 1025 |
unsigned long pc; |
|
| 1026 |
int is_write; |
|
| 1027 |
|
|
| 1028 |
pc = IAR_sig(uc); |
|
| 1029 |
is_write = 0; |
|
| 1030 |
#if 0 |
|
| 1031 |
/* ppc 4xx case */ |
|
| 1032 |
if (DSISR_sig(uc) & 0x00800000) {
|
|
| 1033 |
is_write = 1; |
|
| 1034 |
} |
|
| 1035 |
#else |
|
| 1036 |
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
|
|
| 1037 |
is_write = 1; |
|
| 1038 |
} |
|
| 1039 |
#endif |
|
| 1040 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1041 |
is_write, &uc->uc_sigmask, puc); |
|
| 1042 |
} |
|
| 1043 |
|
|
| 1044 |
#elif defined(__alpha__) |
|
| 1045 |
|
|
| 1046 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1047 |
void *puc) |
|
| 1048 |
{
|
|
| 1049 |
siginfo_t *info = pinfo; |
|
| 1050 |
struct ucontext *uc = puc; |
|
| 1051 |
uint32_t *pc = uc->uc_mcontext.sc_pc; |
|
| 1052 |
uint32_t insn = *pc; |
|
| 1053 |
int is_write = 0; |
|
| 1054 |
|
|
| 1055 |
/* XXX: need kernel patch to get write flag faster */ |
|
| 1056 |
switch (insn >> 26) {
|
|
| 1057 |
case 0x0d: /* stw */ |
|
| 1058 |
case 0x0e: /* stb */ |
|
| 1059 |
case 0x0f: /* stq_u */ |
|
| 1060 |
case 0x24: /* stf */ |
|
| 1061 |
case 0x25: /* stg */ |
|
| 1062 |
case 0x26: /* sts */ |
|
| 1063 |
case 0x27: /* stt */ |
|
| 1064 |
case 0x2c: /* stl */ |
|
| 1065 |
case 0x2d: /* stq */ |
|
| 1066 |
case 0x2e: /* stl_c */ |
|
| 1067 |
case 0x2f: /* stq_c */ |
|
| 1068 |
is_write = 1; |
|
| 1069 |
} |
|
| 1070 |
|
|
| 1071 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1072 |
is_write, &uc->uc_sigmask, puc); |
|
| 1073 |
} |
|
| 1074 |
#elif defined(__sparc__) |
|
| 1075 |
|
|
| 1076 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1077 |
void *puc) |
|
| 1078 |
{
|
|
| 1079 |
siginfo_t *info = pinfo; |
|
| 1080 |
int is_write; |
|
| 1081 |
uint32_t insn; |
|
| 1082 |
#if !defined(__arch64__) || defined(CONFIG_SOLARIS) |
|
| 1083 |
uint32_t *regs = (uint32_t *)(info + 1); |
|
| 1084 |
void *sigmask = (regs + 20); |
|
| 1085 |
/* XXX: is there a standard glibc define ? */ |
|
| 1086 |
unsigned long pc = regs[1]; |
|
| 1087 |
#else |
|
| 1088 |
#ifdef __linux__ |
|
| 1089 |
struct sigcontext *sc = puc; |
|
| 1090 |
unsigned long pc = sc->sigc_regs.tpc; |
|
| 1091 |
void *sigmask = (void *)sc->sigc_mask; |
|
| 1092 |
#elif defined(__OpenBSD__) |
|
| 1093 |
struct sigcontext *uc = puc; |
|
| 1094 |
unsigned long pc = uc->sc_pc; |
|
| 1095 |
void *sigmask = (void *)(long)uc->sc_mask; |
|
| 1096 |
#endif |
|
| 1097 |
#endif |
|
| 1098 |
|
|
| 1099 |
/* XXX: need kernel patch to get write flag faster */ |
|
| 1100 |
is_write = 0; |
|
| 1101 |
insn = *(uint32_t *)pc; |
|
| 1102 |
if ((insn >> 30) == 3) {
|
|
| 1103 |
switch ((insn >> 19) & 0x3f) {
|
|
| 1104 |
case 0x05: /* stb */ |
|
| 1105 |
case 0x15: /* stba */ |
|
| 1106 |
case 0x06: /* sth */ |
|
| 1107 |
case 0x16: /* stha */ |
|
| 1108 |
case 0x04: /* st */ |
|
| 1109 |
case 0x14: /* sta */ |
|
| 1110 |
case 0x07: /* std */ |
|
| 1111 |
case 0x17: /* stda */ |
|
| 1112 |
case 0x0e: /* stx */ |
|
| 1113 |
case 0x1e: /* stxa */ |
|
| 1114 |
case 0x24: /* stf */ |
|
| 1115 |
case 0x34: /* stfa */ |
|
| 1116 |
case 0x27: /* stdf */ |
|
| 1117 |
case 0x37: /* stdfa */ |
|
| 1118 |
case 0x26: /* stqf */ |
|
| 1119 |
case 0x36: /* stqfa */ |
|
| 1120 |
case 0x25: /* stfsr */ |
|
| 1121 |
case 0x3c: /* casa */ |
|
| 1122 |
case 0x3e: /* casxa */ |
|
| 1123 |
is_write = 1; |
|
| 1124 |
break; |
|
| 1125 |
} |
|
| 1126 |
} |
|
| 1127 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1128 |
is_write, sigmask, NULL); |
|
| 1129 |
} |
|
| 1130 |
|
|
| 1131 |
#elif defined(__arm__) |
|
| 1132 |
|
|
| 1133 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1134 |
void *puc) |
|
| 1135 |
{
|
|
| 1136 |
siginfo_t *info = pinfo; |
|
| 1137 |
struct ucontext *uc = puc; |
|
| 1138 |
unsigned long pc; |
|
| 1139 |
int is_write; |
|
| 1140 |
|
|
| 1141 |
#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) |
|
| 1142 |
pc = uc->uc_mcontext.gregs[R15]; |
|
| 1143 |
#else |
|
| 1144 |
pc = uc->uc_mcontext.arm_pc; |
|
| 1145 |
#endif |
|
| 1146 |
/* XXX: compute is_write */ |
|
| 1147 |
is_write = 0; |
|
| 1148 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1149 |
is_write, |
|
| 1150 |
&uc->uc_sigmask, puc); |
|
| 1151 |
} |
|
| 1152 |
|
|
| 1153 |
#elif defined(__mc68000) |
|
| 1154 |
|
|
| 1155 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1156 |
void *puc) |
|
| 1157 |
{
|
|
| 1158 |
siginfo_t *info = pinfo; |
|
| 1159 |
struct ucontext *uc = puc; |
|
| 1160 |
unsigned long pc; |
|
| 1161 |
int is_write; |
|
| 1162 |
|
|
| 1163 |
pc = uc->uc_mcontext.gregs[16]; |
|
| 1164 |
/* XXX: compute is_write */ |
|
| 1165 |
is_write = 0; |
|
| 1166 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1167 |
is_write, |
|
| 1168 |
&uc->uc_sigmask, puc); |
|
| 1169 |
} |
|
| 1170 |
|
|
| 1171 |
#elif defined(__ia64) |
|
| 1172 |
|
|
| 1173 |
#ifndef __ISR_VALID |
|
| 1174 |
/* This ought to be in <bits/siginfo.h>... */ |
|
| 1175 |
# define __ISR_VALID 1 |
|
| 1176 |
#endif |
|
| 1177 |
|
|
| 1178 |
int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
|
| 1179 |
{
|
|
| 1180 |
siginfo_t *info = pinfo; |
|
| 1181 |
struct ucontext *uc = puc; |
|
| 1182 |
unsigned long ip; |
|
| 1183 |
int is_write = 0; |
|
| 1184 |
|
|
| 1185 |
ip = uc->uc_mcontext.sc_ip; |
|
| 1186 |
switch (host_signum) {
|
|
| 1187 |
case SIGILL: |
|
| 1188 |
case SIGFPE: |
|
| 1189 |
case SIGSEGV: |
|
| 1190 |
case SIGBUS: |
|
| 1191 |
case SIGTRAP: |
|
| 1192 |
if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
|
|
| 1193 |
/* ISR.W (write-access) is bit 33: */ |
|
| 1194 |
is_write = (info->si_isr >> 33) & 1; |
|
| 1195 |
} |
|
| 1196 |
break; |
|
| 1197 |
|
|
| 1198 |
default: |
|
| 1199 |
break; |
|
| 1200 |
} |
|
| 1201 |
return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
|
| 1202 |
is_write, |
|
| 1203 |
(sigset_t *)&uc->uc_sigmask, puc); |
|
| 1204 |
} |
|
| 1205 |
|
|
| 1206 |
#elif defined(__s390__) |
|
| 1207 |
|
|
| 1208 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1209 |
void *puc) |
|
| 1210 |
{
|
|
| 1211 |
siginfo_t *info = pinfo; |
|
| 1212 |
struct ucontext *uc = puc; |
|
| 1213 |
unsigned long pc; |
|
| 1214 |
uint16_t *pinsn; |
|
| 1215 |
int is_write = 0; |
|
| 1216 |
|
|
| 1217 |
pc = uc->uc_mcontext.psw.addr; |
|
| 1218 |
|
|
| 1219 |
/* ??? On linux, the non-rt signal handler has 4 (!) arguments instead |
|
| 1220 |
of the normal 2 arguments. The 3rd argument contains the "int_code" |
|
| 1221 |
from the hardware which does in fact contain the is_write value. |
|
| 1222 |
The rt signal handler, as far as I can tell, does not give this value |
|
| 1223 |
at all. Not that we could get to it from here even if it were. */ |
|
| 1224 |
/* ??? This is not even close to complete, since it ignores all |
|
| 1225 |
of the read-modify-write instructions. */ |
|
| 1226 |
pinsn = (uint16_t *)pc; |
|
| 1227 |
switch (pinsn[0] >> 8) {
|
|
| 1228 |
case 0x50: /* ST */ |
|
| 1229 |
case 0x42: /* STC */ |
|
| 1230 |
case 0x40: /* STH */ |
|
| 1231 |
is_write = 1; |
|
| 1232 |
break; |
|
| 1233 |
case 0xc4: /* RIL format insns */ |
|
| 1234 |
switch (pinsn[0] & 0xf) {
|
|
| 1235 |
case 0xf: /* STRL */ |
|
| 1236 |
case 0xb: /* STGRL */ |
|
| 1237 |
case 0x7: /* STHRL */ |
|
| 1238 |
is_write = 1; |
|
| 1239 |
} |
|
| 1240 |
break; |
|
| 1241 |
case 0xe3: /* RXY format insns */ |
|
| 1242 |
switch (pinsn[2] & 0xff) {
|
|
| 1243 |
case 0x50: /* STY */ |
|
| 1244 |
case 0x24: /* STG */ |
|
| 1245 |
case 0x72: /* STCY */ |
|
| 1246 |
case 0x70: /* STHY */ |
|
| 1247 |
case 0x8e: /* STPQ */ |
|
| 1248 |
case 0x3f: /* STRVH */ |
|
| 1249 |
case 0x3e: /* STRV */ |
|
| 1250 |
case 0x2f: /* STRVG */ |
|
| 1251 |
is_write = 1; |
|
| 1252 |
} |
|
| 1253 |
break; |
|
| 1254 |
} |
|
| 1255 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1256 |
is_write, &uc->uc_sigmask, puc); |
|
| 1257 |
} |
|
| 1258 |
|
|
| 1259 |
#elif defined(__mips__) |
|
| 1260 |
|
|
| 1261 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1262 |
void *puc) |
|
| 1263 |
{
|
|
| 1264 |
siginfo_t *info = pinfo; |
|
| 1265 |
struct ucontext *uc = puc; |
|
| 1266 |
greg_t pc = uc->uc_mcontext.pc; |
|
| 1267 |
int is_write; |
|
| 1268 |
|
|
| 1269 |
/* XXX: compute is_write */ |
|
| 1270 |
is_write = 0; |
|
| 1271 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1272 |
is_write, &uc->uc_sigmask, puc); |
|
| 1273 |
} |
|
| 1274 |
|
|
| 1275 |
#elif defined(__hppa__) |
|
| 1276 |
|
|
| 1277 |
int cpu_signal_handler(int host_signum, void *pinfo, |
|
| 1278 |
void *puc) |
|
| 1279 |
{
|
|
| 1280 |
struct siginfo *info = pinfo; |
|
| 1281 |
struct ucontext *uc = puc; |
|
| 1282 |
unsigned long pc = uc->uc_mcontext.sc_iaoq[0]; |
|
| 1283 |
uint32_t insn = *(uint32_t *)pc; |
|
| 1284 |
int is_write = 0; |
|
| 1285 |
|
|
| 1286 |
/* XXX: need kernel patch to get write flag faster. */ |
|
| 1287 |
switch (insn >> 26) {
|
|
| 1288 |
case 0x1a: /* STW */ |
|
| 1289 |
case 0x19: /* STH */ |
|
| 1290 |
case 0x18: /* STB */ |
|
| 1291 |
case 0x1b: /* STWM */ |
|
| 1292 |
is_write = 1; |
|
| 1293 |
break; |
|
| 1294 |
|
|
| 1295 |
case 0x09: /* CSTWX, FSTWX, FSTWS */ |
|
| 1296 |
case 0x0b: /* CSTDX, FSTDX, FSTDS */ |
|
| 1297 |
/* Distinguish from coprocessor load ... */ |
|
| 1298 |
is_write = (insn >> 9) & 1; |
|
| 1299 |
break; |
|
| 1300 |
|
|
| 1301 |
case 0x03: |
|
| 1302 |
switch ((insn >> 6) & 15) {
|
|
| 1303 |
case 0xa: /* STWS */ |
|
| 1304 |
case 0x9: /* STHS */ |
|
| 1305 |
case 0x8: /* STBS */ |
|
| 1306 |
case 0xe: /* STWAS */ |
|
| 1307 |
case 0xc: /* STBYS */ |
|
| 1308 |
is_write = 1; |
|
| 1309 |
} |
|
| 1310 |
break; |
|
| 1311 |
} |
|
| 1312 |
|
|
| 1313 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
|
| 1314 |
is_write, &uc->uc_sigmask, puc); |
|
| 1315 |
} |
|
| 1316 |
|
|
| 1317 |
#else |
|
| 1318 |
|
|
| 1319 |
#error host CPU specific signal handler needed |
|
| 1320 |
|
|
| 1321 |
#endif |
|
| 1322 |
|
|
| 1323 |
#endif /* !defined(CONFIG_SOFTMMU) */ |
|
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