Revision 42fc73a1
| b/hw/mc146818rtc.c | ||
|---|---|---|
| 60 | 60 |
uint8_t cmos_data[128]; |
| 61 | 61 |
uint8_t cmos_index; |
| 62 | 62 |
struct tm current_tm; |
| 63 |
int base_year; |
|
| 63 | 64 |
qemu_irq irq; |
| 64 | 65 |
int it_shift; |
| 65 | 66 |
/* periodic timer */ |
| ... | ... | |
| 235 | 236 |
tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
| 236 | 237 |
tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
| 237 | 238 |
tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; |
| 238 |
tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
|
|
| 239 |
tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
|
|
| 239 | 240 |
} |
| 240 | 241 |
|
| 241 | 242 |
static void rtc_copy_date(RTCState *s) |
| 242 | 243 |
{
|
| 243 | 244 |
const struct tm *tm = &s->current_tm; |
| 245 |
int year; |
|
| 244 | 246 |
|
| 245 | 247 |
s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
| 246 | 248 |
s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
| ... | ... | |
| 256 | 258 |
s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1); |
| 257 | 259 |
s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
| 258 | 260 |
s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1); |
| 259 |
s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100); |
|
| 261 |
year = (tm->tm_year - s->base_year) % 100; |
|
| 262 |
if (year < 0) |
|
| 263 |
year += 100; |
|
| 264 |
s->cmos_data[RTC_YEAR] = to_bcd(s, year); |
|
| 260 | 265 |
} |
| 261 | 266 |
|
| 262 | 267 |
/* month is between 0 and 11. */ |
| ... | ... | |
| 522 | 527 |
} |
| 523 | 528 |
#endif |
| 524 | 529 |
|
| 525 |
RTCState *rtc_init(int base, qemu_irq irq) |
|
| 530 |
RTCState *rtc_init(int base, qemu_irq irq, int base_year)
|
|
| 526 | 531 |
{
|
| 527 | 532 |
RTCState *s; |
| 528 | 533 |
|
| ... | ... | |
| 536 | 541 |
s->cmos_data[RTC_REG_C] = 0x00; |
| 537 | 542 |
s->cmos_data[RTC_REG_D] = 0x80; |
| 538 | 543 |
|
| 544 |
s->base_year = base_year; |
|
| 539 | 545 |
rtc_set_date_from_host(s); |
| 540 | 546 |
|
| 541 | 547 |
s->periodic_timer = qemu_new_timer(vm_clock, |
| ... | ... | |
| 631 | 637 |
&cmos_mm_writel, |
| 632 | 638 |
}; |
| 633 | 639 |
|
| 634 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq) |
|
| 640 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, |
|
| 641 |
int base_year) |
|
| 635 | 642 |
{
|
| 636 | 643 |
RTCState *s; |
| 637 | 644 |
int io_memory; |
| ... | ... | |
| 646 | 653 |
s->cmos_data[RTC_REG_C] = 0x00; |
| 647 | 654 |
s->cmos_data[RTC_REG_D] = 0x80; |
| 648 | 655 |
|
| 656 |
s->base_year = base_year; |
|
| 649 | 657 |
rtc_set_date_from_host(s); |
| 650 | 658 |
|
| 651 | 659 |
s->periodic_timer = qemu_new_timer(vm_clock, |
| b/hw/mips_jazz.c | ||
|---|---|---|
| 241 | 241 |
fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds); |
| 242 | 242 |
|
| 243 | 243 |
/* Real time clock */ |
| 244 |
rtc_init(0x70, i8259[8]); |
|
| 244 |
rtc_init(0x70, i8259[8], 1980);
|
|
| 245 | 245 |
s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env); |
| 246 | 246 |
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); |
| 247 | 247 |
|
| b/hw/mips_malta.c | ||
|---|---|---|
| 918 | 918 |
|
| 919 | 919 |
/* Super I/O */ |
| 920 | 920 |
i8042_init(i8259[1], i8259[12], 0x60); |
| 921 |
rtc_state = rtc_init(0x70, i8259[8]); |
|
| 921 |
rtc_state = rtc_init(0x70, i8259[8], 2000);
|
|
| 922 | 922 |
serial_init(0x3f8, i8259[4], 115200, serial_hds[0]); |
| 923 | 923 |
serial_init(0x2f8, i8259[3], 115200, serial_hds[1]); |
| 924 | 924 |
if (parallel_hds[0]) |
| b/hw/mips_r4k.c | ||
|---|---|---|
| 235 | 235 |
/* The PIC is attached to the MIPS CPU INT0 pin */ |
| 236 | 236 |
i8259 = i8259_init(env->irq[2]); |
| 237 | 237 |
|
| 238 |
rtc_state = rtc_init(0x70, i8259[8]); |
|
| 238 |
rtc_state = rtc_init(0x70, i8259[8], 2000);
|
|
| 239 | 239 |
|
| 240 | 240 |
/* Register 64 KB of ISA IO space at 0x14000000 */ |
| 241 | 241 |
isa_mmio_init(0x14000000, 0x00010000); |
| b/hw/pc.c | ||
|---|---|---|
| 968 | 968 |
} |
| 969 | 969 |
} |
| 970 | 970 |
|
| 971 |
rtc_state = rtc_init(0x70, i8259[8]); |
|
| 971 |
rtc_state = rtc_init(0x70, i8259[8], 2000);
|
|
| 972 | 972 |
|
| 973 | 973 |
qemu_register_boot_set(pc_boot_set, rtc_state); |
| 974 | 974 |
|
| b/hw/pc.h | ||
|---|---|---|
| 83 | 83 |
|
| 84 | 84 |
typedef struct RTCState RTCState; |
| 85 | 85 |
|
| 86 |
RTCState *rtc_init(int base, qemu_irq irq); |
|
| 87 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq); |
|
| 86 |
RTCState *rtc_init(int base, qemu_irq irq, int base_year); |
|
| 87 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, |
|
| 88 |
int base_year); |
|
| 88 | 89 |
void rtc_set_memory(RTCState *s, int addr, int val); |
| 89 | 90 |
void rtc_set_date(RTCState *s, const struct tm *tm); |
| 90 | 91 |
void cmos_set_s3_resume(void); |
| b/hw/ppc_prep.c | ||
|---|---|---|
| 659 | 659 |
vga_ram_size, 0, 0); |
| 660 | 660 |
// openpic = openpic_init(0x00000000, 0xF0000000, 1); |
| 661 | 661 |
// pit = pit_init(0x40, i8259[0]); |
| 662 |
rtc_init(0x70, i8259[8]); |
|
| 662 |
rtc_init(0x70, i8259[8], 2000);
|
|
| 663 | 663 |
|
| 664 | 664 |
serial_init(0x3f8, i8259[4], 115200, serial_hds[0]); |
| 665 | 665 |
nb_nics1 = nb_nics; |
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