Revision 43057ab1 target-mips/helper.c
| b/target-mips/helper.c | ||
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#include "cpu.h" |
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#include "exec-all.h" |
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|
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enum {
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TLBRET_DIRTY = -4, |
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TLBRET_INVALID = -3, |
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TLBRET_NOMATCH = -2, |
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TLBRET_BADADDR = -1, |
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TLBRET_MATCH = 0 |
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}; |
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/* MIPS32 4K MMU emulation */ |
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#ifdef MIPS_USES_R4K_TLB |
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static int map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{
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target_ulong tag = address & (TARGET_PAGE_MASK << 1); |
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uint8_t ASID = env->CP0_EntryHi & 0xFF; |
|
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tlb_t *tlb; |
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target_ulong tag; |
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uint8_t ASID; |
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int i, n; |
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int ret; |
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ret = -2; |
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tag = address & 0xFFFFE000; |
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ASID = env->CP0_EntryHi & 0xFF; |
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for (i = 0; i < MIPS_TLB_NB; i++) {
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tlb = &env->tlb[i]; |
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/* Check ASID, virtual page number & size */ |
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if ((tlb->G == 1 || tlb->ASID == ASID) && |
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tlb->VPN == tag && address < tlb->end2) {
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/* TLB match */ |
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n = (address >> 12) & 1;
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n = (address >> TARGET_PAGE_BITS) & 1;
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/* Check access rights */ |
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if (!(n ? tlb->V1 : tlb->V0))
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return -3;
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if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
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*physical = tlb->PFN[n] | (address & 0xFFF);
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if (!(n ? tlb->V1 : tlb->V0))
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return TLBRET_INVALID;
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if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
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*physical = tlb->PFN[n] | (address & ~TARGET_PAGE_MASK);
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*prot = PAGE_READ; |
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if (n ? tlb->D1 : tlb->D0) |
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*prot |= PAGE_WRITE; |
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return 0;
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return TLBRET_MATCH;
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} |
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return -4;
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return TLBRET_DIRTY;
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} |
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} |
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return ret; |
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return TLBRET_NOMATCH; |
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} |
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#endif |
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int get_physical_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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static int get_physical_address (CPUState *env, target_ulong *physical, |
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int *prot, target_ulong address, |
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int rw, int access_type) |
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{
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int user_mode; |
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int ret; |
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/* User mode can only access useg */ |
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user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
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int ret = TLBRET_MATCH; |
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#if 0 |
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if (logfile) {
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fprintf(logfile, "user mode %d h %08x\n", |
| ... | ... | |
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} |
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#endif |
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if (user_mode && address > 0x7FFFFFFFUL) |
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return -1; |
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ret = 0; |
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return TLBRET_BADADDR; |
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if (address < 0x80000000UL) {
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if (!(env->hflags & MIPS_HFLAG_ERL)) {
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#ifdef MIPS_USES_R4K_TLB |
| ... | ... | |
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access_type = ACCESS_INT; |
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if (env->user_mode_only) {
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/* user mode only emulation */ |
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ret = -2;
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ret = TLBRET_NOMATCH;
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goto do_fault; |
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} |
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ret = get_physical_address(env, &physical, &prot, |
| ... | ... | |
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fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n", |
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__func__, address, ret, physical, prot); |
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} |
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if (ret == 0) {
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ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot, |
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is_user, is_softmmu); |
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if (ret == TLBRET_MATCH) {
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ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
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physical & TARGET_PAGE_MASK, prot, |
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is_user, is_softmmu); |
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} else if (ret < 0) {
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do_fault: |
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switch (ret) {
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default: |
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case -1:
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case TLBRET_BADADDR:
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/* Reference to kernel address from user mode or supervisor mode */ |
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/* Reference to supervisor address from user mode */ |
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if (rw) |
| ... | ... | |
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else |
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exception = EXCP_AdEL; |
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break; |
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case -2:
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */ |
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if (rw) |
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exception = EXCP_TLBS; |
| ... | ... | |
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exception = EXCP_TLBL; |
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error_code = 1; |
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break; |
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case -3:
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case TLBRET_INVALID:
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/* TLB match with no valid bit */ |
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if (rw) |
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exception = EXCP_TLBS; |
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else |
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exception = EXCP_TLBL; |
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break; |
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case -4:
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case TLBRET_DIRTY:
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/* TLB match but 'D' bit is cleared */ |
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exception = EXCP_LTLBL; |
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break; |
| ... | ... | |
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env->CP0_Context = (env->CP0_Context & 0xff800000) | |
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((address >> 9) & 0x007ffff0); |
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env->CP0_EntryHi = |
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(env->CP0_EntryHi & 0xFF) | (address & 0xFFFFE000);
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(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
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env->exception_index = exception; |
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env->error_code = error_code; |
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ret = 1; |
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