Revision 434254aa tcg/mips/tcg-target.c

b/tcg/mips/tcg-target.c
595 595
        } else if (arg2 == 0) {
596 596
            tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
597 597
        } else {
598
            tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, arg1, arg2);
599
            tcg_out_opc_imm(s, OPC_SLTIU, ret, TCG_REG_AT, 1);
598
            tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
599
            tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
600 600
        }
601 601
        break;
602 602
    case TCG_COND_NE:
......
605 605
        } else if (arg2 == 0) {
606 606
            tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
607 607
        } else {
608
            tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, arg1, arg2);
609
            tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, TCG_REG_AT);
608
            tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
609
            tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
610 610
        }
611 611
        break;
612 612
    case TCG_COND_LT:
......
616 616
        tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
617 617
        break;
618 618
    case TCG_COND_GE:
619
        tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg1, arg2);
620
        tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
619
        tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
620
        tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
621 621
        break;
622 622
    case TCG_COND_GEU:
623
        tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg1, arg2);
624
        tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
623
        tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
624
        tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
625 625
        break;
626 626
    case TCG_COND_LE:
627
        tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, arg2, arg1);
628
        tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
627
        tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
628
        tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
629 629
        break;
630 630
    case TCG_COND_LEU:
631
        tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg2, arg1);
632
        tcg_out_opc_imm(s, OPC_XORI, ret, TCG_REG_AT, 1);
631
        tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
632
        tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
633 633
        break;
634 634
    case TCG_COND_GT:
635 635
        tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
......
643 643
    }
644 644
}
645 645

  
646
/* XXX: we implement it at the target level to avoid having to
647
   handle cross basic blocks temporaries */
648
static void tcg_out_setcond2(TCGContext *s, int cond, int ret,
649
                             int arg1, int arg2, int arg3, int arg4)
650
{
651
    switch (cond) {
652
    case TCG_COND_EQ:
653
        tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_AT, arg2, arg4);
654
        tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, arg1, arg3);
655
        tcg_out_opc_reg(s, OPC_AND, ret, TCG_REG_AT, TCG_REG_T0);
656
        return;
657
    case TCG_COND_NE:
658
        tcg_out_setcond(s, TCG_COND_NE, TCG_REG_AT, arg2, arg4);
659
        tcg_out_setcond(s, TCG_COND_NE, TCG_REG_T0, arg1, arg3);
660
        tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_AT, TCG_REG_T0);
661
        return;
662
    case TCG_COND_LT:
663
    case TCG_COND_LE:
664
        tcg_out_setcond(s, TCG_COND_LT, TCG_REG_AT, arg2, arg4);
665
        break;
666
    case TCG_COND_GT:
667
    case TCG_COND_GE:
668
        tcg_out_setcond(s, TCG_COND_GT, TCG_REG_AT, arg2, arg4);
669
        break;
670
    case TCG_COND_LTU:
671
    case TCG_COND_LEU:
672
        tcg_out_setcond(s, TCG_COND_LTU, TCG_REG_AT, arg2, arg4);
673
        break;
674
    case TCG_COND_GTU:
675
    case TCG_COND_GEU:
676
        tcg_out_setcond(s, TCG_COND_GTU, TCG_REG_AT, arg2, arg4);
677
        break;
678
    default:
679
        tcg_abort();
680
        break;
681
    }
682

  
683
    tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, arg2, arg4);
684

  
685
    switch(cond) {
686
    case TCG_COND_LT:
687
    case TCG_COND_LTU:
688
        tcg_out_setcond(s, TCG_COND_LTU, ret, arg1, arg3);
689
        break;
690
    case TCG_COND_LE:
691
    case TCG_COND_LEU:
692
        tcg_out_setcond(s, TCG_COND_LEU, ret, arg1, arg3);
693
        break;
694
    case TCG_COND_GT:
695
    case TCG_COND_GTU:
696
        tcg_out_setcond(s, TCG_COND_GTU, ret, arg1, arg3);
697
        break;
698
    case TCG_COND_GE:
699
    case TCG_COND_GEU:
700
        tcg_out_setcond(s, TCG_COND_GEU, ret, arg1, arg3);
701
        break;
702
    default:
703
        tcg_abort();
704
    }
705

  
706
    tcg_out_opc_reg(s, OPC_AND, ret, ret, TCG_REG_T0);
707
    tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
708
}
709

  
646 710
#if defined(CONFIG_SOFTMMU)
647 711

  
648 712
#include "../../softmmu_defs.h"
......
1218 1282
    case INDEX_op_setcond_i32:
1219 1283
        tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
1220 1284
        break;
1285
    case INDEX_op_setcond2_i32:
1286
        tcg_out_setcond2(s, args[5], args[0], args[1], args[2], args[3], args[4]);
1287
        break;
1221 1288

  
1222 1289
    case INDEX_op_qemu_ld8u:
1223 1290
        tcg_out_qemu_ld(s, args, 0);
......
1293 1360

  
1294 1361
    { INDEX_op_brcond_i32, { "rZ", "rZ" } },
1295 1362
    { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
1363
    { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
1296 1364

  
1297 1365
    { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
1298 1366
    { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },

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