Revision 43a34704 hw/m48t59.c

b/hw/m48t59.c
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 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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 */
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struct m48t59_t {
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struct M48t59State {
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    /* Model parameters */
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    uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
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    /* Hardware parameters */
......
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typedef struct M48t59ISAState {
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    ISADevice busdev;
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    m48t59_t state;
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    M48t59State state;
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} M48t59ISAState;
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typedef struct M48t59SysBusState {
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    SysBusDevice busdev;
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    m48t59_t state;
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    M48t59State state;
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} M48t59SysBusState;
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/* Fake timer functions */
......
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{
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    struct tm tm;
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    uint64_t next_time;
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    qemu_set_irq(NVRAM->IRQ, 1);
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    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
......
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    qemu_set_irq(NVRAM->IRQ, 0);
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}
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static void set_alarm (m48t59_t *NVRAM)
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static void set_alarm(M48t59State *NVRAM)
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{
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    int diff;
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    if (NVRAM->alrm_timer != NULL) {
......
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}
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/* RTC management helpers */
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static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
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static inline void get_time(M48t59State *NVRAM, struct tm *tm)
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{
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    qemu_get_timedate(tm, NVRAM->time_offset);
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}
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static void set_time (m48t59_t *NVRAM, struct tm *tm)
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static void set_time(M48t59State *NVRAM, struct tm *tm)
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{
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    NVRAM->time_offset = qemu_timedate_diff(tm);
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    set_alarm(NVRAM);
......
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/* Watchdog management */
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static void watchdog_cb (void *opaque)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    NVRAM->buffer[0x1FF0] |= 0x80;
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    if (NVRAM->buffer[0x1FF7] & 0x80) {
......
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    }
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}
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static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
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static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
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{
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    uint64_t interval; /* in 1/16 seconds */
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......
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    struct tm tm;
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    int tmp;
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......
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uint32_t m48t59_read (void *opaque, uint32_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    struct tm tm;
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    uint32_t retval = 0xFF;
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......
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void m48t59_set_addr (void *opaque, uint32_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    NVRAM->addr = addr;
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}
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void m48t59_toggle_lock (void *opaque, int lock)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    NVRAM->lock ^= 1 << lock;
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}
......
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/* IO access to NVRAM */
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static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    addr -= NVRAM->io_base;
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    NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
......
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static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    uint32_t retval;
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    addr -= NVRAM->io_base;
......
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static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    m48t59_write(NVRAM, addr, value & 0xff);
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}
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static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
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    m48t59_write(NVRAM, addr + 1, value & 0xff);
......
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static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
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    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
......
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static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    uint32_t retval;
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    retval = m48t59_read(NVRAM, addr);
......
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static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    uint32_t retval;
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    retval = m48t59_read(NVRAM, addr) << 8;
......
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static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
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{
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    m48t59_t *NVRAM = opaque;
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    M48t59State *NVRAM = opaque;
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    uint32_t retval;
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    retval = m48t59_read(NVRAM, addr) << 24;
......
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static void m48t59_save(QEMUFile *f, void *opaque)
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{
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    m48t59_t *s = opaque;
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    M48t59State *s = opaque;
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    qemu_put_8s(f, &s->lock);
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    qemu_put_be16s(f, &s->addr);
......
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static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
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{
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    m48t59_t *s = opaque;
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    M48t59State *s = opaque;
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    if (version_id != 1)
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        return -EINVAL;
......
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    return 0;
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}
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static void m48t59_reset_common(m48t59_t *NVRAM)
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static void m48t59_reset_common(M48t59State *NVRAM)
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{
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    NVRAM->addr = 0;
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    NVRAM->lock = 0;
......
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static void m48t59_reset_isa(DeviceState *d)
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{
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    M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
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    m48t59_t *NVRAM = &isa->state;
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    M48t59State *NVRAM = &isa->state;
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    m48t59_reset_common(NVRAM);
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}
......
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static void m48t59_reset_sysbus(DeviceState *d)
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{
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    M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
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    m48t59_t *NVRAM = &sys->state;
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    M48t59State *NVRAM = &sys->state;
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    m48t59_reset_common(NVRAM);
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}
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/* Initialisation routine */
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m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
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                       uint32_t io_base, uint16_t size,
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                       int type)
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M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
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                         uint32_t io_base, uint16_t size, int type)
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{
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    DeviceState *dev;
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    SysBusDevice *s;
......
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    return &d->state;
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}
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m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
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M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
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{
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    M48t59ISAState *d;
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    ISADevice *dev;
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    m48t59_t *s;
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    M48t59State *s;
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    dev = isa_create("m48t59_isa");
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    qdev_prop_set_uint32(&dev->qdev, "type", type);
......
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    return s;
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}
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static void m48t59_init_common(m48t59_t *s)
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static void m48t59_init_common(M48t59State *s)
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{
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    s->buffer = qemu_mallocz(s->size);
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    if (s->type == 59) {
......
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static int m48t59_init_isa1(ISADevice *dev)
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{
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    M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
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    m48t59_t *s = &d->state;
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    M48t59State *s = &d->state;
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    isa_init_irq(dev, &s->IRQ, 8);
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    m48t59_init_common(s);
......
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static int m48t59_init1(SysBusDevice *dev)
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{
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    M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
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    m48t59_t *s = &d->state;
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    M48t59State *s = &d->state;
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    int mem_index;
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    sysbus_init_irq(dev, &s->IRQ);

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