Statistics
| Branch: | Revision:

root / hw / m48t59.c @ 43a34704

History | View | Annotate | Download (19.5 kB)

1
/*
2
 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
3
 *
4
 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "nvram.h"
26
#include "qemu-timer.h"
27
#include "sysemu.h"
28
#include "sysbus.h"
29
#include "isa.h"
30

    
31
//#define DEBUG_NVRAM
32

    
33
#if defined(DEBUG_NVRAM)
34
#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
35
#else
36
#define NVRAM_PRINTF(fmt, ...) do { } while (0)
37
#endif
38

    
39
/*
40
 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
41
 * alarm and a watchdog timer and related control registers. In the
42
 * PPC platform there is also a nvram lock function.
43
 */
44

    
45
/*
46
 * Chipset docs:
47
 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
48
 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
49
 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
50
 */
51

    
52
struct M48t59State {
53
    /* Model parameters */
54
    uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
55
    /* Hardware parameters */
56
    qemu_irq IRQ;
57
    uint32_t io_base;
58
    uint32_t size;
59
    /* RTC management */
60
    time_t   time_offset;
61
    time_t   stop_time;
62
    /* Alarm & watchdog */
63
    struct tm alarm;
64
    struct QEMUTimer *alrm_timer;
65
    struct QEMUTimer *wd_timer;
66
    /* NVRAM storage */
67
    uint8_t  lock;
68
    uint16_t addr;
69
    uint8_t *buffer;
70
};
71

    
72
typedef struct M48t59ISAState {
73
    ISADevice busdev;
74
    M48t59State state;
75
} M48t59ISAState;
76

    
77
typedef struct M48t59SysBusState {
78
    SysBusDevice busdev;
79
    M48t59State state;
80
} M48t59SysBusState;
81

    
82
/* Fake timer functions */
83

    
84
/* Alarm management */
85
static void alarm_cb (void *opaque)
86
{
87
    struct tm tm;
88
    uint64_t next_time;
89
    M48t59State *NVRAM = opaque;
90

    
91
    qemu_set_irq(NVRAM->IRQ, 1);
92
    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
93
        (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
94
        (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
95
        (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
96
        /* Repeat once a month */
97
        qemu_get_timedate(&tm, NVRAM->time_offset);
98
        tm.tm_mon++;
99
        if (tm.tm_mon == 13) {
100
            tm.tm_mon = 1;
101
            tm.tm_year++;
102
        }
103
        next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
104
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
105
               (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
106
               (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
107
               (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
108
        /* Repeat once a day */
109
        next_time = 24 * 60 * 60;
110
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
111
               (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
112
               (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
113
               (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
114
        /* Repeat once an hour */
115
        next_time = 60 * 60;
116
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
117
               (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
118
               (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
119
               (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
120
        /* Repeat once a minute */
121
        next_time = 60;
122
    } else {
123
        /* Repeat once a second */
124
        next_time = 1;
125
    }
126
    qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
127
                    next_time * 1000);
128
    qemu_set_irq(NVRAM->IRQ, 0);
129
}
130

    
131
static void set_alarm(M48t59State *NVRAM)
132
{
133
    int diff;
134
    if (NVRAM->alrm_timer != NULL) {
135
        qemu_del_timer(NVRAM->alrm_timer);
136
        diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
137
        if (diff > 0)
138
            qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
139
    }
140
}
141

    
142
/* RTC management helpers */
143
static inline void get_time(M48t59State *NVRAM, struct tm *tm)
144
{
145
    qemu_get_timedate(tm, NVRAM->time_offset);
146
}
147

    
148
static void set_time(M48t59State *NVRAM, struct tm *tm)
149
{
150
    NVRAM->time_offset = qemu_timedate_diff(tm);
151
    set_alarm(NVRAM);
152
}
153

    
154
/* Watchdog management */
155
static void watchdog_cb (void *opaque)
156
{
157
    M48t59State *NVRAM = opaque;
158

    
159
    NVRAM->buffer[0x1FF0] |= 0x80;
160
    if (NVRAM->buffer[0x1FF7] & 0x80) {
161
        NVRAM->buffer[0x1FF7] = 0x00;
162
        NVRAM->buffer[0x1FFC] &= ~0x40;
163
        /* May it be a hw CPU Reset instead ? */
164
        qemu_system_reset_request();
165
    } else {
166
        qemu_set_irq(NVRAM->IRQ, 1);
167
        qemu_set_irq(NVRAM->IRQ, 0);
168
    }
169
}
170

    
171
static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
172
{
173
    uint64_t interval; /* in 1/16 seconds */
174

    
175
    NVRAM->buffer[0x1FF0] &= ~0x80;
176
    if (NVRAM->wd_timer != NULL) {
177
        qemu_del_timer(NVRAM->wd_timer);
178
        if (value != 0) {
179
            interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
180
            qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
181
                           ((interval * 1000) >> 4));
182
        }
183
    }
184
}
185

    
186
/* Direct access to NVRAM */
187
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
188
{
189
    M48t59State *NVRAM = opaque;
190
    struct tm tm;
191
    int tmp;
192

    
193
    if (addr > 0x1FF8 && addr < 0x2000)
194
        NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
195

    
196
    /* check for NVRAM access */
197
    if ((NVRAM->type == 2 && addr < 0x7f8) ||
198
        (NVRAM->type == 8 && addr < 0x1ff8) ||
199
        (NVRAM->type == 59 && addr < 0x1ff0))
200
        goto do_write;
201

    
202
    /* TOD access */
203
    switch (addr) {
204
    case 0x1FF0:
205
        /* flags register : read-only */
206
        break;
207
    case 0x1FF1:
208
        /* unused */
209
        break;
210
    case 0x1FF2:
211
        /* alarm seconds */
212
        tmp = from_bcd(val & 0x7F);
213
        if (tmp >= 0 && tmp <= 59) {
214
            NVRAM->alarm.tm_sec = tmp;
215
            NVRAM->buffer[0x1FF2] = val;
216
            set_alarm(NVRAM);
217
        }
218
        break;
219
    case 0x1FF3:
220
        /* alarm minutes */
221
        tmp = from_bcd(val & 0x7F);
222
        if (tmp >= 0 && tmp <= 59) {
223
            NVRAM->alarm.tm_min = tmp;
224
            NVRAM->buffer[0x1FF3] = val;
225
            set_alarm(NVRAM);
226
        }
227
        break;
228
    case 0x1FF4:
229
        /* alarm hours */
230
        tmp = from_bcd(val & 0x3F);
231
        if (tmp >= 0 && tmp <= 23) {
232
            NVRAM->alarm.tm_hour = tmp;
233
            NVRAM->buffer[0x1FF4] = val;
234
            set_alarm(NVRAM);
235
        }
236
        break;
237
    case 0x1FF5:
238
        /* alarm date */
239
        tmp = from_bcd(val & 0x1F);
240
        if (tmp != 0) {
241
            NVRAM->alarm.tm_mday = tmp;
242
            NVRAM->buffer[0x1FF5] = val;
243
            set_alarm(NVRAM);
244
        }
245
        break;
246
    case 0x1FF6:
247
        /* interrupts */
248
        NVRAM->buffer[0x1FF6] = val;
249
        break;
250
    case 0x1FF7:
251
        /* watchdog */
252
        NVRAM->buffer[0x1FF7] = val;
253
        set_up_watchdog(NVRAM, val);
254
        break;
255
    case 0x1FF8:
256
    case 0x07F8:
257
        /* control */
258
       NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
259
        break;
260
    case 0x1FF9:
261
    case 0x07F9:
262
        /* seconds (BCD) */
263
        tmp = from_bcd(val & 0x7F);
264
        if (tmp >= 0 && tmp <= 59) {
265
            get_time(NVRAM, &tm);
266
            tm.tm_sec = tmp;
267
            set_time(NVRAM, &tm);
268
        }
269
        if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
270
            if (val & 0x80) {
271
                NVRAM->stop_time = time(NULL);
272
            } else {
273
                NVRAM->time_offset += NVRAM->stop_time - time(NULL);
274
                NVRAM->stop_time = 0;
275
            }
276
        }
277
        NVRAM->buffer[addr] = val & 0x80;
278
        break;
279
    case 0x1FFA:
280
    case 0x07FA:
281
        /* minutes (BCD) */
282
        tmp = from_bcd(val & 0x7F);
283
        if (tmp >= 0 && tmp <= 59) {
284
            get_time(NVRAM, &tm);
285
            tm.tm_min = tmp;
286
            set_time(NVRAM, &tm);
287
        }
288
        break;
289
    case 0x1FFB:
290
    case 0x07FB:
291
        /* hours (BCD) */
292
        tmp = from_bcd(val & 0x3F);
293
        if (tmp >= 0 && tmp <= 23) {
294
            get_time(NVRAM, &tm);
295
            tm.tm_hour = tmp;
296
            set_time(NVRAM, &tm);
297
        }
298
        break;
299
    case 0x1FFC:
300
    case 0x07FC:
301
        /* day of the week / century */
302
        tmp = from_bcd(val & 0x07);
303
        get_time(NVRAM, &tm);
304
        tm.tm_wday = tmp;
305
        set_time(NVRAM, &tm);
306
        NVRAM->buffer[addr] = val & 0x40;
307
        break;
308
    case 0x1FFD:
309
    case 0x07FD:
310
        /* date */
311
        tmp = from_bcd(val & 0x1F);
312
        if (tmp != 0) {
313
            get_time(NVRAM, &tm);
314
            tm.tm_mday = tmp;
315
            set_time(NVRAM, &tm);
316
        }
317
        break;
318
    case 0x1FFE:
319
    case 0x07FE:
320
        /* month */
321
        tmp = from_bcd(val & 0x1F);
322
        if (tmp >= 1 && tmp <= 12) {
323
            get_time(NVRAM, &tm);
324
            tm.tm_mon = tmp - 1;
325
            set_time(NVRAM, &tm);
326
        }
327
        break;
328
    case 0x1FFF:
329
    case 0x07FF:
330
        /* year */
331
        tmp = from_bcd(val);
332
        if (tmp >= 0 && tmp <= 99) {
333
            get_time(NVRAM, &tm);
334
            if (NVRAM->type == 8)
335
                tm.tm_year = from_bcd(val) + 68; // Base year is 1968
336
            else
337
                tm.tm_year = from_bcd(val);
338
            set_time(NVRAM, &tm);
339
        }
340
        break;
341
    default:
342
        /* Check lock registers state */
343
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
344
            break;
345
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
346
            break;
347
    do_write:
348
        if (addr < NVRAM->size) {
349
            NVRAM->buffer[addr] = val & 0xFF;
350
        }
351
        break;
352
    }
353
}
354

    
355
uint32_t m48t59_read (void *opaque, uint32_t addr)
356
{
357
    M48t59State *NVRAM = opaque;
358
    struct tm tm;
359
    uint32_t retval = 0xFF;
360

    
361
    /* check for NVRAM access */
362
    if ((NVRAM->type == 2 && addr < 0x078f) ||
363
        (NVRAM->type == 8 && addr < 0x1ff8) ||
364
        (NVRAM->type == 59 && addr < 0x1ff0))
365
        goto do_read;
366

    
367
    /* TOD access */
368
    switch (addr) {
369
    case 0x1FF0:
370
        /* flags register */
371
        goto do_read;
372
    case 0x1FF1:
373
        /* unused */
374
        retval = 0;
375
        break;
376
    case 0x1FF2:
377
        /* alarm seconds */
378
        goto do_read;
379
    case 0x1FF3:
380
        /* alarm minutes */
381
        goto do_read;
382
    case 0x1FF4:
383
        /* alarm hours */
384
        goto do_read;
385
    case 0x1FF5:
386
        /* alarm date */
387
        goto do_read;
388
    case 0x1FF6:
389
        /* interrupts */
390
        goto do_read;
391
    case 0x1FF7:
392
        /* A read resets the watchdog */
393
        set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
394
        goto do_read;
395
    case 0x1FF8:
396
    case 0x07F8:
397
        /* control */
398
        goto do_read;
399
    case 0x1FF9:
400
    case 0x07F9:
401
        /* seconds (BCD) */
402
        get_time(NVRAM, &tm);
403
        retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
404
        break;
405
    case 0x1FFA:
406
    case 0x07FA:
407
        /* minutes (BCD) */
408
        get_time(NVRAM, &tm);
409
        retval = to_bcd(tm.tm_min);
410
        break;
411
    case 0x1FFB:
412
    case 0x07FB:
413
        /* hours (BCD) */
414
        get_time(NVRAM, &tm);
415
        retval = to_bcd(tm.tm_hour);
416
        break;
417
    case 0x1FFC:
418
    case 0x07FC:
419
        /* day of the week / century */
420
        get_time(NVRAM, &tm);
421
        retval = NVRAM->buffer[addr] | tm.tm_wday;
422
        break;
423
    case 0x1FFD:
424
    case 0x07FD:
425
        /* date */
426
        get_time(NVRAM, &tm);
427
        retval = to_bcd(tm.tm_mday);
428
        break;
429
    case 0x1FFE:
430
    case 0x07FE:
431
        /* month */
432
        get_time(NVRAM, &tm);
433
        retval = to_bcd(tm.tm_mon + 1);
434
        break;
435
    case 0x1FFF:
436
    case 0x07FF:
437
        /* year */
438
        get_time(NVRAM, &tm);
439
        if (NVRAM->type == 8)
440
            retval = to_bcd(tm.tm_year - 68); // Base year is 1968
441
        else
442
            retval = to_bcd(tm.tm_year);
443
        break;
444
    default:
445
        /* Check lock registers state */
446
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
447
            break;
448
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
449
            break;
450
    do_read:
451
        if (addr < NVRAM->size) {
452
            retval = NVRAM->buffer[addr];
453
        }
454
        break;
455
    }
456
    if (addr > 0x1FF9 && addr < 0x2000)
457
       NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
458

    
459
    return retval;
460
}
461

    
462
void m48t59_set_addr (void *opaque, uint32_t addr)
463
{
464
    M48t59State *NVRAM = opaque;
465

    
466
    NVRAM->addr = addr;
467
}
468

    
469
void m48t59_toggle_lock (void *opaque, int lock)
470
{
471
    M48t59State *NVRAM = opaque;
472

    
473
    NVRAM->lock ^= 1 << lock;
474
}
475

    
476
/* IO access to NVRAM */
477
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
478
{
479
    M48t59State *NVRAM = opaque;
480

    
481
    addr -= NVRAM->io_base;
482
    NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
483
    switch (addr) {
484
    case 0:
485
        NVRAM->addr &= ~0x00FF;
486
        NVRAM->addr |= val;
487
        break;
488
    case 1:
489
        NVRAM->addr &= ~0xFF00;
490
        NVRAM->addr |= val << 8;
491
        break;
492
    case 3:
493
        m48t59_write(NVRAM, val, NVRAM->addr);
494
        NVRAM->addr = 0x0000;
495
        break;
496
    default:
497
        break;
498
    }
499
}
500

    
501
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
502
{
503
    M48t59State *NVRAM = opaque;
504
    uint32_t retval;
505

    
506
    addr -= NVRAM->io_base;
507
    switch (addr) {
508
    case 3:
509
        retval = m48t59_read(NVRAM, NVRAM->addr);
510
        break;
511
    default:
512
        retval = -1;
513
        break;
514
    }
515
    NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
516

    
517
    return retval;
518
}
519

    
520
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
521
{
522
    M48t59State *NVRAM = opaque;
523

    
524
    m48t59_write(NVRAM, addr, value & 0xff);
525
}
526

    
527
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
528
{
529
    M48t59State *NVRAM = opaque;
530

    
531
    m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
532
    m48t59_write(NVRAM, addr + 1, value & 0xff);
533
}
534

    
535
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
536
{
537
    M48t59State *NVRAM = opaque;
538

    
539
    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
540
    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
541
    m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
542
    m48t59_write(NVRAM, addr + 3, value & 0xff);
543
}
544

    
545
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
546
{
547
    M48t59State *NVRAM = opaque;
548
    uint32_t retval;
549

    
550
    retval = m48t59_read(NVRAM, addr);
551
    return retval;
552
}
553

    
554
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
555
{
556
    M48t59State *NVRAM = opaque;
557
    uint32_t retval;
558

    
559
    retval = m48t59_read(NVRAM, addr) << 8;
560
    retval |= m48t59_read(NVRAM, addr + 1);
561
    return retval;
562
}
563

    
564
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
565
{
566
    M48t59State *NVRAM = opaque;
567
    uint32_t retval;
568

    
569
    retval = m48t59_read(NVRAM, addr) << 24;
570
    retval |= m48t59_read(NVRAM, addr + 1) << 16;
571
    retval |= m48t59_read(NVRAM, addr + 2) << 8;
572
    retval |= m48t59_read(NVRAM, addr + 3);
573
    return retval;
574
}
575

    
576
static CPUWriteMemoryFunc * const nvram_write[] = {
577
    &nvram_writeb,
578
    &nvram_writew,
579
    &nvram_writel,
580
};
581

    
582
static CPUReadMemoryFunc * const nvram_read[] = {
583
    &nvram_readb,
584
    &nvram_readw,
585
    &nvram_readl,
586
};
587

    
588
static void m48t59_save(QEMUFile *f, void *opaque)
589
{
590
    M48t59State *s = opaque;
591

    
592
    qemu_put_8s(f, &s->lock);
593
    qemu_put_be16s(f, &s->addr);
594
    qemu_put_buffer(f, s->buffer, s->size);
595
}
596

    
597
static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
598
{
599
    M48t59State *s = opaque;
600

    
601
    if (version_id != 1)
602
        return -EINVAL;
603

    
604
    qemu_get_8s(f, &s->lock);
605
    qemu_get_be16s(f, &s->addr);
606
    qemu_get_buffer(f, s->buffer, s->size);
607

    
608
    return 0;
609
}
610

    
611
static void m48t59_reset_common(M48t59State *NVRAM)
612
{
613
    NVRAM->addr = 0;
614
    NVRAM->lock = 0;
615
    if (NVRAM->alrm_timer != NULL)
616
        qemu_del_timer(NVRAM->alrm_timer);
617

    
618
    if (NVRAM->wd_timer != NULL)
619
        qemu_del_timer(NVRAM->wd_timer);
620
}
621

    
622
static void m48t59_reset_isa(DeviceState *d)
623
{
624
    M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
625
    M48t59State *NVRAM = &isa->state;
626

    
627
    m48t59_reset_common(NVRAM);
628
}
629

    
630
static void m48t59_reset_sysbus(DeviceState *d)
631
{
632
    M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
633
    M48t59State *NVRAM = &sys->state;
634

    
635
    m48t59_reset_common(NVRAM);
636
}
637

    
638
/* Initialisation routine */
639
M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
640
                         uint32_t io_base, uint16_t size, int type)
641
{
642
    DeviceState *dev;
643
    SysBusDevice *s;
644
    M48t59SysBusState *d;
645

    
646
    dev = qdev_create(NULL, "m48t59");
647
    qdev_prop_set_uint32(dev, "type", type);
648
    qdev_prop_set_uint32(dev, "size", size);
649
    qdev_prop_set_uint32(dev, "io_base", io_base);
650
    qdev_init_nofail(dev);
651
    s = sysbus_from_qdev(dev);
652
    sysbus_connect_irq(s, 0, IRQ);
653
    if (io_base != 0) {
654
        register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
655
        register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
656
    }
657
    if (mem_base != 0) {
658
        sysbus_mmio_map(s, 0, mem_base);
659
    }
660

    
661
    d = FROM_SYSBUS(M48t59SysBusState, s);
662

    
663
    return &d->state;
664
}
665

    
666
M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
667
{
668
    M48t59ISAState *d;
669
    ISADevice *dev;
670
    M48t59State *s;
671

    
672
    dev = isa_create("m48t59_isa");
673
    qdev_prop_set_uint32(&dev->qdev, "type", type);
674
    qdev_prop_set_uint32(&dev->qdev, "size", size);
675
    qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
676
    qdev_init_nofail(&dev->qdev);
677
    d = DO_UPCAST(M48t59ISAState, busdev, dev);
678
    s = &d->state;
679

    
680
    if (io_base != 0) {
681
        register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
682
        register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
683
    }
684

    
685
    return s;
686
}
687

    
688
static void m48t59_init_common(M48t59State *s)
689
{
690
    s->buffer = qemu_mallocz(s->size);
691
    if (s->type == 59) {
692
        s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
693
        s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
694
    }
695
    qemu_get_timedate(&s->alarm, 0);
696

    
697
    register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
698
}
699

    
700
static int m48t59_init_isa1(ISADevice *dev)
701
{
702
    M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
703
    M48t59State *s = &d->state;
704

    
705
    isa_init_irq(dev, &s->IRQ, 8);
706
    m48t59_init_common(s);
707

    
708
    return 0;
709
}
710

    
711
static int m48t59_init1(SysBusDevice *dev)
712
{
713
    M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
714
    M48t59State *s = &d->state;
715
    int mem_index;
716

    
717
    sysbus_init_irq(dev, &s->IRQ);
718

    
719
    mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
720
    sysbus_init_mmio(dev, s->size, mem_index);
721
    m48t59_init_common(s);
722

    
723
    return 0;
724
}
725

    
726
static ISADeviceInfo m48t59_isa_info = {
727
    .init = m48t59_init_isa1,
728
    .qdev.name = "m48t59_isa",
729
    .qdev.size = sizeof(M48t59ISAState),
730
    .qdev.reset = m48t59_reset_isa,
731
    .qdev.no_user = 1,
732
    .qdev.props = (Property[]) {
733
        DEFINE_PROP_UINT32("size",    M48t59ISAState, state.size,    -1),
734
        DEFINE_PROP_UINT32("type",    M48t59ISAState, state.type,    -1),
735
        DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base,  0),
736
        DEFINE_PROP_END_OF_LIST(),
737
    }
738
};
739

    
740
static SysBusDeviceInfo m48t59_info = {
741
    .init = m48t59_init1,
742
    .qdev.name  = "m48t59",
743
    .qdev.size = sizeof(M48t59SysBusState),
744
    .qdev.reset = m48t59_reset_sysbus,
745
    .qdev.props = (Property[]) {
746
        DEFINE_PROP_UINT32("size",    M48t59SysBusState, state.size,    -1),
747
        DEFINE_PROP_UINT32("type",    M48t59SysBusState, state.type,    -1),
748
        DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base,  0),
749
        DEFINE_PROP_END_OF_LIST(),
750
    }
751
};
752

    
753
static void m48t59_register_devices(void)
754
{
755
    sysbus_register_withprop(&m48t59_info);
756
    isa_qdev_register(&m48t59_isa_info);
757
}
758

    
759
device_init(m48t59_register_devices)