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/*
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 * QEMU Sun4u/Sun4v System Emulator
3
 *
4
 * Copyright (c) 2005 Fabrice Bellard
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "pci.h"
26
#include "apb_pci.h"
27
#include "pc.h"
28
#include "nvram.h"
29
#include "fdc.h"
30
#include "net.h"
31
#include "qemu-timer.h"
32
#include "sysemu.h"
33
#include "boards.h"
34
#include "firmware_abi.h"
35
#include "fw_cfg.h"
36
#include "sysbus.h"
37
#include "ide.h"
38
#include "loader.h"
39
#include "elf.h"
40

    
41
//#define DEBUG_IRQ
42
//#define DEBUG_EBUS
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//#define DEBUG_TIMER
44

    
45
#ifdef DEBUG_IRQ
46
#define CPUIRQ_DPRINTF(fmt, ...)                                \
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    do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
48
#else
49
#define CPUIRQ_DPRINTF(fmt, ...)
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#endif
51

    
52
#ifdef DEBUG_EBUS
53
#define EBUS_DPRINTF(fmt, ...)                                  \
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    do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
55
#else
56
#define EBUS_DPRINTF(fmt, ...)
57
#endif
58

    
59
#ifdef DEBUG_TIMER
60
#define TIMER_DPRINTF(fmt, ...)                                  \
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    do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
62
#else
63
#define TIMER_DPRINTF(fmt, ...)
64
#endif
65

    
66
#define KERNEL_LOAD_ADDR     0x00404000
67
#define CMDLINE_ADDR         0x003ff000
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#define INITRD_LOAD_ADDR     0x00300000
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#define PROM_SIZE_MAX        (4 * 1024 * 1024)
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#define PROM_VADDR           0x000ffd00000ULL
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#define APB_SPECIAL_BASE     0x1fe00000000ULL
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#define APB_MEM_BASE         0x1ff00000000ULL
73
#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
74
#define PROM_FILENAME        "openbios-sparc64"
75
#define NVRAM_SIZE           0x2000
76
#define MAX_IDE_BUS          2
77
#define BIOS_CFG_IOPORT      0x510
78
#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
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#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
80
#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
81

    
82
#define MAX_PILS 16
83

    
84
#define TICK_MAX             0x7fffffffffffffffULL
85

    
86
struct hwdef {
87
    const char * const default_cpu_model;
88
    uint16_t machine_id;
89
    uint64_t prom_addr;
90
    uint64_t console_serial_base;
91
};
92

    
93
int DMA_get_channel_mode (int nchan)
94
{
95
    return 0;
96
}
97
int DMA_read_memory (int nchan, void *buf, int pos, int size)
98
{
99
    return 0;
100
}
101
int DMA_write_memory (int nchan, void *buf, int pos, int size)
102
{
103
    return 0;
104
}
105
void DMA_hold_DREQ (int nchan) {}
106
void DMA_release_DREQ (int nchan) {}
107
void DMA_schedule(int nchan) {}
108
void DMA_init (int high_page_enable) {}
109
void DMA_register_channel (int nchan,
110
                           DMA_transfer_handler transfer_handler,
111
                           void *opaque)
112
{
113
}
114

    
115
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
116
{
117
    fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
118
    return 0;
119
}
120

    
121
static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
122
                                  const char *arch, ram_addr_t RAM_size,
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                                  const char *boot_devices,
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                                  uint32_t kernel_image, uint32_t kernel_size,
125
                                  const char *cmdline,
126
                                  uint32_t initrd_image, uint32_t initrd_size,
127
                                  uint32_t NVRAM_image,
128
                                  int width, int height, int depth,
129
                                  const uint8_t *macaddr)
130
{
131
    unsigned int i;
132
    uint32_t start, end;
133
    uint8_t image[0x1ff0];
134
    struct OpenBIOS_nvpart_v1 *part_header;
135

    
136
    memset(image, '\0', sizeof(image));
137

    
138
    start = 0;
139

    
140
    // OpenBIOS nvram variables
141
    // Variable partition
142
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
143
    part_header->signature = OPENBIOS_PART_SYSTEM;
144
    pstrcpy(part_header->name, sizeof(part_header->name), "system");
145

    
146
    end = start + sizeof(struct OpenBIOS_nvpart_v1);
147
    for (i = 0; i < nb_prom_envs; i++)
148
        end = OpenBIOS_set_var(image, end, prom_envs[i]);
149

    
150
    // End marker
151
    image[end++] = '\0';
152

    
153
    end = start + ((end - start + 15) & ~15);
154
    OpenBIOS_finish_partition(part_header, end - start);
155

    
156
    // free partition
157
    start = end;
158
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
159
    part_header->signature = OPENBIOS_PART_FREE;
160
    pstrcpy(part_header->name, sizeof(part_header->name), "free");
161

    
162
    end = 0x1fd0;
163
    OpenBIOS_finish_partition(part_header, end - start);
164

    
165
    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
166

    
167
    for (i = 0; i < sizeof(image); i++)
168
        m48t59_write(nvram, i, image[i]);
169

    
170
    return 0;
171
}
172
static unsigned long sun4u_load_kernel(const char *kernel_filename,
173
                                       const char *initrd_filename,
174
                                       ram_addr_t RAM_size, long *initrd_size)
175
{
176
    int linux_boot;
177
    unsigned int i;
178
    long kernel_size;
179
    uint8_t *ptr;
180

    
181
    linux_boot = (kernel_filename != NULL);
182

    
183
    kernel_size = 0;
184
    if (linux_boot) {
185
        int bswap_needed;
186

    
187
#ifdef BSWAP_NEEDED
188
        bswap_needed = 1;
189
#else
190
        bswap_needed = 0;
191
#endif
192
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL,
193
                               1, ELF_MACHINE, 0);
194
        if (kernel_size < 0)
195
            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
196
                                    RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
197
                                    TARGET_PAGE_SIZE);
198
        if (kernel_size < 0)
199
            kernel_size = load_image_targphys(kernel_filename,
200
                                              KERNEL_LOAD_ADDR,
201
                                              RAM_size - KERNEL_LOAD_ADDR);
202
        if (kernel_size < 0) {
203
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
204
                    kernel_filename);
205
            exit(1);
206
        }
207

    
208
        /* load initrd */
209
        *initrd_size = 0;
210
        if (initrd_filename) {
211
            *initrd_size = load_image_targphys(initrd_filename,
212
                                               INITRD_LOAD_ADDR,
213
                                               RAM_size - INITRD_LOAD_ADDR);
214
            if (*initrd_size < 0) {
215
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
216
                        initrd_filename);
217
                exit(1);
218
            }
219
        }
220
        if (*initrd_size > 0) {
221
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
222
                ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
223
                if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
224
                    stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
225
                    stl_p(ptr + 28, *initrd_size);
226
                    break;
227
                }
228
            }
229
        }
230
    }
231
    return kernel_size;
232
}
233

    
234
void pic_info(Monitor *mon)
235
{
236
}
237

    
238
void irq_info(Monitor *mon)
239
{
240
}
241

    
242
void cpu_check_irqs(CPUState *env)
243
{
244
    uint32_t pil = env->pil_in |
245
                  (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
246

    
247
    /* check if TM or SM in SOFTINT are set
248
       setting these also causes interrupt 14 */
249
    if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
250
        pil |= 1 << 14;
251
    }
252

    
253
    if (!pil) {
254
        if (env->interrupt_request & CPU_INTERRUPT_HARD) {
255
            CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
256
                           env->interrupt_index);
257
            env->interrupt_index = 0;
258
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
259
        }
260
        return;
261
    }
262

    
263
    if (cpu_interrupts_enabled(env)) {
264

    
265
        unsigned int i;
266

    
267
        for (i = 15; i > env->psrpil; i--) {
268
            if (pil & (1 << i)) {
269
                int old_interrupt = env->interrupt_index;
270
                int new_interrupt = TT_EXTINT | i;
271

    
272
                if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
273
                    CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
274
                                   "current %x >= pending %x\n",
275
                                   env->tl, cpu_tsptr(env)->tt, new_interrupt);
276
                } else if (old_interrupt != new_interrupt) {
277
                    env->interrupt_index = new_interrupt;
278
                    CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
279
                                   old_interrupt, new_interrupt);
280
                    cpu_interrupt(env, CPU_INTERRUPT_HARD);
281
                }
282
                break;
283
            }
284
        }
285
    } else {
286
        CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
287
                       "current interrupt %x\n",
288
                       pil, env->pil_in, env->softint, env->interrupt_index);
289
    }
290
}
291

    
292
static void cpu_kick_irq(CPUState *env)
293
{
294
    env->halted = 0;
295
    cpu_check_irqs(env);
296
}
297

    
298
static void cpu_set_irq(void *opaque, int irq, int level)
299
{
300
    CPUState *env = opaque;
301

    
302
    if (level) {
303
        CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
304
        env->halted = 0;
305
        env->pil_in |= 1 << irq;
306
        cpu_check_irqs(env);
307
    } else {
308
        CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
309
        env->pil_in &= ~(1 << irq);
310
        cpu_check_irqs(env);
311
    }
312
}
313

    
314
typedef struct ResetData {
315
    CPUState *env;
316
    uint64_t prom_addr;
317
} ResetData;
318

    
319
void cpu_put_timer(QEMUFile *f, CPUTimer *s)
320
{
321
    qemu_put_be32s(f, &s->frequency);
322
    qemu_put_be32s(f, &s->disabled);
323
    qemu_put_be64s(f, &s->disabled_mask);
324
    qemu_put_sbe64s(f, &s->clock_offset);
325

    
326
    qemu_put_timer(f, s->qtimer);
327
}
328

    
329
void cpu_get_timer(QEMUFile *f, CPUTimer *s)
330
{
331
    qemu_get_be32s(f, &s->frequency);
332
    qemu_get_be32s(f, &s->disabled);
333
    qemu_get_be64s(f, &s->disabled_mask);
334
    qemu_get_sbe64s(f, &s->clock_offset);
335

    
336
    qemu_get_timer(f, s->qtimer);
337
}
338

    
339
static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
340
                                  QEMUBHFunc *cb, uint32_t frequency,
341
                                  uint64_t disabled_mask)
342
{
343
    CPUTimer *timer = qemu_mallocz(sizeof (CPUTimer));
344

    
345
    timer->name = name;
346
    timer->frequency = frequency;
347
    timer->disabled_mask = disabled_mask;
348

    
349
    timer->disabled = 1;
350
    timer->clock_offset = qemu_get_clock(vm_clock);
351

    
352
    timer->qtimer = qemu_new_timer(vm_clock, cb, env);
353

    
354
    return timer;
355
}
356

    
357
static void cpu_timer_reset(CPUTimer *timer)
358
{
359
    timer->disabled = 1;
360
    timer->clock_offset = qemu_get_clock(vm_clock);
361

    
362
    qemu_del_timer(timer->qtimer);
363
}
364

    
365
static void main_cpu_reset(void *opaque)
366
{
367
    ResetData *s = (ResetData *)opaque;
368
    CPUState *env = s->env;
369
    static unsigned int nr_resets;
370

    
371
    cpu_reset(env);
372

    
373
    cpu_timer_reset(env->tick);
374
    cpu_timer_reset(env->stick);
375
    cpu_timer_reset(env->hstick);
376

    
377
    env->gregs[1] = 0; // Memory start
378
    env->gregs[2] = ram_size; // Memory size
379
    env->gregs[3] = 0; // Machine description XXX
380
    if (nr_resets++ == 0) {
381
        /* Power on reset */
382
        env->pc = s->prom_addr + 0x20ULL;
383
    } else {
384
        env->pc = s->prom_addr + 0x40ULL;
385
    }
386
    env->npc = env->pc + 4;
387
}
388

    
389
static void tick_irq(void *opaque)
390
{
391
    CPUState *env = opaque;
392

    
393
    CPUTimer* timer = env->tick;
394

    
395
    if (timer->disabled) {
396
        CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
397
        return;
398
    } else {
399
        CPUIRQ_DPRINTF("tick: fire\n");
400
    }
401

    
402
    env->softint |= SOFTINT_TIMER;
403
    cpu_kick_irq(env);
404
}
405

    
406
static void stick_irq(void *opaque)
407
{
408
    CPUState *env = opaque;
409

    
410
    CPUTimer* timer = env->stick;
411

    
412
    if (timer->disabled) {
413
        CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
414
        return;
415
    } else {
416
        CPUIRQ_DPRINTF("stick: fire\n");
417
    }
418

    
419
    env->softint |= SOFTINT_STIMER;
420
    cpu_kick_irq(env);
421
}
422

    
423
static void hstick_irq(void *opaque)
424
{
425
    CPUState *env = opaque;
426

    
427
    CPUTimer* timer = env->hstick;
428

    
429
    if (timer->disabled) {
430
        CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
431
        return;
432
    } else {
433
        CPUIRQ_DPRINTF("hstick: fire\n");
434
    }
435

    
436
    env->softint |= SOFTINT_STIMER;
437
    cpu_kick_irq(env);
438
}
439

    
440
static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
441
{
442
    return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
443
}
444

    
445
static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
446
{
447
    return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
448
}
449

    
450
void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
451
{
452
    uint64_t real_count = count & ~timer->disabled_mask;
453
    uint64_t disabled_bit = count & timer->disabled_mask;
454

    
455
    int64_t vm_clock_offset = qemu_get_clock(vm_clock) -
456
                    cpu_to_timer_ticks(real_count, timer->frequency);
457

    
458
    TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
459
                  timer->name, real_count,
460
                  timer->disabled?"disabled":"enabled", timer);
461

    
462
    timer->disabled = disabled_bit ? 1 : 0;
463
    timer->clock_offset = vm_clock_offset;
464
}
465

    
466
uint64_t cpu_tick_get_count(CPUTimer *timer)
467
{
468
    uint64_t real_count = timer_to_cpu_ticks(
469
                    qemu_get_clock(vm_clock) - timer->clock_offset,
470
                    timer->frequency);
471

    
472
    TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
473
           timer->name, real_count,
474
           timer->disabled?"disabled":"enabled", timer);
475

    
476
    if (timer->disabled)
477
        real_count |= timer->disabled_mask;
478

    
479
    return real_count;
480
}
481

    
482
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
483
{
484
    int64_t now = qemu_get_clock(vm_clock);
485

    
486
    uint64_t real_limit = limit & ~timer->disabled_mask;
487
    timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
488

    
489
    int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
490
                    timer->clock_offset;
491

    
492
    if (expires < now) {
493
        expires = now + 1;
494
    }
495

    
496
    TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
497
                  "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
498
                  timer->name, real_limit,
499
                  timer->disabled?"disabled":"enabled",
500
                  timer, limit,
501
                  timer_to_cpu_ticks(now - timer->clock_offset,
502
                                     timer->frequency),
503
                  timer_to_cpu_ticks(expires - now, timer->frequency));
504

    
505
    if (!real_limit) {
506
        TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
507
                timer->name);
508
        qemu_del_timer(timer->qtimer);
509
    } else if (timer->disabled) {
510
        qemu_del_timer(timer->qtimer);
511
    } else {
512
        qemu_mod_timer(timer->qtimer, expires);
513
    }
514
}
515

    
516
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
517
                              pcibus_t addr, pcibus_t size, int type)
518
{
519
    EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
520
                 region_num, addr);
521
    switch (region_num) {
522
    case 0:
523
        isa_mmio_init(addr, 0x1000000);
524
        break;
525
    case 1:
526
        isa_mmio_init(addr, 0x800000);
527
        break;
528
    }
529
}
530

    
531
static void dummy_isa_irq_handler(void *opaque, int n, int level)
532
{
533
}
534

    
535
/* EBUS (Eight bit bus) bridge */
536
static void
537
pci_ebus_init(PCIBus *bus, int devfn)
538
{
539
    qemu_irq *isa_irq;
540

    
541
    pci_create_simple(bus, devfn, "ebus");
542
    isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
543
    isa_bus_irqs(isa_irq);
544
}
545

    
546
static int
547
pci_ebus_init1(PCIDevice *s)
548
{
549
    isa_bus_new(&s->qdev);
550

    
551
    pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
552
    pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
553
    s->config[0x04] = 0x06; // command = bus master, pci mem
554
    s->config[0x05] = 0x00;
555
    s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
556
    s->config[0x07] = 0x03; // status = medium devsel
557
    s->config[0x08] = 0x01; // revision
558
    s->config[0x09] = 0x00; // programming i/f
559
    pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
560
    s->config[0x0D] = 0x0a; // latency_timer
561
    s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
562

    
563
    pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,
564
                           ebus_mmio_mapfunc);
565
    pci_register_bar(s, 1, 0x800000,  PCI_BASE_ADDRESS_SPACE_MEMORY,
566
                           ebus_mmio_mapfunc);
567
    return 0;
568
}
569

    
570
static PCIDeviceInfo ebus_info = {
571
    .qdev.name = "ebus",
572
    .qdev.size = sizeof(PCIDevice),
573
    .init = pci_ebus_init1,
574
};
575

    
576
static void pci_ebus_register(void)
577
{
578
    pci_qdev_register(&ebus_info);
579
}
580

    
581
device_init(pci_ebus_register);
582

    
583
/* Boot PROM (OpenBIOS) */
584
static void prom_init(target_phys_addr_t addr, const char *bios_name)
585
{
586
    DeviceState *dev;
587
    SysBusDevice *s;
588
    char *filename;
589
    int ret;
590

    
591
    dev = qdev_create(NULL, "openprom");
592
    qdev_init_nofail(dev);
593
    s = sysbus_from_qdev(dev);
594

    
595
    sysbus_mmio_map(s, 0, addr);
596

    
597
    /* load boot prom */
598
    if (bios_name == NULL) {
599
        bios_name = PROM_FILENAME;
600
    }
601
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
602
    if (filename) {
603
        ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
604
                       1, ELF_MACHINE, 0);
605
        if (ret < 0 || ret > PROM_SIZE_MAX) {
606
            ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
607
        }
608
        qemu_free(filename);
609
    } else {
610
        ret = -1;
611
    }
612
    if (ret < 0 || ret > PROM_SIZE_MAX) {
613
        fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
614
        exit(1);
615
    }
616
}
617

    
618
static int prom_init1(SysBusDevice *dev)
619
{
620
    ram_addr_t prom_offset;
621

    
622
    prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
623
    sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
624
    return 0;
625
}
626

    
627
static SysBusDeviceInfo prom_info = {
628
    .init = prom_init1,
629
    .qdev.name  = "openprom",
630
    .qdev.size  = sizeof(SysBusDevice),
631
    .qdev.props = (Property[]) {
632
        {/* end of property list */}
633
    }
634
};
635

    
636
static void prom_register_devices(void)
637
{
638
    sysbus_register_withprop(&prom_info);
639
}
640

    
641
device_init(prom_register_devices);
642

    
643

    
644
typedef struct RamDevice
645
{
646
    SysBusDevice busdev;
647
    uint64_t size;
648
} RamDevice;
649

    
650
/* System RAM */
651
static int ram_init1(SysBusDevice *dev)
652
{
653
    ram_addr_t RAM_size, ram_offset;
654
    RamDevice *d = FROM_SYSBUS(RamDevice, dev);
655

    
656
    RAM_size = d->size;
657

    
658
    ram_offset = qemu_ram_alloc(RAM_size);
659
    sysbus_init_mmio(dev, RAM_size, ram_offset);
660
    return 0;
661
}
662

    
663
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
664
{
665
    DeviceState *dev;
666
    SysBusDevice *s;
667
    RamDevice *d;
668

    
669
    /* allocate RAM */
670
    dev = qdev_create(NULL, "memory");
671
    s = sysbus_from_qdev(dev);
672

    
673
    d = FROM_SYSBUS(RamDevice, s);
674
    d->size = RAM_size;
675
    qdev_init_nofail(dev);
676

    
677
    sysbus_mmio_map(s, 0, addr);
678
}
679

    
680
static SysBusDeviceInfo ram_info = {
681
    .init = ram_init1,
682
    .qdev.name  = "memory",
683
    .qdev.size  = sizeof(RamDevice),
684
    .qdev.props = (Property[]) {
685
        DEFINE_PROP_UINT64("size", RamDevice, size, 0),
686
        DEFINE_PROP_END_OF_LIST(),
687
    }
688
};
689

    
690
static void ram_register_devices(void)
691
{
692
    sysbus_register_withprop(&ram_info);
693
}
694

    
695
device_init(ram_register_devices);
696

    
697
static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
698
{
699
    CPUState *env;
700
    ResetData *reset_info;
701

    
702
    uint32_t   tick_frequency = 100*1000000;
703
    uint32_t  stick_frequency = 100*1000000;
704
    uint32_t hstick_frequency = 100*1000000;
705

    
706
    if (!cpu_model)
707
        cpu_model = hwdef->default_cpu_model;
708
    env = cpu_init(cpu_model);
709
    if (!env) {
710
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
711
        exit(1);
712
    }
713

    
714
    env->tick = cpu_timer_create("tick", env, tick_irq,
715
                                  tick_frequency, TICK_NPT_MASK);
716

    
717
    env->stick = cpu_timer_create("stick", env, stick_irq,
718
                                   stick_frequency, TICK_INT_DIS);
719

    
720
    env->hstick = cpu_timer_create("hstick", env, hstick_irq,
721
                                    hstick_frequency, TICK_INT_DIS);
722

    
723
    reset_info = qemu_mallocz(sizeof(ResetData));
724
    reset_info->env = env;
725
    reset_info->prom_addr = hwdef->prom_addr;
726
    qemu_register_reset(main_cpu_reset, reset_info);
727

    
728
    return env;
729
}
730

    
731
static void sun4uv_init(ram_addr_t RAM_size,
732
                        const char *boot_devices,
733
                        const char *kernel_filename, const char *kernel_cmdline,
734
                        const char *initrd_filename, const char *cpu_model,
735
                        const struct hwdef *hwdef)
736
{
737
    CPUState *env;
738
    M48t59State *nvram;
739
    unsigned int i;
740
    long initrd_size, kernel_size;
741
    PCIBus *pci_bus, *pci_bus2, *pci_bus3;
742
    qemu_irq *irq;
743
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
744
    DriveInfo *fd[MAX_FD];
745
    void *fw_cfg;
746

    
747
    /* init CPUs */
748
    env = cpu_devinit(cpu_model, hwdef);
749

    
750
    /* set up devices */
751
    ram_init(0, RAM_size);
752

    
753
    prom_init(hwdef->prom_addr, bios_name);
754

    
755

    
756
    irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
757
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
758
                           &pci_bus3);
759
    isa_mem_base = VGA_BASE;
760
    pci_vga_init(pci_bus, 0, 0);
761

    
762
    // XXX Should be pci_bus3
763
    pci_ebus_init(pci_bus, -1);
764

    
765
    i = 0;
766
    if (hwdef->console_serial_base) {
767
        serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
768
                       serial_hds[i], 1);
769
        i++;
770
    }
771
    for(; i < MAX_SERIAL_PORTS; i++) {
772
        if (serial_hds[i]) {
773
            serial_isa_init(i, serial_hds[i]);
774
        }
775
    }
776

    
777
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
778
        if (parallel_hds[i]) {
779
            parallel_init(i, parallel_hds[i]);
780
        }
781
    }
782

    
783
    for(i = 0; i < nb_nics; i++)
784
        pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
785

    
786
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
787
        fprintf(stderr, "qemu: too many IDE bus\n");
788
        exit(1);
789
    }
790
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
791
        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
792
                          i % MAX_IDE_DEVS);
793
    }
794

    
795
    pci_cmd646_ide_init(pci_bus, hd, 1);
796

    
797
    isa_create_simple("i8042");
798
    for(i = 0; i < MAX_FD; i++) {
799
        fd[i] = drive_get(IF_FLOPPY, 0, i);
800
    }
801
    fdctrl_init_isa(fd);
802
    nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
803

    
804
    initrd_size = 0;
805
    kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
806
                                    ram_size, &initrd_size);
807

    
808
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
809
                           KERNEL_LOAD_ADDR, kernel_size,
810
                           kernel_cmdline,
811
                           INITRD_LOAD_ADDR, initrd_size,
812
                           /* XXX: need an option to load a NVRAM image */
813
                           0,
814
                           graphic_width, graphic_height, graphic_depth,
815
                           (uint8_t *)&nd_table[0].macaddr);
816

    
817
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
818
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
819
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
820
    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
821
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
822
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
823
    if (kernel_cmdline) {
824
        fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
825
                       strlen(kernel_cmdline) + 1);
826
        fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
827
                         (uint8_t*)strdup(kernel_cmdline),
828
                         strlen(kernel_cmdline) + 1);
829
    } else {
830
        fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
831
    }
832
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
833
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
834
    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
835

    
836
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
837
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
838
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
839

    
840
    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
841
}
842

    
843
enum {
844
    sun4u_id = 0,
845
    sun4v_id = 64,
846
    niagara_id,
847
};
848

    
849
static const struct hwdef hwdefs[] = {
850
    /* Sun4u generic PC-like machine */
851
    {
852
        .default_cpu_model = "TI UltraSparc II",
853
        .machine_id = sun4u_id,
854
        .prom_addr = 0x1fff0000000ULL,
855
        .console_serial_base = 0,
856
    },
857
    /* Sun4v generic PC-like machine */
858
    {
859
        .default_cpu_model = "Sun UltraSparc T1",
860
        .machine_id = sun4v_id,
861
        .prom_addr = 0x1fff0000000ULL,
862
        .console_serial_base = 0,
863
    },
864
    /* Sun4v generic Niagara machine */
865
    {
866
        .default_cpu_model = "Sun UltraSparc T1",
867
        .machine_id = niagara_id,
868
        .prom_addr = 0xfff0000000ULL,
869
        .console_serial_base = 0xfff0c2c000ULL,
870
    },
871
};
872

    
873
/* Sun4u hardware initialisation */
874
static void sun4u_init(ram_addr_t RAM_size,
875
                       const char *boot_devices,
876
                       const char *kernel_filename, const char *kernel_cmdline,
877
                       const char *initrd_filename, const char *cpu_model)
878
{
879
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
880
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
881
}
882

    
883
/* Sun4v hardware initialisation */
884
static void sun4v_init(ram_addr_t RAM_size,
885
                       const char *boot_devices,
886
                       const char *kernel_filename, const char *kernel_cmdline,
887
                       const char *initrd_filename, const char *cpu_model)
888
{
889
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
890
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
891
}
892

    
893
/* Niagara hardware initialisation */
894
static void niagara_init(ram_addr_t RAM_size,
895
                         const char *boot_devices,
896
                         const char *kernel_filename, const char *kernel_cmdline,
897
                         const char *initrd_filename, const char *cpu_model)
898
{
899
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
900
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
901
}
902

    
903
static QEMUMachine sun4u_machine = {
904
    .name = "sun4u",
905
    .desc = "Sun4u platform",
906
    .init = sun4u_init,
907
    .max_cpus = 1, // XXX for now
908
    .is_default = 1,
909
};
910

    
911
static QEMUMachine sun4v_machine = {
912
    .name = "sun4v",
913
    .desc = "Sun4v platform",
914
    .init = sun4v_init,
915
    .max_cpus = 1, // XXX for now
916
};
917

    
918
static QEMUMachine niagara_machine = {
919
    .name = "Niagara",
920
    .desc = "Sun4v platform, Niagara",
921
    .init = niagara_init,
922
    .max_cpus = 1, // XXX for now
923
};
924

    
925
static void sun4u_machine_init(void)
926
{
927
    qemu_register_machine(&sun4u_machine);
928
    qemu_register_machine(&sun4v_machine);
929
    qemu_register_machine(&niagara_machine);
930
}
931

    
932
machine_init(sun4u_machine_init);