Statistics
| Branch: | Revision:

root / hw / mcf_intc.c @ 43ad7e3e

History | View | Annotate | Download (3.6 kB)

1 5fafdf24 ths
/*
2 20dcee94 pbrook
 * ColdFire Interrupt Controller emulation.
3 20dcee94 pbrook
 *
4 20dcee94 pbrook
 * Copyright (c) 2007 CodeSourcery.
5 20dcee94 pbrook
 *
6 20dcee94 pbrook
 * This code is licenced under the GPL
7 20dcee94 pbrook
 */
8 87ecb68b pbrook
#include "hw.h"
9 87ecb68b pbrook
#include "mcf.h"
10 20dcee94 pbrook
11 20dcee94 pbrook
typedef struct {
12 20dcee94 pbrook
    uint64_t ipr;
13 20dcee94 pbrook
    uint64_t imr;
14 20dcee94 pbrook
    uint64_t ifr;
15 20dcee94 pbrook
    uint64_t enabled;
16 20dcee94 pbrook
    uint8_t icr[64];
17 20dcee94 pbrook
    CPUState *env;
18 20dcee94 pbrook
    int active_vector;
19 20dcee94 pbrook
} mcf_intc_state;
20 20dcee94 pbrook
21 20dcee94 pbrook
static void mcf_intc_update(mcf_intc_state *s)
22 20dcee94 pbrook
{
23 20dcee94 pbrook
    uint64_t active;
24 20dcee94 pbrook
    int i;
25 20dcee94 pbrook
    int best;
26 20dcee94 pbrook
    int best_level;
27 20dcee94 pbrook
28 20dcee94 pbrook
    active = (s->ipr | s->ifr) & s->enabled & ~s->imr;
29 20dcee94 pbrook
    best_level = 0;
30 20dcee94 pbrook
    best = 64;
31 20dcee94 pbrook
    if (active) {
32 20dcee94 pbrook
        for (i = 0; i < 64; i++) {
33 20dcee94 pbrook
            if ((active & 1) != 0 && s->icr[i] >= best_level) {
34 20dcee94 pbrook
                best_level = s->icr[i];
35 20dcee94 pbrook
                best = i;
36 20dcee94 pbrook
            }
37 20dcee94 pbrook
            active >>= 1;
38 20dcee94 pbrook
        }
39 20dcee94 pbrook
    }
40 20dcee94 pbrook
    s->active_vector = ((best == 64) ? 24 : (best + 64));
41 20dcee94 pbrook
    m68k_set_irq_level(s->env, best_level, s->active_vector);
42 20dcee94 pbrook
}
43 20dcee94 pbrook
44 c227f099 Anthony Liguori
static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
45 20dcee94 pbrook
{
46 20dcee94 pbrook
    int offset;
47 20dcee94 pbrook
    mcf_intc_state *s = (mcf_intc_state *)opaque;
48 20dcee94 pbrook
    offset = addr & 0xff;
49 20dcee94 pbrook
    if (offset >= 0x40 && offset < 0x80) {
50 20dcee94 pbrook
        return s->icr[offset - 0x40];
51 20dcee94 pbrook
    }
52 20dcee94 pbrook
    switch (offset) {
53 20dcee94 pbrook
    case 0x00:
54 20dcee94 pbrook
        return (uint32_t)(s->ipr >> 32);
55 20dcee94 pbrook
    case 0x04:
56 20dcee94 pbrook
        return (uint32_t)s->ipr;
57 20dcee94 pbrook
    case 0x08:
58 20dcee94 pbrook
        return (uint32_t)(s->imr >> 32);
59 20dcee94 pbrook
    case 0x0c:
60 20dcee94 pbrook
        return (uint32_t)s->imr;
61 20dcee94 pbrook
    case 0x10:
62 20dcee94 pbrook
        return (uint32_t)(s->ifr >> 32);
63 20dcee94 pbrook
    case 0x14:
64 20dcee94 pbrook
        return (uint32_t)s->ifr;
65 20dcee94 pbrook
    case 0xe0: /* SWIACK.  */
66 20dcee94 pbrook
        return s->active_vector;
67 20dcee94 pbrook
    case 0xe1: case 0xe2: case 0xe3: case 0xe4:
68 20dcee94 pbrook
    case 0xe5: case 0xe6: case 0xe7:
69 20dcee94 pbrook
        /* LnIACK */
70 2ac71179 Paul Brook
        hw_error("mcf_intc_read: LnIACK not implemented\n");
71 20dcee94 pbrook
    default:
72 20dcee94 pbrook
        return 0;
73 20dcee94 pbrook
    }
74 20dcee94 pbrook
}
75 20dcee94 pbrook
76 c227f099 Anthony Liguori
static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
77 20dcee94 pbrook
{
78 20dcee94 pbrook
    int offset;
79 20dcee94 pbrook
    mcf_intc_state *s = (mcf_intc_state *)opaque;
80 20dcee94 pbrook
    offset = addr & 0xff;
81 20dcee94 pbrook
    if (offset >= 0x40 && offset < 0x80) {
82 20dcee94 pbrook
        int n = offset - 0x40;
83 20dcee94 pbrook
        s->icr[n] = val;
84 20dcee94 pbrook
        if (val == 0)
85 20dcee94 pbrook
            s->enabled &= ~(1ull << n);
86 20dcee94 pbrook
        else
87 20dcee94 pbrook
            s->enabled |= (1ull << n);
88 20dcee94 pbrook
        mcf_intc_update(s);
89 20dcee94 pbrook
        return;
90 20dcee94 pbrook
    }
91 20dcee94 pbrook
    switch (offset) {
92 20dcee94 pbrook
    case 0x00: case 0x04:
93 20dcee94 pbrook
        /* Ignore IPR writes.  */
94 20dcee94 pbrook
        return;
95 20dcee94 pbrook
    case 0x08:
96 20dcee94 pbrook
        s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);
97 20dcee94 pbrook
        break;
98 20dcee94 pbrook
    case 0x0c:
99 20dcee94 pbrook
        s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
100 20dcee94 pbrook
        break;
101 20dcee94 pbrook
    default:
102 2ac71179 Paul Brook
        hw_error("mcf_intc_write: Bad write offset %d\n", offset);
103 20dcee94 pbrook
        break;
104 20dcee94 pbrook
    }
105 20dcee94 pbrook
    mcf_intc_update(s);
106 20dcee94 pbrook
}
107 20dcee94 pbrook
108 20dcee94 pbrook
static void mcf_intc_set_irq(void *opaque, int irq, int level)
109 20dcee94 pbrook
{
110 20dcee94 pbrook
    mcf_intc_state *s = (mcf_intc_state *)opaque;
111 20dcee94 pbrook
    if (irq >= 64)
112 20dcee94 pbrook
        return;
113 20dcee94 pbrook
    if (level)
114 20dcee94 pbrook
        s->ipr |= 1ull << irq;
115 20dcee94 pbrook
    else
116 20dcee94 pbrook
        s->ipr &= ~(1ull << irq);
117 20dcee94 pbrook
    mcf_intc_update(s);
118 20dcee94 pbrook
}
119 20dcee94 pbrook
120 20dcee94 pbrook
static void mcf_intc_reset(mcf_intc_state *s)
121 20dcee94 pbrook
{
122 20dcee94 pbrook
    s->imr = ~0ull;
123 20dcee94 pbrook
    s->ipr = 0;
124 20dcee94 pbrook
    s->ifr = 0;
125 20dcee94 pbrook
    s->enabled = 0;
126 20dcee94 pbrook
    memset(s->icr, 0, 64);
127 20dcee94 pbrook
    s->active_vector = 24;
128 20dcee94 pbrook
}
129 20dcee94 pbrook
130 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const mcf_intc_readfn[] = {
131 20dcee94 pbrook
   mcf_intc_read,
132 20dcee94 pbrook
   mcf_intc_read,
133 20dcee94 pbrook
   mcf_intc_read
134 20dcee94 pbrook
};
135 20dcee94 pbrook
136 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const mcf_intc_writefn[] = {
137 20dcee94 pbrook
   mcf_intc_write,
138 20dcee94 pbrook
   mcf_intc_write,
139 20dcee94 pbrook
   mcf_intc_write
140 20dcee94 pbrook
};
141 20dcee94 pbrook
142 c227f099 Anthony Liguori
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
143 20dcee94 pbrook
{
144 20dcee94 pbrook
    mcf_intc_state *s;
145 20dcee94 pbrook
    int iomemtype;
146 20dcee94 pbrook
147 20dcee94 pbrook
    s = qemu_mallocz(sizeof(mcf_intc_state));
148 20dcee94 pbrook
    s->env = env;
149 20dcee94 pbrook
    mcf_intc_reset(s);
150 20dcee94 pbrook
151 1eed09cb Avi Kivity
    iomemtype = cpu_register_io_memory(mcf_intc_readfn,
152 20dcee94 pbrook
                                       mcf_intc_writefn, s);
153 20dcee94 pbrook
    cpu_register_physical_memory(base, 0x100, iomemtype);
154 20dcee94 pbrook
155 20dcee94 pbrook
    return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
156 20dcee94 pbrook
}