Statistics
| Branch: | Revision:

root / hw / mst_fpga.c @ 43ad7e3e

History | View | Annotate | Download (5.1 kB)

1 7233b355 ths
/*
2 7233b355 ths
 * PXA270-based Intel Mainstone platforms.
3 7233b355 ths
 * FPGA driver
4 7233b355 ths
 *
5 7233b355 ths
 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
6 7233b355 ths
 *                                    <akuster@mvista.com>
7 7233b355 ths
 *
8 7233b355 ths
 * This code is licensed under the GNU GPL v2.
9 7233b355 ths
 */
10 7233b355 ths
#include "hw.h"
11 7233b355 ths
#include "pxa.h"
12 7233b355 ths
#include "mainstone.h"
13 7233b355 ths
14 7233b355 ths
/* Mainstone FPGA for extern irqs */
15 7233b355 ths
#define FPGA_GPIO_PIN        0
16 7233b355 ths
#define MST_NUM_IRQS        16
17 7233b355 ths
#define MST_LEDDAT1                0x10
18 7233b355 ths
#define MST_LEDDAT2                0x14
19 7233b355 ths
#define MST_LEDCTRL                0x40
20 7233b355 ths
#define MST_GPSWR                0x60
21 7233b355 ths
#define MST_MSCWR1                0x80
22 7233b355 ths
#define MST_MSCWR2                0x84
23 7233b355 ths
#define MST_MSCWR3                0x88
24 7233b355 ths
#define MST_MSCRD                0x90
25 7233b355 ths
#define MST_INTMSKENA        0xc0
26 7233b355 ths
#define MST_INTSETCLR        0xd0
27 7233b355 ths
#define MST_PCMCIA0                0xe0
28 7233b355 ths
#define MST_PCMCIA1                0xe4
29 7233b355 ths
30 7233b355 ths
typedef struct mst_irq_state{
31 7233b355 ths
        qemu_irq *parent;
32 7233b355 ths
        qemu_irq *pins;
33 7233b355 ths
34 7233b355 ths
        uint32_t prev_level;
35 7233b355 ths
        uint32_t leddat1;
36 7233b355 ths
        uint32_t leddat2;
37 7233b355 ths
        uint32_t ledctrl;
38 7233b355 ths
        uint32_t gpswr;
39 7233b355 ths
        uint32_t mscwr1;
40 7233b355 ths
        uint32_t mscwr2;
41 7233b355 ths
        uint32_t mscwr3;
42 7233b355 ths
        uint32_t mscrd;
43 7233b355 ths
        uint32_t intmskena;
44 7233b355 ths
        uint32_t intsetclr;
45 7233b355 ths
        uint32_t pcmcia0;
46 7233b355 ths
        uint32_t pcmcia1;
47 7233b355 ths
}mst_irq_state;
48 7233b355 ths
49 7233b355 ths
static void
50 7233b355 ths
mst_fpga_update_gpio(mst_irq_state *s)
51 7233b355 ths
{
52 7233b355 ths
        uint32_t level, diff;
53 7233b355 ths
        int bit;
54 7233b355 ths
        level = s->prev_level ^ s->intsetclr;
55 7233b355 ths
56 7233b355 ths
        for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
57 7233b355 ths
                bit = ffs(diff) - 1;
58 7233b355 ths
                qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
59 7233b355 ths
        }
60 7233b355 ths
        s->prev_level = level;
61 7233b355 ths
}
62 7233b355 ths
63 7233b355 ths
static void
64 7233b355 ths
mst_fpga_set_irq(void *opaque, int irq, int level)
65 7233b355 ths
{
66 7233b355 ths
        mst_irq_state *s = (mst_irq_state *)opaque;
67 7233b355 ths
68 7233b355 ths
        if (level)
69 7233b355 ths
                s->prev_level |= 1u << irq;
70 7233b355 ths
        else
71 7233b355 ths
                s->prev_level &= ~(1u << irq);
72 7233b355 ths
73 7233b355 ths
        if(s->intmskena & (1u << irq)) {
74 7233b355 ths
                s->intsetclr = 1u << irq;
75 7233b355 ths
                qemu_set_irq(s->parent[0], level);
76 7233b355 ths
        }
77 7233b355 ths
}
78 7233b355 ths
79 7233b355 ths
80 7233b355 ths
static uint32_t
81 c227f099 Anthony Liguori
mst_fpga_readb(void *opaque, target_phys_addr_t addr)
82 7233b355 ths
{
83 7233b355 ths
        mst_irq_state *s = (mst_irq_state *) opaque;
84 7233b355 ths
85 7233b355 ths
        switch (addr) {
86 7233b355 ths
        case MST_LEDDAT1:
87 7233b355 ths
                return s->leddat1;
88 7233b355 ths
        case MST_LEDDAT2:
89 7233b355 ths
                return s->leddat2;
90 7233b355 ths
        case MST_LEDCTRL:
91 7233b355 ths
                return s->ledctrl;
92 7233b355 ths
        case MST_GPSWR:
93 7233b355 ths
                return s->gpswr;
94 7233b355 ths
        case MST_MSCWR1:
95 7233b355 ths
                return s->mscwr1;
96 7233b355 ths
        case MST_MSCWR2:
97 7233b355 ths
                return s->mscwr2;
98 7233b355 ths
        case MST_MSCWR3:
99 7233b355 ths
                return s->mscwr3;
100 7233b355 ths
        case MST_MSCRD:
101 7233b355 ths
                return s->mscrd;
102 7233b355 ths
        case MST_INTMSKENA:
103 7233b355 ths
                return s->intmskena;
104 7233b355 ths
        case MST_INTSETCLR:
105 7233b355 ths
                return s->intsetclr;
106 7233b355 ths
        case MST_PCMCIA0:
107 7233b355 ths
                return s->pcmcia0;
108 7233b355 ths
        case MST_PCMCIA1:
109 7233b355 ths
                return s->pcmcia1;
110 7233b355 ths
        default:
111 7233b355 ths
                printf("Mainstone - mst_fpga_readb: Bad register offset "
112 7233b355 ths
                        REG_FMT " \n", addr);
113 7233b355 ths
        }
114 7233b355 ths
        return 0;
115 7233b355 ths
}
116 7233b355 ths
117 7233b355 ths
static void
118 c227f099 Anthony Liguori
mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
119 7233b355 ths
{
120 7233b355 ths
        mst_irq_state *s = (mst_irq_state *) opaque;
121 7233b355 ths
        value &= 0xffffffff;
122 7233b355 ths
123 7233b355 ths
        switch (addr) {
124 7233b355 ths
        case MST_LEDDAT1:
125 7233b355 ths
                s->leddat1 = value;
126 7233b355 ths
                break;
127 7233b355 ths
        case MST_LEDDAT2:
128 7233b355 ths
                s->leddat2 = value;
129 7233b355 ths
                break;
130 7233b355 ths
        case MST_LEDCTRL:
131 7233b355 ths
                s->ledctrl = value;
132 7233b355 ths
                break;
133 7233b355 ths
        case MST_GPSWR:
134 7233b355 ths
                s->gpswr = value;
135 7233b355 ths
                break;
136 7233b355 ths
        case MST_MSCWR1:
137 7233b355 ths
                s->mscwr1 = value;
138 7233b355 ths
                break;
139 7233b355 ths
        case MST_MSCWR2:
140 7233b355 ths
                s->mscwr2 = value;
141 7233b355 ths
                break;
142 7233b355 ths
        case MST_MSCWR3:
143 7233b355 ths
                s->mscwr3 = value;
144 7233b355 ths
                break;
145 7233b355 ths
        case MST_MSCRD:
146 7233b355 ths
                s->mscrd =  value;
147 7233b355 ths
                break;
148 7233b355 ths
        case MST_INTMSKENA:        /* Mask interupt */
149 7233b355 ths
                s->intmskena = (value & 0xFEEFF);
150 7233b355 ths
                mst_fpga_update_gpio(s);
151 7233b355 ths
                break;
152 7233b355 ths
        case MST_INTSETCLR:        /* clear or set interrupt */
153 7233b355 ths
                s->intsetclr = (value & 0xFEEFF);
154 7233b355 ths
                break;
155 7233b355 ths
        case MST_PCMCIA0:
156 7233b355 ths
                s->pcmcia0 = value;
157 7233b355 ths
                break;
158 7233b355 ths
        case MST_PCMCIA1:
159 7233b355 ths
                s->pcmcia1 = value;
160 7233b355 ths
                break;
161 7233b355 ths
        default:
162 7233b355 ths
                printf("Mainstone - mst_fpga_writeb: Bad register offset "
163 7233b355 ths
                        REG_FMT " \n", addr);
164 7233b355 ths
        }
165 7233b355 ths
}
166 7233b355 ths
167 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
168 7233b355 ths
        mst_fpga_readb,
169 7233b355 ths
        mst_fpga_readb,
170 7233b355 ths
        mst_fpga_readb,
171 7233b355 ths
};
172 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
173 7233b355 ths
        mst_fpga_writeb,
174 7233b355 ths
        mst_fpga_writeb,
175 7233b355 ths
        mst_fpga_writeb,
176 7233b355 ths
};
177 7233b355 ths
178 7233b355 ths
static void
179 7233b355 ths
mst_fpga_save(QEMUFile *f, void *opaque)
180 7233b355 ths
{
181 7233b355 ths
        struct mst_irq_state *s = (mst_irq_state *) opaque;
182 7233b355 ths
183 7233b355 ths
        qemu_put_be32s(f, &s->prev_level);
184 7233b355 ths
        qemu_put_be32s(f, &s->leddat1);
185 7233b355 ths
        qemu_put_be32s(f, &s->leddat2);
186 7233b355 ths
        qemu_put_be32s(f, &s->ledctrl);
187 7233b355 ths
        qemu_put_be32s(f, &s->gpswr);
188 7233b355 ths
        qemu_put_be32s(f, &s->mscwr1);
189 7233b355 ths
        qemu_put_be32s(f, &s->mscwr2);
190 7233b355 ths
        qemu_put_be32s(f, &s->mscwr3);
191 7233b355 ths
        qemu_put_be32s(f, &s->mscrd);
192 7233b355 ths
        qemu_put_be32s(f, &s->intmskena);
193 7233b355 ths
        qemu_put_be32s(f, &s->intsetclr);
194 7233b355 ths
        qemu_put_be32s(f, &s->pcmcia0);
195 7233b355 ths
        qemu_put_be32s(f, &s->pcmcia1);
196 7233b355 ths
}
197 7233b355 ths
198 7233b355 ths
static int
199 7233b355 ths
mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
200 7233b355 ths
{
201 7233b355 ths
        mst_irq_state *s = (mst_irq_state *) opaque;
202 7233b355 ths
203 7233b355 ths
        qemu_get_be32s(f, &s->prev_level);
204 7233b355 ths
        qemu_get_be32s(f, &s->leddat1);
205 7233b355 ths
        qemu_get_be32s(f, &s->leddat2);
206 7233b355 ths
        qemu_get_be32s(f, &s->ledctrl);
207 7233b355 ths
        qemu_get_be32s(f, &s->gpswr);
208 7233b355 ths
        qemu_get_be32s(f, &s->mscwr1);
209 7233b355 ths
        qemu_get_be32s(f, &s->mscwr2);
210 7233b355 ths
        qemu_get_be32s(f, &s->mscwr3);
211 7233b355 ths
        qemu_get_be32s(f, &s->mscrd);
212 7233b355 ths
        qemu_get_be32s(f, &s->intmskena);
213 7233b355 ths
        qemu_get_be32s(f, &s->intsetclr);
214 7233b355 ths
        qemu_get_be32s(f, &s->pcmcia0);
215 7233b355 ths
        qemu_get_be32s(f, &s->pcmcia1);
216 7233b355 ths
        return 0;
217 7233b355 ths
}
218 7233b355 ths
219 bc24a225 Paul Brook
qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
220 7233b355 ths
{
221 7233b355 ths
        mst_irq_state *s;
222 7233b355 ths
        int iomemtype;
223 7233b355 ths
        qemu_irq *qi;
224 7233b355 ths
225 7233b355 ths
        s = (mst_irq_state  *)
226 7233b355 ths
                qemu_mallocz(sizeof(mst_irq_state));
227 7233b355 ths
228 7233b355 ths
        s->parent = &cpu->pic[irq];
229 7233b355 ths
230 7233b355 ths
        /* alloc the external 16 irqs */
231 7233b355 ths
        qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
232 7233b355 ths
        s->pins = qi;
233 7233b355 ths
234 1eed09cb Avi Kivity
        iomemtype = cpu_register_io_memory(mst_fpga_readfn,
235 7233b355 ths
                mst_fpga_writefn, s);
236 8da3ff18 pbrook
        cpu_register_physical_memory(base, 0x00100000, iomemtype);
237 0be71e32 Alex Williamson
        register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
238 0be71e32 Alex Williamson
                        mst_fpga_load, s);
239 7233b355 ths
        return qi;
240 7233b355 ths
}