root / hw / sun4m.c @ 43ad7e3e
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 9d07d757 | Paul Brook | #include "sysbus.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 1cd3af54 | Gerd Hoffmann | #include "esp.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
38 | b4ed08e0 | blueswir1 | #include "escc.h" |
39 | 676d9b9b | Artyom Tarasenko | #include "empty_slot.h" |
40 | 4b48bf05 | Blue Swirl | #include "qdev-addr.h" |
41 | ca20cf32 | Blue Swirl | #include "loader.h" |
42 | ca20cf32 | Blue Swirl | #include "elf.h" |
43 | 2446333c | Blue Swirl | #include "blockdev.h" |
44 | 97bf4851 | Blue Swirl | #include "trace.h" |
45 | 420557e8 | bellard | |
46 | 36cd9210 | blueswir1 | /*
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47 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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48 | 36cd9210 | blueswir1 | *
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49 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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50 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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51 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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52 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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53 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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54 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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55 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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56 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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57 | 36cd9210 | blueswir1 | * SPARCstation 4
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58 | 36cd9210 | blueswir1 | *
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59 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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60 | 7d85892b | blueswir1 | *
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61 | 7d85892b | blueswir1 | * SPARCcenter 2000
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62 | 7d85892b | blueswir1 | * SPARCserver 1000
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63 | 7d85892b | blueswir1 | *
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64 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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65 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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66 | ee76f82e | blueswir1 | * SPARCstation SLC
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67 | ee76f82e | blueswir1 | * SPARCstation IPC
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68 | ee76f82e | blueswir1 | * SPARCstation ELC
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69 | ee76f82e | blueswir1 | * SPARCstation IPX
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70 | ee76f82e | blueswir1 | *
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71 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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72 | 36cd9210 | blueswir1 | */
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73 | 36cd9210 | blueswir1 | |
74 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
75 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
76 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
77 | a7227727 | blueswir1 | #define PROM_SIZE_MAX (1024 * 1024) |
78 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
79 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
80 | 3cce6243 | blueswir1 | #define CFG_ADDR 0xd00000510ULL |
81 | fbfcf955 | blueswir1 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
82 | b8174937 | bellard | |
83 | ba3c64fb | bellard | #define MAX_CPUS 16 |
84 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
85 | 9a62fb24 | Bob Breuer | #define MAX_VSIMMS 4 |
86 | 420557e8 | bellard | |
87 | b4ed08e0 | blueswir1 | #define ESCC_CLOCK 4915200 |
88 | b4ed08e0 | blueswir1 | |
89 | 8137cde8 | blueswir1 | struct sun4m_hwdef {
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90 | 3386376c | Artyom Tarasenko | target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
91 | c227f099 | Anthony Liguori | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
92 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base, fd_base; |
93 | c5de386a | Artyom Tarasenko | target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; |
94 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
95 | 9a62fb24 | Bob Breuer | target_phys_addr_t bpp_base, dbri_base, sx_base; |
96 | 9a62fb24 | Bob Breuer | struct {
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97 | 9a62fb24 | Bob Breuer | target_phys_addr_t reg_base, vram_base; |
98 | 9a62fb24 | Bob Breuer | } vsimm[MAX_VSIMMS]; |
99 | c227f099 | Anthony Liguori | target_phys_addr_t ecc_base; |
100 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
101 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
102 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
103 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
104 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
105 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
106 | 36cd9210 | blueswir1 | }; |
107 | 36cd9210 | blueswir1 | |
108 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
109 | 7d85892b | blueswir1 | |
110 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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111 | c227f099 | Anthony Liguori | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
112 | c227f099 | Anthony Liguori | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
113 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base; |
114 | c227f099 | Anthony Liguori | target_phys_addr_t espdma_base, esp_base; |
115 | c227f099 | Anthony Liguori | target_phys_addr_t ledma_base, le_base; |
116 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base; |
117 | c227f099 | Anthony Liguori | target_phys_addr_t sbi_base; |
118 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
119 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
120 | 7d85892b | blueswir1 | uint32_t iounit_version; |
121 | 7d85892b | blueswir1 | uint64_t max_mem; |
122 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
123 | 7d85892b | blueswir1 | }; |
124 | 7d85892b | blueswir1 | |
125 | 8137cde8 | blueswir1 | struct sun4c_hwdef {
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126 | c227f099 | Anthony Liguori | target_phys_addr_t iommu_base, slavio_base; |
127 | c227f099 | Anthony Liguori | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
128 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base, fd_base; |
129 | c227f099 | Anthony Liguori | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
130 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base, aux1_base; |
131 | 8137cde8 | blueswir1 | uint8_t nvram_machine_id; |
132 | 8137cde8 | blueswir1 | uint16_t machine_id; |
133 | 8137cde8 | blueswir1 | uint32_t iommu_version; |
134 | 8137cde8 | blueswir1 | uint64_t max_mem; |
135 | 8137cde8 | blueswir1 | const char * const default_cpu_model; |
136 | 8137cde8 | blueswir1 | }; |
137 | 8137cde8 | blueswir1 | |
138 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
139 | 6f7e9aec | bellard | { |
140 | 6f7e9aec | bellard | return 0; |
141 | 6f7e9aec | bellard | } |
142 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
143 | 6f7e9aec | bellard | { |
144 | 6f7e9aec | bellard | return 0; |
145 | 6f7e9aec | bellard | } |
146 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
147 | 6f7e9aec | bellard | { |
148 | 6f7e9aec | bellard | return 0; |
149 | 6f7e9aec | bellard | } |
150 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
151 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
152 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
153 | 4556bd8b | Blue Swirl | |
154 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
155 | 4556bd8b | Blue Swirl | { |
156 | 4556bd8b | Blue Swirl | } |
157 | 4556bd8b | Blue Swirl | |
158 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
159 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
160 | 6f7e9aec | bellard | void *opaque)
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161 | 6f7e9aec | bellard | { |
162 | 6f7e9aec | bellard | } |
163 | 6f7e9aec | bellard | |
164 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
165 | 81864572 | blueswir1 | { |
166 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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167 | 81864572 | blueswir1 | return 0; |
168 | 81864572 | blueswir1 | } |
169 | 81864572 | blueswir1 | |
170 | 43a34704 | Blue Swirl | static void nvram_init(M48t59State *nvram, uint8_t *macaddr, |
171 | 43a34704 | Blue Swirl | const char *cmdline, const char *boot_devices, |
172 | 43a34704 | Blue Swirl | ram_addr_t RAM_size, uint32_t kernel_size, |
173 | f930d07e | blueswir1 | int width, int height, int depth, |
174 | 905fdcb5 | blueswir1 | int nvram_machine_id, const char *arch) |
175 | e80cfcfc | bellard | { |
176 | d2c63fc1 | blueswir1 | unsigned int i; |
177 | 66508601 | blueswir1 | uint32_t start, end; |
178 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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179 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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180 | d2c63fc1 | blueswir1 | |
181 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
182 | e80cfcfc | bellard | |
183 | 513f789f | blueswir1 | start = 0;
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184 | b6f479d3 | bellard | |
185 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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186 | 66508601 | blueswir1 | // Variable partition
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187 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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188 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
189 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
190 | 66508601 | blueswir1 | |
191 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
192 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
193 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
194 | d2c63fc1 | blueswir1 | |
195 | d2c63fc1 | blueswir1 | // End marker
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196 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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197 | 66508601 | blueswir1 | |
198 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
199 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
200 | 66508601 | blueswir1 | |
201 | 66508601 | blueswir1 | // free partition
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202 | 66508601 | blueswir1 | start = end; |
203 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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204 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
205 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
206 | 66508601 | blueswir1 | |
207 | 66508601 | blueswir1 | end = 0x1fd0;
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208 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
209 | d2c63fc1 | blueswir1 | |
210 | 905fdcb5 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
211 | 905fdcb5 | blueswir1 | nvram_machine_id); |
212 | d2c63fc1 | blueswir1 | |
213 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
214 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
215 | e80cfcfc | bellard | } |
216 | e80cfcfc | bellard | |
217 | d453c2c3 | Blue Swirl | static DeviceState *slavio_intctl;
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218 | e80cfcfc | bellard | |
219 | 376253ec | aliguori | void pic_info(Monitor *mon)
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220 | e80cfcfc | bellard | { |
221 | 7d85892b | blueswir1 | if (slavio_intctl)
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222 | 376253ec | aliguori | slavio_pic_info(mon, slavio_intctl); |
223 | e80cfcfc | bellard | } |
224 | e80cfcfc | bellard | |
225 | 376253ec | aliguori | void irq_info(Monitor *mon)
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226 | e80cfcfc | bellard | { |
227 | 7d85892b | blueswir1 | if (slavio_intctl)
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228 | 376253ec | aliguori | slavio_irq_info(mon, slavio_intctl); |
229 | e80cfcfc | bellard | } |
230 | e80cfcfc | bellard | |
231 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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232 | 327ac2e7 | blueswir1 | { |
233 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
234 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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235 | 327ac2e7 | blueswir1 | unsigned int i; |
236 | 327ac2e7 | blueswir1 | |
237 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
238 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
239 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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240 | 327ac2e7 | blueswir1 | |
241 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
242 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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243 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_interrupt(i); |
244 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
245 | f32d7ec5 | blueswir1 | } |
246 | 327ac2e7 | blueswir1 | break;
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247 | 327ac2e7 | blueswir1 | } |
248 | 327ac2e7 | blueswir1 | } |
249 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
250 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
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251 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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252 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
253 | 327ac2e7 | blueswir1 | } |
254 | 327ac2e7 | blueswir1 | } |
255 | 327ac2e7 | blueswir1 | |
256 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
257 | b3a23197 | blueswir1 | { |
258 | b3a23197 | blueswir1 | CPUState *env = opaque; |
259 | b3a23197 | blueswir1 | |
260 | b3a23197 | blueswir1 | if (level) {
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261 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_set_irq_raise(irq); |
262 | b3a23197 | blueswir1 | env->halted = 0;
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263 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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264 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
265 | b3a23197 | blueswir1 | } else {
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266 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_set_irq_lower(irq); |
267 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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268 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
269 | b3a23197 | blueswir1 | } |
270 | b3a23197 | blueswir1 | } |
271 | b3a23197 | blueswir1 | |
272 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
273 | b3a23197 | blueswir1 | { |
274 | b3a23197 | blueswir1 | } |
275 | b3a23197 | blueswir1 | |
276 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
277 | c68ea704 | bellard | { |
278 | c68ea704 | bellard | CPUState *env = opaque; |
279 | 3d29fbef | blueswir1 | |
280 | 3d29fbef | blueswir1 | cpu_reset(env); |
281 | 3d29fbef | blueswir1 | env->halted = 0;
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282 | 3d29fbef | blueswir1 | } |
283 | 3d29fbef | blueswir1 | |
284 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
285 | 3d29fbef | blueswir1 | { |
286 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
287 | 3d29fbef | blueswir1 | |
288 | c68ea704 | bellard | cpu_reset(env); |
289 | 3d29fbef | blueswir1 | env->halted = 1;
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290 | c68ea704 | bellard | } |
291 | c68ea704 | bellard | |
292 | 6d0c293d | blueswir1 | static void cpu_halt_signal(void *opaque, int irq, int level) |
293 | 6d0c293d | blueswir1 | { |
294 | 6d0c293d | blueswir1 | if (level && cpu_single_env)
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295 | 6d0c293d | blueswir1 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
296 | 6d0c293d | blueswir1 | } |
297 | 6d0c293d | blueswir1 | |
298 | 409dbce5 | Aurelien Jarno | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
299 | 409dbce5 | Aurelien Jarno | { |
300 | 409dbce5 | Aurelien Jarno | return addr - 0xf0000000ULL; |
301 | 409dbce5 | Aurelien Jarno | } |
302 | 409dbce5 | Aurelien Jarno | |
303 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
304 | 293f78bc | blueswir1 | const char *initrd_filename, |
305 | c227f099 | Anthony Liguori | ram_addr_t RAM_size) |
306 | 3ebf5aaf | blueswir1 | { |
307 | 3ebf5aaf | blueswir1 | int linux_boot;
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308 | 3ebf5aaf | blueswir1 | unsigned int i; |
309 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
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310 | 3c178e72 | Gerd Hoffmann | uint8_t *ptr; |
311 | 3ebf5aaf | blueswir1 | |
312 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
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313 | 3ebf5aaf | blueswir1 | |
314 | 3ebf5aaf | blueswir1 | kernel_size = 0;
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315 | 3ebf5aaf | blueswir1 | if (linux_boot) {
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316 | ca20cf32 | Blue Swirl | int bswap_needed;
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317 | ca20cf32 | Blue Swirl | |
318 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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319 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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320 | ca20cf32 | Blue Swirl | #else
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321 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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322 | ca20cf32 | Blue Swirl | #endif
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323 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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324 | 409dbce5 | Aurelien Jarno | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
325 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
326 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
327 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
328 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
329 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
330 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
331 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
332 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
333 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
334 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
335 | 3ebf5aaf | blueswir1 | kernel_filename); |
336 | 3ebf5aaf | blueswir1 | exit(1);
|
337 | 3ebf5aaf | blueswir1 | } |
338 | 3ebf5aaf | blueswir1 | |
339 | 3ebf5aaf | blueswir1 | /* load initrd */
|
340 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
341 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
342 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
343 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
344 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
345 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
346 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
347 | 3ebf5aaf | blueswir1 | initrd_filename); |
348 | 3ebf5aaf | blueswir1 | exit(1);
|
349 | 3ebf5aaf | blueswir1 | } |
350 | 3ebf5aaf | blueswir1 | } |
351 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
352 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
353 | 3c178e72 | Gerd Hoffmann | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
354 | 3c178e72 | Gerd Hoffmann | if (ldl_p(ptr) == 0x48647253) { // HdrS |
355 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 16, INITRD_LOAD_ADDR);
|
356 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 20, initrd_size);
|
357 | 3ebf5aaf | blueswir1 | break;
|
358 | 3ebf5aaf | blueswir1 | } |
359 | 3ebf5aaf | blueswir1 | } |
360 | 3ebf5aaf | blueswir1 | } |
361 | 3ebf5aaf | blueswir1 | } |
362 | 3ebf5aaf | blueswir1 | return kernel_size;
|
363 | 3ebf5aaf | blueswir1 | } |
364 | 3ebf5aaf | blueswir1 | |
365 | c227f099 | Anthony Liguori | static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
366 | 4b48bf05 | Blue Swirl | { |
367 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
368 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
369 | 4b48bf05 | Blue Swirl | |
370 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "iommu"); |
371 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
372 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
373 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
374 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
375 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
376 | 4b48bf05 | Blue Swirl | |
377 | 4b48bf05 | Blue Swirl | return s;
|
378 | 4b48bf05 | Blue Swirl | } |
379 | 4b48bf05 | Blue Swirl | |
380 | c227f099 | Anthony Liguori | static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
381 | 74ff8d90 | Blue Swirl | void *iommu, qemu_irq *dev_irq)
|
382 | 74ff8d90 | Blue Swirl | { |
383 | 74ff8d90 | Blue Swirl | DeviceState *dev; |
384 | 74ff8d90 | Blue Swirl | SysBusDevice *s; |
385 | 74ff8d90 | Blue Swirl | |
386 | 74ff8d90 | Blue Swirl | dev = qdev_create(NULL, "sparc32_dma"); |
387 | 74ff8d90 | Blue Swirl | qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
|
388 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
389 | 74ff8d90 | Blue Swirl | s = sysbus_from_qdev(dev); |
390 | 74ff8d90 | Blue Swirl | sysbus_connect_irq(s, 0, parent_irq);
|
391 | 74ff8d90 | Blue Swirl | *dev_irq = qdev_get_gpio_in(dev, 0);
|
392 | 74ff8d90 | Blue Swirl | sysbus_mmio_map(s, 0, daddr);
|
393 | 74ff8d90 | Blue Swirl | |
394 | 74ff8d90 | Blue Swirl | return s;
|
395 | 74ff8d90 | Blue Swirl | } |
396 | 74ff8d90 | Blue Swirl | |
397 | c227f099 | Anthony Liguori | static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
398 | 74ff8d90 | Blue Swirl | void *dma_opaque, qemu_irq irq)
|
399 | 9d07d757 | Paul Brook | { |
400 | 9d07d757 | Paul Brook | DeviceState *dev; |
401 | 9d07d757 | Paul Brook | SysBusDevice *s; |
402 | 74ff8d90 | Blue Swirl | qemu_irq reset; |
403 | 9d07d757 | Paul Brook | |
404 | 9d07d757 | Paul Brook | qemu_check_nic_model(&nd_table[0], "lance"); |
405 | 9d07d757 | Paul Brook | |
406 | 9d07d757 | Paul Brook | dev = qdev_create(NULL, "lance"); |
407 | 76224833 | Gerd Hoffmann | qdev_set_nic_properties(dev, nd); |
408 | daa65491 | Blue Swirl | qdev_prop_set_ptr(dev, "dma", dma_opaque);
|
409 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
410 | 9d07d757 | Paul Brook | s = sysbus_from_qdev(dev); |
411 | 9d07d757 | Paul Brook | sysbus_mmio_map(s, 0, leaddr);
|
412 | 9d07d757 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
413 | 74ff8d90 | Blue Swirl | reset = qdev_get_gpio_in(dev, 0);
|
414 | 74ff8d90 | Blue Swirl | qdev_connect_gpio_out(dma_opaque, 0, reset);
|
415 | 9d07d757 | Paul Brook | } |
416 | 9d07d757 | Paul Brook | |
417 | c227f099 | Anthony Liguori | static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
|
418 | c227f099 | Anthony Liguori | target_phys_addr_t addrg, |
419 | 462eda24 | Blue Swirl | qemu_irq **parent_irq) |
420 | 4b48bf05 | Blue Swirl | { |
421 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
422 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
423 | 4b48bf05 | Blue Swirl | unsigned int i, j; |
424 | 4b48bf05 | Blue Swirl | |
425 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_intctl"); |
426 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
427 | 4b48bf05 | Blue Swirl | |
428 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
429 | 4b48bf05 | Blue Swirl | |
430 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
431 | 4b48bf05 | Blue Swirl | for (j = 0; j < MAX_PILS; j++) { |
432 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
433 | 4b48bf05 | Blue Swirl | } |
434 | 4b48bf05 | Blue Swirl | } |
435 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addrg);
|
436 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
437 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
438 | 4b48bf05 | Blue Swirl | } |
439 | 4b48bf05 | Blue Swirl | |
440 | 4b48bf05 | Blue Swirl | return dev;
|
441 | 4b48bf05 | Blue Swirl | } |
442 | 4b48bf05 | Blue Swirl | |
443 | 4b48bf05 | Blue Swirl | #define SYS_TIMER_OFFSET 0x10000ULL |
444 | 4b48bf05 | Blue Swirl | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
445 | 4b48bf05 | Blue Swirl | |
446 | c227f099 | Anthony Liguori | static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
447 | 4b48bf05 | Blue Swirl | qemu_irq *cpu_irqs, unsigned int num_cpus) |
448 | 4b48bf05 | Blue Swirl | { |
449 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
450 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
451 | 4b48bf05 | Blue Swirl | unsigned int i; |
452 | 4b48bf05 | Blue Swirl | |
453 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_timer"); |
454 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
455 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
456 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
457 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, master_irq);
|
458 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
459 | 4b48bf05 | Blue Swirl | |
460 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
461 | c227f099 | Anthony Liguori | sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
|
462 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
|
463 | 4b48bf05 | Blue Swirl | } |
464 | 4b48bf05 | Blue Swirl | } |
465 | 4b48bf05 | Blue Swirl | |
466 | 4b48bf05 | Blue Swirl | #define MISC_LEDS 0x01600000 |
467 | 4b48bf05 | Blue Swirl | #define MISC_CFG 0x01800000 |
468 | 4b48bf05 | Blue Swirl | #define MISC_DIAG 0x01a00000 |
469 | 4b48bf05 | Blue Swirl | #define MISC_MDM 0x01b00000 |
470 | 4b48bf05 | Blue Swirl | #define MISC_SYS 0x01f00000 |
471 | 4b48bf05 | Blue Swirl | |
472 | c227f099 | Anthony Liguori | static void slavio_misc_init(target_phys_addr_t base, |
473 | c227f099 | Anthony Liguori | target_phys_addr_t aux1_base, |
474 | c227f099 | Anthony Liguori | target_phys_addr_t aux2_base, qemu_irq irq, |
475 | b2b6f6ec | Blue Swirl | qemu_irq fdc_tc) |
476 | 4b48bf05 | Blue Swirl | { |
477 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
478 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
479 | 4b48bf05 | Blue Swirl | |
480 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_misc"); |
481 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
482 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
483 | 4b48bf05 | Blue Swirl | if (base) {
|
484 | 4b48bf05 | Blue Swirl | /* 8 bit registers */
|
485 | 4b48bf05 | Blue Swirl | /* Slavio control */
|
486 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base + MISC_CFG);
|
487 | 4b48bf05 | Blue Swirl | /* Diagnostics */
|
488 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
489 | 4b48bf05 | Blue Swirl | /* Modem control */
|
490 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, base + MISC_MDM);
|
491 | 4b48bf05 | Blue Swirl | /* 16 bit registers */
|
492 | 4b48bf05 | Blue Swirl | /* ss600mp diag LEDs */
|
493 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
494 | 4b48bf05 | Blue Swirl | /* 32 bit registers */
|
495 | 4b48bf05 | Blue Swirl | /* System control */
|
496 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, base + MISC_SYS);
|
497 | 4b48bf05 | Blue Swirl | } |
498 | 4b48bf05 | Blue Swirl | if (aux1_base) {
|
499 | 4b48bf05 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
500 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, aux1_base);
|
501 | 4b48bf05 | Blue Swirl | } |
502 | 4b48bf05 | Blue Swirl | if (aux2_base) {
|
503 | 4b48bf05 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
504 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 6, aux2_base);
|
505 | 4b48bf05 | Blue Swirl | } |
506 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
507 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 1, fdc_tc);
|
508 | d9c32310 | Blue Swirl | qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
509 | 4b48bf05 | Blue Swirl | } |
510 | 4b48bf05 | Blue Swirl | |
511 | c227f099 | Anthony Liguori | static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
512 | 4b48bf05 | Blue Swirl | { |
513 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
514 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
515 | 4b48bf05 | Blue Swirl | |
516 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "eccmemctl"); |
517 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
518 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
519 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
520 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
521 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base);
|
522 | 4b48bf05 | Blue Swirl | if (version == 0) { // SS-600MP only |
523 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + 0x1000); |
524 | 4b48bf05 | Blue Swirl | } |
525 | 4b48bf05 | Blue Swirl | } |
526 | 4b48bf05 | Blue Swirl | |
527 | c227f099 | Anthony Liguori | static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
528 | 4b48bf05 | Blue Swirl | { |
529 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
530 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
531 | 4b48bf05 | Blue Swirl | |
532 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "apc"); |
533 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
534 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
535 | 4b48bf05 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
536 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, power_base);
|
537 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, cpu_halt);
|
538 | 4b48bf05 | Blue Swirl | } |
539 | 4b48bf05 | Blue Swirl | |
540 | c227f099 | Anthony Liguori | static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
541 | 4b48bf05 | Blue Swirl | int height, int depth) |
542 | 4b48bf05 | Blue Swirl | { |
543 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
544 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
545 | 4b48bf05 | Blue Swirl | |
546 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "SUNW,tcx"); |
547 | 4b48bf05 | Blue Swirl | qdev_prop_set_taddr(dev, "addr", addr);
|
548 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
549 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "width", width);
|
550 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "height", height);
|
551 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "depth", depth);
|
552 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
553 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
554 | 4b48bf05 | Blue Swirl | /* 8-bit plane */
|
555 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
556 | 4b48bf05 | Blue Swirl | /* DAC */
|
557 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
558 | 4b48bf05 | Blue Swirl | /* TEC (dummy) */
|
559 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
560 | 4b48bf05 | Blue Swirl | /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
561 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
562 | 4b48bf05 | Blue Swirl | if (depth == 24) { |
563 | 4b48bf05 | Blue Swirl | /* 24-bit plane */
|
564 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
565 | 4b48bf05 | Blue Swirl | /* Control plane */
|
566 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
567 | 4b48bf05 | Blue Swirl | } else {
|
568 | 4b48bf05 | Blue Swirl | /* THC 8 bit (dummy) */
|
569 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
570 | 4b48bf05 | Blue Swirl | } |
571 | 4b48bf05 | Blue Swirl | } |
572 | 4b48bf05 | Blue Swirl | |
573 | 325f2747 | Blue Swirl | /* NCR89C100/MACIO Internal ID register */
|
574 | 325f2747 | Blue Swirl | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
575 | 325f2747 | Blue Swirl | |
576 | c227f099 | Anthony Liguori | static void idreg_init(target_phys_addr_t addr) |
577 | 325f2747 | Blue Swirl | { |
578 | 325f2747 | Blue Swirl | DeviceState *dev; |
579 | 325f2747 | Blue Swirl | SysBusDevice *s; |
580 | 325f2747 | Blue Swirl | |
581 | 325f2747 | Blue Swirl | dev = qdev_create(NULL, "macio_idreg"); |
582 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
583 | 325f2747 | Blue Swirl | s = sysbus_from_qdev(dev); |
584 | 325f2747 | Blue Swirl | |
585 | 325f2747 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
586 | 325f2747 | Blue Swirl | cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
587 | 325f2747 | Blue Swirl | } |
588 | 325f2747 | Blue Swirl | |
589 | 81a322d4 | Gerd Hoffmann | static int idreg_init1(SysBusDevice *dev) |
590 | 325f2747 | Blue Swirl | { |
591 | c227f099 | Anthony Liguori | ram_addr_t idreg_offset; |
592 | 325f2747 | Blue Swirl | |
593 | 1724f049 | Alex Williamson | idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data)); |
594 | 325f2747 | Blue Swirl | sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
|
595 | 81a322d4 | Gerd Hoffmann | return 0; |
596 | 325f2747 | Blue Swirl | } |
597 | 325f2747 | Blue Swirl | |
598 | 325f2747 | Blue Swirl | static SysBusDeviceInfo idreg_info = {
|
599 | 325f2747 | Blue Swirl | .init = idreg_init1, |
600 | 325f2747 | Blue Swirl | .qdev.name = "macio_idreg",
|
601 | 325f2747 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
602 | 325f2747 | Blue Swirl | }; |
603 | 325f2747 | Blue Swirl | |
604 | 325f2747 | Blue Swirl | static void idreg_register_devices(void) |
605 | 325f2747 | Blue Swirl | { |
606 | 325f2747 | Blue Swirl | sysbus_register_withprop(&idreg_info); |
607 | 325f2747 | Blue Swirl | } |
608 | 325f2747 | Blue Swirl | |
609 | 325f2747 | Blue Swirl | device_init(idreg_register_devices); |
610 | 325f2747 | Blue Swirl | |
611 | c5de386a | Artyom Tarasenko | /* SS-5 TCX AFX register */
|
612 | c5de386a | Artyom Tarasenko | static void afx_init(target_phys_addr_t addr) |
613 | c5de386a | Artyom Tarasenko | { |
614 | c5de386a | Artyom Tarasenko | DeviceState *dev; |
615 | c5de386a | Artyom Tarasenko | SysBusDevice *s; |
616 | c5de386a | Artyom Tarasenko | |
617 | c5de386a | Artyom Tarasenko | dev = qdev_create(NULL, "tcx_afx"); |
618 | c5de386a | Artyom Tarasenko | qdev_init_nofail(dev); |
619 | c5de386a | Artyom Tarasenko | s = sysbus_from_qdev(dev); |
620 | c5de386a | Artyom Tarasenko | |
621 | c5de386a | Artyom Tarasenko | sysbus_mmio_map(s, 0, addr);
|
622 | c5de386a | Artyom Tarasenko | } |
623 | c5de386a | Artyom Tarasenko | |
624 | c5de386a | Artyom Tarasenko | static int afx_init1(SysBusDevice *dev) |
625 | c5de386a | Artyom Tarasenko | { |
626 | c5de386a | Artyom Tarasenko | ram_addr_t afx_offset; |
627 | c5de386a | Artyom Tarasenko | |
628 | 1724f049 | Alex Williamson | afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4); |
629 | c5de386a | Artyom Tarasenko | sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
|
630 | c5de386a | Artyom Tarasenko | return 0; |
631 | c5de386a | Artyom Tarasenko | } |
632 | c5de386a | Artyom Tarasenko | |
633 | c5de386a | Artyom Tarasenko | static SysBusDeviceInfo afx_info = {
|
634 | c5de386a | Artyom Tarasenko | .init = afx_init1, |
635 | c5de386a | Artyom Tarasenko | .qdev.name = "tcx_afx",
|
636 | c5de386a | Artyom Tarasenko | .qdev.size = sizeof(SysBusDevice),
|
637 | c5de386a | Artyom Tarasenko | }; |
638 | c5de386a | Artyom Tarasenko | |
639 | c5de386a | Artyom Tarasenko | static void afx_register_devices(void) |
640 | c5de386a | Artyom Tarasenko | { |
641 | c5de386a | Artyom Tarasenko | sysbus_register_withprop(&afx_info); |
642 | c5de386a | Artyom Tarasenko | } |
643 | c5de386a | Artyom Tarasenko | |
644 | c5de386a | Artyom Tarasenko | device_init(afx_register_devices); |
645 | c5de386a | Artyom Tarasenko | |
646 | f48f6569 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
647 | 409dbce5 | Aurelien Jarno | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
648 | 409dbce5 | Aurelien Jarno | { |
649 | 409dbce5 | Aurelien Jarno | target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; |
650 | 409dbce5 | Aurelien Jarno | return addr + *base_addr - PROM_VADDR;
|
651 | 409dbce5 | Aurelien Jarno | } |
652 | 409dbce5 | Aurelien Jarno | |
653 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
654 | f48f6569 | Blue Swirl | { |
655 | f48f6569 | Blue Swirl | DeviceState *dev; |
656 | f48f6569 | Blue Swirl | SysBusDevice *s; |
657 | f48f6569 | Blue Swirl | char *filename;
|
658 | f48f6569 | Blue Swirl | int ret;
|
659 | f48f6569 | Blue Swirl | |
660 | f48f6569 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
661 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
662 | f48f6569 | Blue Swirl | s = sysbus_from_qdev(dev); |
663 | f48f6569 | Blue Swirl | |
664 | f48f6569 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
665 | f48f6569 | Blue Swirl | |
666 | f48f6569 | Blue Swirl | /* load boot prom */
|
667 | f48f6569 | Blue Swirl | if (bios_name == NULL) { |
668 | f48f6569 | Blue Swirl | bios_name = PROM_FILENAME; |
669 | f48f6569 | Blue Swirl | } |
670 | f48f6569 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
671 | f48f6569 | Blue Swirl | if (filename) {
|
672 | 409dbce5 | Aurelien Jarno | ret = load_elf(filename, translate_prom_address, &addr, NULL,
|
673 | 409dbce5 | Aurelien Jarno | NULL, NULL, 1, ELF_MACHINE, 0); |
674 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
675 | f48f6569 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
676 | f48f6569 | Blue Swirl | } |
677 | f48f6569 | Blue Swirl | qemu_free(filename); |
678 | f48f6569 | Blue Swirl | } else {
|
679 | f48f6569 | Blue Swirl | ret = -1;
|
680 | f48f6569 | Blue Swirl | } |
681 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
682 | f48f6569 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
683 | f48f6569 | Blue Swirl | exit(1);
|
684 | f48f6569 | Blue Swirl | } |
685 | f48f6569 | Blue Swirl | } |
686 | f48f6569 | Blue Swirl | |
687 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
688 | f48f6569 | Blue Swirl | { |
689 | c227f099 | Anthony Liguori | ram_addr_t prom_offset; |
690 | f48f6569 | Blue Swirl | |
691 | 1724f049 | Alex Williamson | prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX); |
692 | f48f6569 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
693 | 81a322d4 | Gerd Hoffmann | return 0; |
694 | f48f6569 | Blue Swirl | } |
695 | f48f6569 | Blue Swirl | |
696 | f48f6569 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
697 | f48f6569 | Blue Swirl | .init = prom_init1, |
698 | f48f6569 | Blue Swirl | .qdev.name = "openprom",
|
699 | f48f6569 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
700 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
701 | ee6847d1 | Gerd Hoffmann | {/* end of property list */}
|
702 | f48f6569 | Blue Swirl | } |
703 | f48f6569 | Blue Swirl | }; |
704 | f48f6569 | Blue Swirl | |
705 | f48f6569 | Blue Swirl | static void prom_register_devices(void) |
706 | f48f6569 | Blue Swirl | { |
707 | f48f6569 | Blue Swirl | sysbus_register_withprop(&prom_info); |
708 | f48f6569 | Blue Swirl | } |
709 | f48f6569 | Blue Swirl | |
710 | f48f6569 | Blue Swirl | device_init(prom_register_devices); |
711 | f48f6569 | Blue Swirl | |
712 | ee6847d1 | Gerd Hoffmann | typedef struct RamDevice |
713 | ee6847d1 | Gerd Hoffmann | { |
714 | ee6847d1 | Gerd Hoffmann | SysBusDevice busdev; |
715 | 04843626 | Blue Swirl | uint64_t size; |
716 | ee6847d1 | Gerd Hoffmann | } RamDevice; |
717 | ee6847d1 | Gerd Hoffmann | |
718 | a350db85 | Blue Swirl | /* System RAM */
|
719 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
720 | a350db85 | Blue Swirl | { |
721 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, ram_offset; |
722 | ee6847d1 | Gerd Hoffmann | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
723 | a350db85 | Blue Swirl | |
724 | ee6847d1 | Gerd Hoffmann | RAM_size = d->size; |
725 | a350db85 | Blue Swirl | |
726 | 1724f049 | Alex Williamson | ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size); |
727 | a350db85 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
728 | 81a322d4 | Gerd Hoffmann | return 0; |
729 | a350db85 | Blue Swirl | } |
730 | a350db85 | Blue Swirl | |
731 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
732 | a350db85 | Blue Swirl | uint64_t max_mem) |
733 | a350db85 | Blue Swirl | { |
734 | a350db85 | Blue Swirl | DeviceState *dev; |
735 | a350db85 | Blue Swirl | SysBusDevice *s; |
736 | ee6847d1 | Gerd Hoffmann | RamDevice *d; |
737 | a350db85 | Blue Swirl | |
738 | a350db85 | Blue Swirl | /* allocate RAM */
|
739 | a350db85 | Blue Swirl | if ((uint64_t)RAM_size > max_mem) {
|
740 | a350db85 | Blue Swirl | fprintf(stderr, |
741 | a350db85 | Blue Swirl | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
742 | a350db85 | Blue Swirl | (unsigned int)(RAM_size / (1024 * 1024)), |
743 | a350db85 | Blue Swirl | (unsigned int)(max_mem / (1024 * 1024))); |
744 | a350db85 | Blue Swirl | exit(1);
|
745 | a350db85 | Blue Swirl | } |
746 | a350db85 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
747 | a350db85 | Blue Swirl | s = sysbus_from_qdev(dev); |
748 | a350db85 | Blue Swirl | |
749 | ee6847d1 | Gerd Hoffmann | d = FROM_SYSBUS(RamDevice, s); |
750 | ee6847d1 | Gerd Hoffmann | d->size = RAM_size; |
751 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
752 | ee6847d1 | Gerd Hoffmann | |
753 | a350db85 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
754 | a350db85 | Blue Swirl | } |
755 | a350db85 | Blue Swirl | |
756 | a350db85 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
757 | a350db85 | Blue Swirl | .init = ram_init1, |
758 | a350db85 | Blue Swirl | .qdev.name = "memory",
|
759 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(RamDevice),
|
760 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
761 | c885159a | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
762 | c885159a | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
763 | a350db85 | Blue Swirl | } |
764 | a350db85 | Blue Swirl | }; |
765 | a350db85 | Blue Swirl | |
766 | a350db85 | Blue Swirl | static void ram_register_devices(void) |
767 | a350db85 | Blue Swirl | { |
768 | a350db85 | Blue Swirl | sysbus_register_withprop(&ram_info); |
769 | a350db85 | Blue Swirl | } |
770 | a350db85 | Blue Swirl | |
771 | a350db85 | Blue Swirl | device_init(ram_register_devices); |
772 | a350db85 | Blue Swirl | |
773 | 89835363 | Blue Swirl | static void cpu_devinit(const char *cpu_model, unsigned int id, |
774 | 89835363 | Blue Swirl | uint64_t prom_addr, qemu_irq **cpu_irqs) |
775 | 666713c0 | Blue Swirl | { |
776 | 666713c0 | Blue Swirl | CPUState *env; |
777 | 666713c0 | Blue Swirl | |
778 | 666713c0 | Blue Swirl | env = cpu_init(cpu_model); |
779 | 666713c0 | Blue Swirl | if (!env) {
|
780 | 666713c0 | Blue Swirl | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
781 | 666713c0 | Blue Swirl | exit(1);
|
782 | 666713c0 | Blue Swirl | } |
783 | 666713c0 | Blue Swirl | |
784 | 666713c0 | Blue Swirl | cpu_sparc_set_id(env, id); |
785 | 666713c0 | Blue Swirl | if (id == 0) { |
786 | 666713c0 | Blue Swirl | qemu_register_reset(main_cpu_reset, env); |
787 | 666713c0 | Blue Swirl | } else {
|
788 | 666713c0 | Blue Swirl | qemu_register_reset(secondary_cpu_reset, env); |
789 | 666713c0 | Blue Swirl | env->halted = 1;
|
790 | 666713c0 | Blue Swirl | } |
791 | 666713c0 | Blue Swirl | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
792 | 666713c0 | Blue Swirl | env->prom_addr = prom_addr; |
793 | 666713c0 | Blue Swirl | } |
794 | 666713c0 | Blue Swirl | |
795 | c227f099 | Anthony Liguori | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
796 | 3ebf5aaf | blueswir1 | const char *boot_device, |
797 | 3023f332 | aliguori | const char *kernel_filename, |
798 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
799 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
800 | 420557e8 | bellard | { |
801 | 713c45fa | bellard | unsigned int i; |
802 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
803 | a1961a4b | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
804 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
805 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
806 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
807 | 6d0c293d | blueswir1 | qemu_irq *cpu_halt; |
808 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
809 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
810 | 3cce6243 | blueswir1 | void *fw_cfg;
|
811 | 9a62fb24 | Bob Breuer | unsigned int num_vsimms; |
812 | 420557e8 | bellard | |
813 | ba3c64fb | bellard | /* init CPUs */
|
814 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
815 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
816 | b3a23197 | blueswir1 | |
817 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
818 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
819 | ba3c64fb | bellard | } |
820 | b3a23197 | blueswir1 | |
821 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
822 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
823 | b3a23197 | blueswir1 | |
824 | 3ebf5aaf | blueswir1 | |
825 | 3ebf5aaf | blueswir1 | /* set up devices */
|
826 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
827 | 676d9b9b | Artyom Tarasenko | /* models without ECC don't trap when missing ram is accessed */
|
828 | 676d9b9b | Artyom Tarasenko | if (!hwdef->ecc_base) {
|
829 | 676d9b9b | Artyom Tarasenko | empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); |
830 | 676d9b9b | Artyom Tarasenko | } |
831 | a350db85 | Blue Swirl | |
832 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
833 | f48f6569 | Blue Swirl | |
834 | d453c2c3 | Blue Swirl | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
835 | d453c2c3 | Blue Swirl | hwdef->intctl_base + 0x10000ULL,
|
836 | 462eda24 | Blue Swirl | cpu_irqs); |
837 | a1961a4b | Blue Swirl | |
838 | a1961a4b | Blue Swirl | for (i = 0; i < 32; i++) { |
839 | d453c2c3 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
840 | a1961a4b | Blue Swirl | } |
841 | a1961a4b | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
842 | d453c2c3 | Blue Swirl | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
843 | a1961a4b | Blue Swirl | } |
844 | b3a23197 | blueswir1 | |
845 | fe096129 | blueswir1 | if (hwdef->idreg_base) {
|
846 | 325f2747 | Blue Swirl | idreg_init(hwdef->idreg_base); |
847 | 4c2485de | blueswir1 | } |
848 | 4c2485de | blueswir1 | |
849 | c5de386a | Artyom Tarasenko | if (hwdef->afx_base) {
|
850 | c5de386a | Artyom Tarasenko | afx_init(hwdef->afx_base); |
851 | c5de386a | Artyom Tarasenko | } |
852 | c5de386a | Artyom Tarasenko | |
853 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
854 | c533e0b3 | Blue Swirl | slavio_irq[30]);
|
855 | ff403da6 | blueswir1 | |
856 | 3386376c | Artyom Tarasenko | if (hwdef->iommu_pad_base) {
|
857 | 3386376c | Artyom Tarasenko | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
|
858 | 3386376c | Artyom Tarasenko | Software shouldn't use aliased addresses, neither should it crash
|
859 | 3386376c | Artyom Tarasenko | when does. Using empty_slot instead of aliasing can help with
|
860 | 3386376c | Artyom Tarasenko | debugging such accesses */
|
861 | 3386376c | Artyom Tarasenko | empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); |
862 | 3386376c | Artyom Tarasenko | } |
863 | 3386376c | Artyom Tarasenko | |
864 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
865 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
866 | 2d069bab | blueswir1 | |
867 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
868 | 74ff8d90 | Blue Swirl | slavio_irq[16], iommu, &ledma_irq);
|
869 | ba3c64fb | bellard | |
870 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
871 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
872 | eee0b836 | blueswir1 | exit (1);
|
873 | eee0b836 | blueswir1 | } |
874 | 9a62fb24 | Bob Breuer | num_vsimms = 0;
|
875 | 9a62fb24 | Bob Breuer | if (num_vsimms == 0) { |
876 | 9a62fb24 | Bob Breuer | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
877 | 9a62fb24 | Bob Breuer | graphic_depth); |
878 | 9a62fb24 | Bob Breuer | } |
879 | 9a62fb24 | Bob Breuer | |
880 | 9a62fb24 | Bob Breuer | for (i = num_vsimms; i < MAX_VSIMMS; i++) {
|
881 | 9a62fb24 | Bob Breuer | /* vsimm registers probed by OBP */
|
882 | 9a62fb24 | Bob Breuer | if (hwdef->vsimm[i].reg_base) {
|
883 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
|
884 | 9a62fb24 | Bob Breuer | } |
885 | 9a62fb24 | Bob Breuer | } |
886 | 9a62fb24 | Bob Breuer | |
887 | 9a62fb24 | Bob Breuer | if (hwdef->sx_base) {
|
888 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->sx_base, 0x2000);
|
889 | 9a62fb24 | Bob Breuer | } |
890 | dbe06e18 | blueswir1 | |
891 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
892 | dbe06e18 | blueswir1 | |
893 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
894 | 81732d19 | blueswir1 | |
895 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
896 | 81732d19 | blueswir1 | |
897 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
898 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
899 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
900 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
901 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
902 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
903 | 741402f9 | blueswir1 | |
904 | 6d0c293d | blueswir1 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
905 | b2b6f6ec | Blue Swirl | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
906 | b2b6f6ec | Blue Swirl | slavio_irq[30], fdc_tc);
|
907 | b2b6f6ec | Blue Swirl | |
908 | 2582cfa0 | Blue Swirl | if (hwdef->apc_base) {
|
909 | 2582cfa0 | Blue Swirl | apc_init(hwdef->apc_base, cpu_halt[0]);
|
910 | 2582cfa0 | Blue Swirl | } |
911 | 2be17ebd | blueswir1 | |
912 | fe096129 | blueswir1 | if (hwdef->fd_base) {
|
913 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
914 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
915 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
916 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
917 | 2582cfa0 | Blue Swirl | &fdc_tc); |
918 | e4bcb14c | ths | } |
919 | e4bcb14c | ths | |
920 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
921 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
922 | e4bcb14c | ths | exit(1);
|
923 | e4bcb14c | ths | } |
924 | e4bcb14c | ths | |
925 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
926 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
927 | 73d74342 | Blue Swirl | espdma, espdma_irq, &esp_reset, &dma_enable); |
928 | 74ff8d90 | Blue Swirl | |
929 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 0, esp_reset);
|
930 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 1, dma_enable);
|
931 | f1587550 | ths | |
932 | fa28ec52 | Blue Swirl | if (hwdef->cs_base) {
|
933 | fa28ec52 | Blue Swirl | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
934 | c533e0b3 | Blue Swirl | slavio_irq[5]);
|
935 | fa28ec52 | Blue Swirl | } |
936 | b3ceef24 | blueswir1 | |
937 | 9a62fb24 | Bob Breuer | if (hwdef->dbri_base) {
|
938 | 9a62fb24 | Bob Breuer | /* ISDN chip with attached CS4215 audio codec */
|
939 | 9a62fb24 | Bob Breuer | /* prom space */
|
940 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->dbri_base+0x1000, 0x30); |
941 | 9a62fb24 | Bob Breuer | /* reg space */
|
942 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->dbri_base+0x10000, 0x100); |
943 | 9a62fb24 | Bob Breuer | } |
944 | 9a62fb24 | Bob Breuer | |
945 | 9a62fb24 | Bob Breuer | if (hwdef->bpp_base) {
|
946 | 9a62fb24 | Bob Breuer | /* parallel port */
|
947 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->bpp_base, 0x20);
|
948 | 9a62fb24 | Bob Breuer | } |
949 | 9a62fb24 | Bob Breuer | |
950 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
951 | 293f78bc | blueswir1 | RAM_size); |
952 | 36cd9210 | blueswir1 | |
953 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
954 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
955 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
956 | 905fdcb5 | blueswir1 | "Sun4m");
|
957 | 7eb0c8e8 | blueswir1 | |
958 | fe096129 | blueswir1 | if (hwdef->ecc_base)
|
959 | c533e0b3 | Blue Swirl | ecc_init(hwdef->ecc_base, slavio_irq[28],
|
960 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
961 | 3cce6243 | blueswir1 | |
962 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
963 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
964 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
965 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
966 | fbfcf955 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
967 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
968 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
969 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
970 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
971 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
972 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
973 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
974 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
975 | 748a4ee3 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
976 | 748a4ee3 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
977 | 513f789f | blueswir1 | } else {
|
978 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
979 | 748a4ee3 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
980 | 513f789f | blueswir1 | } |
981 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
982 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
983 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
984 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
985 | 36cd9210 | blueswir1 | } |
986 | 36cd9210 | blueswir1 | |
987 | 905fdcb5 | blueswir1 | enum {
|
988 | 905fdcb5 | blueswir1 | ss2_id = 0,
|
989 | 905fdcb5 | blueswir1 | ss5_id = 32,
|
990 | 905fdcb5 | blueswir1 | vger_id, |
991 | 905fdcb5 | blueswir1 | lx_id, |
992 | 905fdcb5 | blueswir1 | ss4_id, |
993 | 905fdcb5 | blueswir1 | scls_id, |
994 | 905fdcb5 | blueswir1 | sbook_id, |
995 | 905fdcb5 | blueswir1 | ss10_id = 64,
|
996 | 905fdcb5 | blueswir1 | ss20_id, |
997 | 905fdcb5 | blueswir1 | ss600mp_id, |
998 | 905fdcb5 | blueswir1 | ss1000_id = 96,
|
999 | 905fdcb5 | blueswir1 | ss2000_id, |
1000 | 905fdcb5 | blueswir1 | }; |
1001 | 905fdcb5 | blueswir1 | |
1002 | 8137cde8 | blueswir1 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
1003 | 36cd9210 | blueswir1 | /* SS-5 */
|
1004 | 36cd9210 | blueswir1 | { |
1005 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
1006 | 3386376c | Artyom Tarasenko | .iommu_pad_base = 0x10004000,
|
1007 | 3386376c | Artyom Tarasenko | .iommu_pad_len = 0x0fffb000,
|
1008 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
1009 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
1010 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
1011 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
1012 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
1013 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
1014 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
1015 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
1016 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
1017 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
1018 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
1019 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
1020 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
1021 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
1022 | c5de386a | Artyom Tarasenko | .afx_base = 0x6e000000,
|
1023 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
1024 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
1025 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1026 | 905fdcb5 | blueswir1 | .machine_id = ss5_id, |
1027 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
1028 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
1029 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1030 | e0353fe2 | blueswir1 | }, |
1031 | e0353fe2 | blueswir1 | /* SS-10 */
|
1032 | e0353fe2 | blueswir1 | { |
1033 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1034 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1035 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1036 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1037 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
1038 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1039 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
1040 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
1041 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1042 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
1043 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
1044 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
1045 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
1046 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1047 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1048 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
1049 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1050 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
1051 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
1052 | 905fdcb5 | blueswir1 | .machine_id = ss10_id, |
1053 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
1054 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1055 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1056 | 36cd9210 | blueswir1 | }, |
1057 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
1058 | 6a3b9cc9 | blueswir1 | { |
1059 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1060 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1061 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1062 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1063 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
1064 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1065 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
1066 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1067 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
1068 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
1069 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
1070 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1071 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1072 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
1073 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1074 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
1075 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x71,
|
1076 | 905fdcb5 | blueswir1 | .machine_id = ss600mp_id, |
1077 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
1078 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1079 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1080 | 6a3b9cc9 | blueswir1 | }, |
1081 | ae40972f | blueswir1 | /* SS-20 */
|
1082 | ae40972f | blueswir1 | { |
1083 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1084 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1085 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1086 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1087 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
1088 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1089 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
1090 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
1091 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1092 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
1093 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
1094 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
1095 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
1096 | 9a62fb24 | Bob Breuer | .bpp_base = 0xef4800000ULL,
|
1097 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1098 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1099 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
1100 | 9a62fb24 | Bob Breuer | .dbri_base = 0xee0000000ULL,
|
1101 | 9a62fb24 | Bob Breuer | .sx_base = 0xf80000000ULL,
|
1102 | 9a62fb24 | Bob Breuer | .vsimm = { |
1103 | 9a62fb24 | Bob Breuer | { |
1104 | 9a62fb24 | Bob Breuer | .reg_base = 0x9c000000ULL,
|
1105 | 9a62fb24 | Bob Breuer | .vram_base = 0xfc000000ULL
|
1106 | 9a62fb24 | Bob Breuer | }, { |
1107 | 9a62fb24 | Bob Breuer | .reg_base = 0x90000000ULL,
|
1108 | 9a62fb24 | Bob Breuer | .vram_base = 0xf0000000ULL
|
1109 | 9a62fb24 | Bob Breuer | }, { |
1110 | 9a62fb24 | Bob Breuer | .reg_base = 0x94000000ULL
|
1111 | 9a62fb24 | Bob Breuer | }, { |
1112 | 9a62fb24 | Bob Breuer | .reg_base = 0x98000000ULL
|
1113 | 9a62fb24 | Bob Breuer | } |
1114 | 9a62fb24 | Bob Breuer | }, |
1115 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1116 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
1117 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
1118 | 905fdcb5 | blueswir1 | .machine_id = ss20_id, |
1119 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
1120 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1121 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1122 | ae40972f | blueswir1 | }, |
1123 | a526a31c | blueswir1 | /* Voyager */
|
1124 | a526a31c | blueswir1 | { |
1125 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1126 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1127 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1128 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1129 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1130 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1131 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1132 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1133 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1134 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1135 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1136 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1137 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1138 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
1139 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1140 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1141 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1142 | 905fdcb5 | blueswir1 | .machine_id = vger_id, |
1143 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1144 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1145 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1146 | a526a31c | blueswir1 | }, |
1147 | a526a31c | blueswir1 | /* LX */
|
1148 | a526a31c | blueswir1 | { |
1149 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1150 | 3386376c | Artyom Tarasenko | .iommu_pad_base = 0x10004000,
|
1151 | 3386376c | Artyom Tarasenko | .iommu_pad_len = 0x0fffb000,
|
1152 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1153 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1154 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1155 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1156 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1157 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1158 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1159 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1160 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1161 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1162 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1163 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1164 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1165 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1166 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1167 | 905fdcb5 | blueswir1 | .machine_id = lx_id, |
1168 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
1169 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1170 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1171 | a526a31c | blueswir1 | }, |
1172 | a526a31c | blueswir1 | /* SS-4 */
|
1173 | a526a31c | blueswir1 | { |
1174 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1175 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1176 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
1177 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1178 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1179 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1180 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1181 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1182 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1183 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1184 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1185 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1186 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1187 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1188 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1189 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1190 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1191 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1192 | 905fdcb5 | blueswir1 | .machine_id = ss4_id, |
1193 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1194 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1195 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1196 | a526a31c | blueswir1 | }, |
1197 | a526a31c | blueswir1 | /* SPARCClassic */
|
1198 | a526a31c | blueswir1 | { |
1199 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1200 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1201 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1202 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1203 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1204 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1205 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1206 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1207 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1208 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1209 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1210 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1211 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1212 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1213 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1214 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1215 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1216 | 905fdcb5 | blueswir1 | .machine_id = scls_id, |
1217 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1218 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1219 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1220 | a526a31c | blueswir1 | }, |
1221 | a526a31c | blueswir1 | /* SPARCbook */
|
1222 | a526a31c | blueswir1 | { |
1223 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1224 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1225 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1226 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1227 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1228 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1229 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1230 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1231 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1232 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1233 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1234 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1235 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1236 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1237 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1238 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1239 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1240 | 905fdcb5 | blueswir1 | .machine_id = sbook_id, |
1241 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1242 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1243 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1244 | a526a31c | blueswir1 | }, |
1245 | 36cd9210 | blueswir1 | }; |
1246 | 36cd9210 | blueswir1 | |
1247 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1248 | c227f099 | Anthony Liguori | static void ss5_init(ram_addr_t RAM_size, |
1249 | 3023f332 | aliguori | const char *boot_device, |
1250 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1251 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1252 | 36cd9210 | blueswir1 | { |
1253 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1254 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1255 | 420557e8 | bellard | } |
1256 | c0e564d5 | bellard | |
1257 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1258 | c227f099 | Anthony Liguori | static void ss10_init(ram_addr_t RAM_size, |
1259 | 3023f332 | aliguori | const char *boot_device, |
1260 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1261 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1262 | e0353fe2 | blueswir1 | { |
1263 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1264 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1265 | e0353fe2 | blueswir1 | } |
1266 | e0353fe2 | blueswir1 | |
1267 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1268 | c227f099 | Anthony Liguori | static void ss600mp_init(ram_addr_t RAM_size, |
1269 | 3023f332 | aliguori | const char *boot_device, |
1270 | 77f193da | blueswir1 | const char *kernel_filename, |
1271 | 77f193da | blueswir1 | const char *kernel_cmdline, |
1272 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1273 | 6a3b9cc9 | blueswir1 | { |
1274 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1275 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1276 | 6a3b9cc9 | blueswir1 | } |
1277 | 6a3b9cc9 | blueswir1 | |
1278 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1279 | c227f099 | Anthony Liguori | static void ss20_init(ram_addr_t RAM_size, |
1280 | 3023f332 | aliguori | const char *boot_device, |
1281 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1282 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1283 | ae40972f | blueswir1 | { |
1284 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1285 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1286 | ee76f82e | blueswir1 | } |
1287 | ee76f82e | blueswir1 | |
1288 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1289 | c227f099 | Anthony Liguori | static void vger_init(ram_addr_t RAM_size, |
1290 | 3023f332 | aliguori | const char *boot_device, |
1291 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1292 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1293 | a526a31c | blueswir1 | { |
1294 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1295 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1296 | a526a31c | blueswir1 | } |
1297 | a526a31c | blueswir1 | |
1298 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1299 | c227f099 | Anthony Liguori | static void ss_lx_init(ram_addr_t RAM_size, |
1300 | 3023f332 | aliguori | const char *boot_device, |
1301 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1302 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1303 | a526a31c | blueswir1 | { |
1304 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1305 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1306 | a526a31c | blueswir1 | } |
1307 | a526a31c | blueswir1 | |
1308 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1309 | c227f099 | Anthony Liguori | static void ss4_init(ram_addr_t RAM_size, |
1310 | 3023f332 | aliguori | const char *boot_device, |
1311 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1312 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1313 | a526a31c | blueswir1 | { |
1314 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1315 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1316 | a526a31c | blueswir1 | } |
1317 | a526a31c | blueswir1 | |
1318 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1319 | c227f099 | Anthony Liguori | static void scls_init(ram_addr_t RAM_size, |
1320 | 3023f332 | aliguori | const char *boot_device, |
1321 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1322 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1323 | a526a31c | blueswir1 | { |
1324 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1325 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1326 | a526a31c | blueswir1 | } |
1327 | a526a31c | blueswir1 | |
1328 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1329 | c227f099 | Anthony Liguori | static void sbook_init(ram_addr_t RAM_size, |
1330 | 3023f332 | aliguori | const char *boot_device, |
1331 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1332 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1333 | a526a31c | blueswir1 | { |
1334 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1335 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1336 | a526a31c | blueswir1 | } |
1337 | a526a31c | blueswir1 | |
1338 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss5_machine = {
|
1339 | 66de733b | blueswir1 | .name = "SS-5",
|
1340 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 5",
|
1341 | 66de733b | blueswir1 | .init = ss5_init, |
1342 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1343 | 0c257437 | Anthony Liguori | .is_default = 1,
|
1344 | c0e564d5 | bellard | }; |
1345 | e0353fe2 | blueswir1 | |
1346 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss10_machine = {
|
1347 | 66de733b | blueswir1 | .name = "SS-10",
|
1348 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 10",
|
1349 | 66de733b | blueswir1 | .init = ss10_init, |
1350 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1351 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1352 | e0353fe2 | blueswir1 | }; |
1353 | 6a3b9cc9 | blueswir1 | |
1354 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss600mp_machine = {
|
1355 | 66de733b | blueswir1 | .name = "SS-600MP",
|
1356 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCserver 600MP",
|
1357 | 66de733b | blueswir1 | .init = ss600mp_init, |
1358 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1359 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1360 | 6a3b9cc9 | blueswir1 | }; |
1361 | ae40972f | blueswir1 | |
1362 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss20_machine = {
|
1363 | 66de733b | blueswir1 | .name = "SS-20",
|
1364 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 20",
|
1365 | 66de733b | blueswir1 | .init = ss20_init, |
1366 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1367 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1368 | ae40972f | blueswir1 | }; |
1369 | ae40972f | blueswir1 | |
1370 | f80f9ec9 | Anthony Liguori | static QEMUMachine voyager_machine = {
|
1371 | 66de733b | blueswir1 | .name = "Voyager",
|
1372 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation Voyager",
|
1373 | 66de733b | blueswir1 | .init = vger_init, |
1374 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1375 | a526a31c | blueswir1 | }; |
1376 | a526a31c | blueswir1 | |
1377 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss_lx_machine = {
|
1378 | 66de733b | blueswir1 | .name = "LX",
|
1379 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation LX",
|
1380 | 66de733b | blueswir1 | .init = ss_lx_init, |
1381 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1382 | a526a31c | blueswir1 | }; |
1383 | a526a31c | blueswir1 | |
1384 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss4_machine = {
|
1385 | 66de733b | blueswir1 | .name = "SS-4",
|
1386 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 4",
|
1387 | 66de733b | blueswir1 | .init = ss4_init, |
1388 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1389 | a526a31c | blueswir1 | }; |
1390 | a526a31c | blueswir1 | |
1391 | f80f9ec9 | Anthony Liguori | static QEMUMachine scls_machine = {
|
1392 | 66de733b | blueswir1 | .name = "SPARCClassic",
|
1393 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCClassic",
|
1394 | 66de733b | blueswir1 | .init = scls_init, |
1395 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1396 | a526a31c | blueswir1 | }; |
1397 | a526a31c | blueswir1 | |
1398 | f80f9ec9 | Anthony Liguori | static QEMUMachine sbook_machine = {
|
1399 | 66de733b | blueswir1 | .name = "SPARCbook",
|
1400 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCbook",
|
1401 | 66de733b | blueswir1 | .init = sbook_init, |
1402 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1403 | a526a31c | blueswir1 | }; |
1404 | a526a31c | blueswir1 | |
1405 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1406 | 7d85892b | blueswir1 | /* SS-1000 */
|
1407 | 7d85892b | blueswir1 | { |
1408 | 7d85892b | blueswir1 | .iounit_bases = { |
1409 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1410 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1411 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1412 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1413 | 7d85892b | blueswir1 | -1,
|
1414 | 7d85892b | blueswir1 | }, |
1415 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1416 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1417 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1418 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1419 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1420 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1421 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1422 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1423 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1424 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1425 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1426 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1427 | 905fdcb5 | blueswir1 | .machine_id = ss1000_id, |
1428 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1429 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1430 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1431 | 7d85892b | blueswir1 | }, |
1432 | 7d85892b | blueswir1 | /* SS-2000 */
|
1433 | 7d85892b | blueswir1 | { |
1434 | 7d85892b | blueswir1 | .iounit_bases = { |
1435 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1436 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1437 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1438 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1439 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1440 | 7d85892b | blueswir1 | }, |
1441 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1442 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1443 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1444 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1445 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1446 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1447 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1448 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1449 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1450 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1451 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1452 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1453 | 905fdcb5 | blueswir1 | .machine_id = ss2000_id, |
1454 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1455 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1456 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1457 | 7d85892b | blueswir1 | }, |
1458 | 7d85892b | blueswir1 | }; |
1459 | 7d85892b | blueswir1 | |
1460 | c227f099 | Anthony Liguori | static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
|
1461 | 4b48bf05 | Blue Swirl | { |
1462 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1463 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1464 | 4b48bf05 | Blue Swirl | unsigned int i; |
1465 | 4b48bf05 | Blue Swirl | |
1466 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sbi"); |
1467 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1468 | 4b48bf05 | Blue Swirl | |
1469 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1470 | 4b48bf05 | Blue Swirl | |
1471 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1472 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, *parent_irq[i]); |
1473 | 4b48bf05 | Blue Swirl | } |
1474 | 4b48bf05 | Blue Swirl | |
1475 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1476 | 4b48bf05 | Blue Swirl | |
1477 | 4b48bf05 | Blue Swirl | return dev;
|
1478 | 4b48bf05 | Blue Swirl | } |
1479 | 4b48bf05 | Blue Swirl | |
1480 | c227f099 | Anthony Liguori | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1481 | 7d85892b | blueswir1 | const char *boot_device, |
1482 | 3023f332 | aliguori | const char *kernel_filename, |
1483 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1484 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1485 | 7d85892b | blueswir1 | { |
1486 | 7d85892b | blueswir1 | unsigned int i; |
1487 | 7fc06735 | Blue Swirl | void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1488 | 7fc06735 | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1489 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
1490 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
1491 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1492 | 3cce6243 | blueswir1 | void *fw_cfg;
|
1493 | 7fc06735 | Blue Swirl | DeviceState *dev; |
1494 | 7d85892b | blueswir1 | |
1495 | 7d85892b | blueswir1 | /* init CPUs */
|
1496 | 7d85892b | blueswir1 | if (!cpu_model)
|
1497 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1498 | 7d85892b | blueswir1 | |
1499 | 666713c0 | Blue Swirl | for(i = 0; i < smp_cpus; i++) { |
1500 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1501 | 7d85892b | blueswir1 | } |
1502 | 7d85892b | blueswir1 | |
1503 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1504 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1505 | 7d85892b | blueswir1 | |
1506 | 7d85892b | blueswir1 | /* set up devices */
|
1507 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1508 | a350db85 | Blue Swirl | |
1509 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1510 | f48f6569 | Blue Swirl | |
1511 | 7fc06735 | Blue Swirl | dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1512 | 7fc06735 | Blue Swirl | |
1513 | 7fc06735 | Blue Swirl | for (i = 0; i < 32; i++) { |
1514 | 7fc06735 | Blue Swirl | sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1515 | 7fc06735 | Blue Swirl | } |
1516 | 7fc06735 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1517 | 7fc06735 | Blue Swirl | sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1518 | 7fc06735 | Blue Swirl | } |
1519 | 7d85892b | blueswir1 | |
1520 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1521 | c227f099 | Anthony Liguori | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1522 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1523 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1524 | c533e0b3 | Blue Swirl | sbi_irq[0]);
|
1525 | 7d85892b | blueswir1 | |
1526 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1527 | 74ff8d90 | Blue Swirl | iounits[0], &espdma_irq);
|
1528 | 7d85892b | blueswir1 | |
1529 | c533e0b3 | Blue Swirl | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1530 | 74ff8d90 | Blue Swirl | iounits[0], &ledma_irq);
|
1531 | 7d85892b | blueswir1 | |
1532 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1533 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1534 | 7d85892b | blueswir1 | exit (1);
|
1535 | 7d85892b | blueswir1 | } |
1536 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1537 | dc828ca1 | pbrook | graphic_depth); |
1538 | 7d85892b | blueswir1 | |
1539 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1540 | 7d85892b | blueswir1 | |
1541 | d95d8f1c | Blue Swirl | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1542 | 7d85892b | blueswir1 | |
1543 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1544 | 7d85892b | blueswir1 | |
1545 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1546 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1547 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1548 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1549 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1550 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1551 | 7d85892b | blueswir1 | |
1552 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1553 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1554 | 7d85892b | blueswir1 | exit(1);
|
1555 | 7d85892b | blueswir1 | } |
1556 | 7d85892b | blueswir1 | |
1557 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1558 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1559 | 73d74342 | Blue Swirl | espdma, espdma_irq, &esp_reset, &dma_enable); |
1560 | 73d74342 | Blue Swirl | |
1561 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 0, esp_reset);
|
1562 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 1, dma_enable);
|
1563 | 7d85892b | blueswir1 | |
1564 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1565 | 293f78bc | blueswir1 | RAM_size); |
1566 | 7d85892b | blueswir1 | |
1567 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1568 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1569 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1570 | 905fdcb5 | blueswir1 | "Sun4d");
|
1571 | 3cce6243 | blueswir1 | |
1572 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1573 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1574 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1575 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1576 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1577 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1578 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1579 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1580 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1581 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1582 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
1583 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
1584 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
1585 | 513f789f | blueswir1 | } else {
|
1586 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1587 | 513f789f | blueswir1 | } |
1588 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1589 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1590 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1591 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1592 | 7d85892b | blueswir1 | } |
1593 | 7d85892b | blueswir1 | |
1594 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1595 | c227f099 | Anthony Liguori | static void ss1000_init(ram_addr_t RAM_size, |
1596 | 3023f332 | aliguori | const char *boot_device, |
1597 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1598 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1599 | 7d85892b | blueswir1 | { |
1600 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1601 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1602 | 7d85892b | blueswir1 | } |
1603 | 7d85892b | blueswir1 | |
1604 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1605 | c227f099 | Anthony Liguori | static void ss2000_init(ram_addr_t RAM_size, |
1606 | 3023f332 | aliguori | const char *boot_device, |
1607 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1608 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1609 | 7d85892b | blueswir1 | { |
1610 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1611 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1612 | 7d85892b | blueswir1 | } |
1613 | 7d85892b | blueswir1 | |
1614 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss1000_machine = {
|
1615 | 66de733b | blueswir1 | .name = "SS-1000",
|
1616 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCserver 1000",
|
1617 | 66de733b | blueswir1 | .init = ss1000_init, |
1618 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1619 | 1bcee014 | blueswir1 | .max_cpus = 8,
|
1620 | 7d85892b | blueswir1 | }; |
1621 | 7d85892b | blueswir1 | |
1622 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2000_machine = {
|
1623 | 66de733b | blueswir1 | .name = "SS-2000",
|
1624 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCcenter 2000",
|
1625 | 66de733b | blueswir1 | .init = ss2000_init, |
1626 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1627 | 1bcee014 | blueswir1 | .max_cpus = 20,
|
1628 | 7d85892b | blueswir1 | }; |
1629 | 8137cde8 | blueswir1 | |
1630 | 8137cde8 | blueswir1 | static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1631 | 8137cde8 | blueswir1 | /* SS-2 */
|
1632 | 8137cde8 | blueswir1 | { |
1633 | 8137cde8 | blueswir1 | .iommu_base = 0xf8000000,
|
1634 | 8137cde8 | blueswir1 | .tcx_base = 0xfe000000,
|
1635 | 8137cde8 | blueswir1 | .slavio_base = 0xf6000000,
|
1636 | 8137cde8 | blueswir1 | .intctl_base = 0xf5000000,
|
1637 | 8137cde8 | blueswir1 | .counter_base = 0xf3000000,
|
1638 | 8137cde8 | blueswir1 | .ms_kb_base = 0xf0000000,
|
1639 | 8137cde8 | blueswir1 | .serial_base = 0xf1000000,
|
1640 | 8137cde8 | blueswir1 | .nvram_base = 0xf2000000,
|
1641 | 8137cde8 | blueswir1 | .fd_base = 0xf7200000,
|
1642 | 8137cde8 | blueswir1 | .dma_base = 0xf8400000,
|
1643 | 8137cde8 | blueswir1 | .esp_base = 0xf8800000,
|
1644 | 8137cde8 | blueswir1 | .le_base = 0xf8c00000,
|
1645 | 8137cde8 | blueswir1 | .aux1_base = 0xf7400003,
|
1646 | 8137cde8 | blueswir1 | .nvram_machine_id = 0x55,
|
1647 | 8137cde8 | blueswir1 | .machine_id = ss2_id, |
1648 | 8137cde8 | blueswir1 | .max_mem = 0x10000000,
|
1649 | 8137cde8 | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
1650 | 8137cde8 | blueswir1 | }, |
1651 | 8137cde8 | blueswir1 | }; |
1652 | 8137cde8 | blueswir1 | |
1653 | c227f099 | Anthony Liguori | static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
|
1654 | 4b48bf05 | Blue Swirl | qemu_irq *parent_irq) |
1655 | 4b48bf05 | Blue Swirl | { |
1656 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1657 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1658 | 4b48bf05 | Blue Swirl | unsigned int i; |
1659 | 4b48bf05 | Blue Swirl | |
1660 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sun4c_intctl"); |
1661 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1662 | 4b48bf05 | Blue Swirl | |
1663 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1664 | 4b48bf05 | Blue Swirl | |
1665 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_PILS; i++) { |
1666 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, parent_irq[i]); |
1667 | 4b48bf05 | Blue Swirl | } |
1668 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1669 | 4b48bf05 | Blue Swirl | |
1670 | 4b48bf05 | Blue Swirl | return dev;
|
1671 | 4b48bf05 | Blue Swirl | } |
1672 | 4b48bf05 | Blue Swirl | |
1673 | c227f099 | Anthony Liguori | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1674 | 8137cde8 | blueswir1 | const char *boot_device, |
1675 | 3023f332 | aliguori | const char *kernel_filename, |
1676 | 8137cde8 | blueswir1 | const char *kernel_cmdline, |
1677 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1678 | 8137cde8 | blueswir1 | { |
1679 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
1680 | e32cba29 | Blue Swirl | qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1681 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
1682 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
1683 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1684 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
1685 | 8137cde8 | blueswir1 | void *fw_cfg;
|
1686 | e32cba29 | Blue Swirl | DeviceState *dev; |
1687 | e32cba29 | Blue Swirl | unsigned int i; |
1688 | 8137cde8 | blueswir1 | |
1689 | 8137cde8 | blueswir1 | /* init CPU */
|
1690 | 8137cde8 | blueswir1 | if (!cpu_model)
|
1691 | 8137cde8 | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1692 | 8137cde8 | blueswir1 | |
1693 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1694 | 8137cde8 | blueswir1 | |
1695 | 8137cde8 | blueswir1 | /* set up devices */
|
1696 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1697 | a350db85 | Blue Swirl | |
1698 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1699 | f48f6569 | Blue Swirl | |
1700 | e32cba29 | Blue Swirl | dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1701 | e32cba29 | Blue Swirl | |
1702 | e32cba29 | Blue Swirl | for (i = 0; i < 8; i++) { |
1703 | e32cba29 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1704 | e32cba29 | Blue Swirl | } |
1705 | 8137cde8 | blueswir1 | |
1706 | 8137cde8 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1707 | c533e0b3 | Blue Swirl | slavio_irq[1]);
|
1708 | 8137cde8 | blueswir1 | |
1709 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1710 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
1711 | 8137cde8 | blueswir1 | |
1712 | 8137cde8 | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1713 | 74ff8d90 | Blue Swirl | slavio_irq[3], iommu, &ledma_irq);
|
1714 | 8137cde8 | blueswir1 | |
1715 | 8137cde8 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1716 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1717 | 8137cde8 | blueswir1 | exit (1);
|
1718 | 8137cde8 | blueswir1 | } |
1719 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1720 | dc828ca1 | pbrook | graphic_depth); |
1721 | 8137cde8 | blueswir1 | |
1722 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1723 | 8137cde8 | blueswir1 | |
1724 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1725 | 8137cde8 | blueswir1 | |
1726 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1727 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1728 | 8137cde8 | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1729 | 8137cde8 | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1730 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[1],
|
1731 | c533e0b3 | Blue Swirl | slavio_irq[1], serial_hds[0], serial_hds[1], |
1732 | aeeb69c7 | aurel32 | ESCC_CLOCK, 1);
|
1733 | 8137cde8 | blueswir1 | |
1734 | b2b6f6ec | Blue Swirl | slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1735 | 8137cde8 | blueswir1 | |
1736 | c227f099 | Anthony Liguori | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1737 | 8137cde8 | blueswir1 | /* there is zero or one floppy drive */
|
1738 | ce802585 | blueswir1 | memset(fd, 0, sizeof(fd)); |
1739 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
1740 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1741 | 2582cfa0 | Blue Swirl | &fdc_tc); |
1742 | 8137cde8 | blueswir1 | } |
1743 | 8137cde8 | blueswir1 | |
1744 | 8137cde8 | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1745 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1746 | 8137cde8 | blueswir1 | exit(1);
|
1747 | 8137cde8 | blueswir1 | } |
1748 | 8137cde8 | blueswir1 | |
1749 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1750 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1751 | 73d74342 | Blue Swirl | espdma, espdma_irq, &esp_reset, &dma_enable); |
1752 | 73d74342 | Blue Swirl | |
1753 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 0, esp_reset);
|
1754 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 1, dma_enable);
|
1755 | 8137cde8 | blueswir1 | |
1756 | 8137cde8 | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1757 | 8137cde8 | blueswir1 | RAM_size); |
1758 | 8137cde8 | blueswir1 | |
1759 | 8137cde8 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1760 | 8137cde8 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1761 | 8137cde8 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1762 | 8137cde8 | blueswir1 | "Sun4c");
|
1763 | 8137cde8 | blueswir1 | |
1764 | 8137cde8 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1765 | 8137cde8 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1766 | 8137cde8 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1767 | 8137cde8 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1768 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1769 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1770 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1771 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1772 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1773 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1774 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
1775 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
1776 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
1777 | 513f789f | blueswir1 | } else {
|
1778 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1779 | 513f789f | blueswir1 | } |
1780 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1781 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1782 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1783 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1784 | 8137cde8 | blueswir1 | } |
1785 | 8137cde8 | blueswir1 | |
1786 | 8137cde8 | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1787 | c227f099 | Anthony Liguori | static void ss2_init(ram_addr_t RAM_size, |
1788 | 3023f332 | aliguori | const char *boot_device, |
1789 | 8137cde8 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1790 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1791 | 8137cde8 | blueswir1 | { |
1792 | 3023f332 | aliguori | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1793 | 8137cde8 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1794 | 8137cde8 | blueswir1 | } |
1795 | 8137cde8 | blueswir1 | |
1796 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2_machine = {
|
1797 | 8137cde8 | blueswir1 | .name = "SS-2",
|
1798 | 8137cde8 | blueswir1 | .desc = "Sun4c platform, SPARCstation 2",
|
1799 | 8137cde8 | blueswir1 | .init = ss2_init, |
1800 | 8137cde8 | blueswir1 | .use_scsi = 1,
|
1801 | 8137cde8 | blueswir1 | }; |
1802 | f80f9ec9 | Anthony Liguori | |
1803 | f80f9ec9 | Anthony Liguori | static void ss2_machine_init(void) |
1804 | f80f9ec9 | Anthony Liguori | { |
1805 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss5_machine); |
1806 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss10_machine); |
1807 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss600mp_machine); |
1808 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss20_machine); |
1809 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&voyager_machine); |
1810 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss_lx_machine); |
1811 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss4_machine); |
1812 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&scls_machine); |
1813 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sbook_machine); |
1814 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss1000_machine); |
1815 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2000_machine); |
1816 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2_machine); |
1817 | f80f9ec9 | Anthony Liguori | } |
1818 | f80f9ec9 | Anthony Liguori | |
1819 | f80f9ec9 | Anthony Liguori | machine_init(ss2_machine_init); |