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/*
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 * QEMU model of the Xilinx timer block.
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 *
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 * Copyright (c) 2009 Edgar E. Iglesias.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "sysbus.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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#define D(x)
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#define R_TCSR     0
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#define R_TLR      1
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#define R_TCR      2
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#define R_MAX      4
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#define TCSR_MDT        (1<<0)
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#define TCSR_UDT        (1<<1)
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#define TCSR_GENT       (1<<2)
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#define TCSR_CAPT       (1<<3)
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#define TCSR_ARHT       (1<<4)
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#define TCSR_LOAD       (1<<5)
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#define TCSR_ENIT       (1<<6)
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#define TCSR_ENT        (1<<7)
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#define TCSR_TINT       (1<<8)
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#define TCSR_PWMA       (1<<9)
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#define TCSR_ENALL      (1<<10)
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struct xlx_timer
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{
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    QEMUBH *bh;
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    ptimer_state *ptimer;
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    void *parent;
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    int nr; /* for debug.  */
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    unsigned long timer_div;
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    uint32_t regs[R_MAX];
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};
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struct timerblock
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{
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    SysBusDevice busdev;
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    qemu_irq irq;
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    uint32_t nr_timers;
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    uint32_t freq_hz;
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    struct xlx_timer *timers;
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};
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static inline unsigned int timer_from_addr(target_phys_addr_t addr)
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{
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    /* Timers get a 4x32bit control reg area each.  */
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    return addr >> 2;
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}
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static void timer_update_irq(struct timerblock *t)
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{
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    unsigned int i, irq = 0;
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    uint32_t csr;
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    for (i = 0; i < t->nr_timers; i++) {
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        csr = t->timers[i].regs[R_TCSR];
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        irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
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    }
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    /* All timers within the same slave share a single IRQ line.  */
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    qemu_set_irq(t->irq, !!irq);
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}
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static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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{
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    struct timerblock *t = opaque;
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    struct xlx_timer *xt;
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    uint32_t r = 0;
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    unsigned int timer;
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    addr >>= 2;
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    timer = timer_from_addr(addr);
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    xt = &t->timers[timer];
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    /* Further decoding to address a specific timers reg.  */
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    addr &= 0x3;
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    switch (addr)
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    {
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        case R_TCR:
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                r = ptimer_get_count(xt->ptimer);
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                if (!(xt->regs[R_TCSR] & TCSR_UDT))
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                    r = ~r;
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                D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
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                         timer, r, xt->regs[R_TCSR] & TCSR_UDT));
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            break;
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        default:
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            if (addr < ARRAY_SIZE(xt->regs))
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                r = xt->regs[addr];
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            break;
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    }
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    D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
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    return r;
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}
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static void timer_enable(struct xlx_timer *xt)
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{
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    uint64_t count;
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    D(printf("%s timer=%d down=%d\n", __func__,
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              xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
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    ptimer_stop(xt->ptimer);
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    if (xt->regs[R_TCSR] & TCSR_UDT)
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        count = xt->regs[R_TLR];
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    else
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        count = ~0 - xt->regs[R_TLR];
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    ptimer_set_count(xt->ptimer, count);
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    ptimer_run(xt->ptimer, 1);
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}
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static void
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    struct timerblock *t = opaque;
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    struct xlx_timer *xt;
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    unsigned int timer;
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    addr >>= 2;
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    timer = timer_from_addr(addr);
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    xt = &t->timers[timer];
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    D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
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             __func__, addr * 4, value, timer, addr & 3));
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    /* Further decoding to address a specific timers reg.  */
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    addr &= 3;
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    switch (addr) 
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    {
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        case R_TCSR:
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            if (value & TCSR_TINT)
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                value &= ~TCSR_TINT;
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            xt->regs[addr] = value;
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            if (value & TCSR_ENT)
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                timer_enable(xt);
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            break;
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        default:
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            if (addr < ARRAY_SIZE(xt->regs))
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                xt->regs[addr] = value;
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            break;
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    }
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    timer_update_irq(t);
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}
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static CPUReadMemoryFunc * const timer_read[] = {
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    NULL, NULL,
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    &timer_readl,
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};
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static CPUWriteMemoryFunc * const timer_write[] = {
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    NULL, NULL,
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    &timer_writel,
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};
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static void timer_hit(void *opaque)
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{
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    struct xlx_timer *xt = opaque;
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    struct timerblock *t = xt->parent;
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    D(printf("%s %d\n", __func__, timer));
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    xt->regs[R_TCSR] |= TCSR_TINT;
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    if (xt->regs[R_TCSR] & TCSR_ARHT)
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        timer_enable(xt);
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    timer_update_irq(t);
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}
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static int xilinx_timer_init(SysBusDevice *dev)
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{
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    struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
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    unsigned int i;
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    int timer_regs;
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    /* All timers share a single irq line.  */
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    sysbus_init_irq(dev, &t->irq);
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    /* Init all the ptimers.  */
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    t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers);
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    for (i = 0; i < t->nr_timers; i++) {
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        struct xlx_timer *xt = &t->timers[i];
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        xt->parent = t;
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        xt->nr = i;
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        xt->bh = qemu_bh_new(timer_hit, xt);
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        xt->ptimer = ptimer_init(xt->bh);
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        ptimer_set_freq(xt->ptimer, t->freq_hz);
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    }
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    timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
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    sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
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    return 0;
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}
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static SysBusDeviceInfo xilinx_timer_info = {
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    .init = xilinx_timer_init,
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    .qdev.name  = "xilinx,timer",
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    .qdev.size  = sizeof(struct timerblock),
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    .qdev.props = (Property[]) {
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        DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   0),
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        DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
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        DEFINE_PROP_END_OF_LIST(),
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    }
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};
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static void xilinx_timer_register(void)
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{
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    sysbus_register_withprop(&xilinx_timer_info);
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}
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device_init(xilinx_timer_register)