Revision 43dc2a64 hw/sh7750.c
| b/hw/sh7750.c | ||
|---|---|---|
| 206 | 206 |
switch (addr) {
|
| 207 | 207 |
default: |
| 208 | 208 |
error_access("byte read", addr);
|
| 209 |
assert(0);
|
|
| 209 |
abort();
|
|
| 210 | 210 |
} |
| 211 | 211 |
} |
| 212 | 212 |
|
| ... | ... | |
| 240 | 240 |
return 0; |
| 241 | 241 |
default: |
| 242 | 242 |
error_access("word read", addr);
|
| 243 |
assert(0);
|
|
| 243 |
abort();
|
|
| 244 | 244 |
} |
| 245 | 245 |
} |
| 246 | 246 |
|
| ... | ... | |
| 287 | 287 |
return s->cpu->prr; |
| 288 | 288 |
default: |
| 289 | 289 |
error_access("long read", addr);
|
| 290 |
assert(0);
|
|
| 290 |
abort();
|
|
| 291 | 291 |
} |
| 292 | 292 |
} |
| 293 | 293 |
|
| ... | ... | |
| 303 | 303 |
} |
| 304 | 304 |
|
| 305 | 305 |
error_access("byte write", addr);
|
| 306 |
assert(0);
|
|
| 306 |
abort();
|
|
| 307 | 307 |
} |
| 308 | 308 |
|
| 309 | 309 |
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
| ... | ... | |
| 349 | 349 |
s->gpioic = mem_value; |
| 350 | 350 |
if (mem_value != 0) {
|
| 351 | 351 |
fprintf(stderr, "I/O interrupts not implemented\n"); |
| 352 |
assert(0);
|
|
| 352 |
abort();
|
|
| 353 | 353 |
} |
| 354 | 354 |
return; |
| 355 | 355 |
default: |
| 356 | 356 |
error_access("word write", addr);
|
| 357 |
assert(0);
|
|
| 357 |
abort();
|
|
| 358 | 358 |
} |
| 359 | 359 |
} |
| 360 | 360 |
|
| ... | ... | |
| 433 | 433 |
return; |
| 434 | 434 |
default: |
| 435 | 435 |
error_access("long write", addr);
|
| 436 |
assert(0);
|
|
| 436 |
abort();
|
|
| 437 | 437 |
} |
| 438 | 438 |
} |
| 439 | 439 |
|
| ... | ... | |
| 618 | 618 |
|
| 619 | 619 |
static uint32_t invalid_read(void *opaque, target_phys_addr_t addr) |
| 620 | 620 |
{
|
| 621 |
assert(0);
|
|
| 621 |
abort();
|
|
| 622 | 622 |
|
| 623 | 623 |
return 0; |
| 624 | 624 |
} |
| ... | ... | |
| 635 | 635 |
case MM_ITLB_ADDR: |
| 636 | 636 |
case MM_ITLB_DATA: |
| 637 | 637 |
/* XXXXX */ |
| 638 |
assert(0);
|
|
| 638 |
abort();
|
|
| 639 | 639 |
break; |
| 640 | 640 |
case MM_OCACHE_ADDR: |
| 641 | 641 |
case MM_OCACHE_DATA: |
| ... | ... | |
| 644 | 644 |
case MM_UTLB_ADDR: |
| 645 | 645 |
case MM_UTLB_DATA: |
| 646 | 646 |
/* XXXXX */ |
| 647 |
assert(0);
|
|
| 647 |
abort();
|
|
| 648 | 648 |
break; |
| 649 | 649 |
default: |
| 650 |
assert(0);
|
|
| 650 |
abort();
|
|
| 651 | 651 |
} |
| 652 | 652 |
|
| 653 | 653 |
return ret; |
| ... | ... | |
| 656 | 656 |
static void invalid_write(void *opaque, target_phys_addr_t addr, |
| 657 | 657 |
uint32_t mem_value) |
| 658 | 658 |
{
|
| 659 |
assert(0);
|
|
| 659 |
abort();
|
|
| 660 | 660 |
} |
| 661 | 661 |
|
| 662 | 662 |
static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, |
| ... | ... | |
| 672 | 672 |
case MM_ITLB_ADDR: |
| 673 | 673 |
case MM_ITLB_DATA: |
| 674 | 674 |
/* XXXXX */ |
| 675 |
assert(0);
|
|
| 675 |
abort();
|
|
| 676 | 676 |
break; |
| 677 | 677 |
case MM_OCACHE_ADDR: |
| 678 | 678 |
case MM_OCACHE_DATA: |
| ... | ... | |
| 683 | 683 |
break; |
| 684 | 684 |
case MM_UTLB_DATA: |
| 685 | 685 |
/* XXXXX */ |
| 686 |
assert(0);
|
|
| 686 |
abort();
|
|
| 687 | 687 |
break; |
| 688 | 688 |
default: |
| 689 |
assert(0);
|
|
| 689 |
abort();
|
|
| 690 | 690 |
break; |
| 691 | 691 |
} |
| 692 | 692 |
} |
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