target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTS
The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormalsas special cases, so we must set the InputDenormal exception flag ourselves.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fns
The functions which do the core estimation algorithms for the VRSQRTEand VRECPE instructions should not set floating point exception flags,so use a local fp status for doing these calculations....
target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNs
Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires thatwe implement the set of negations and additions specified by the ARM ARM;plausible looking simplifications like turning (-A + B) into (B - A) or...
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
Conflicts: cpu-all.h
target-arm: Privatize CPU_INTERRUPT_FIQ.
This interrupt name was only used by the ARM port.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix typos in comments (neccessary -> necessary)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Fix typos in comments and code (occured -> occurred and related)
The code changed here is an unused data type name (evt_flush_occurred).
target-arm: Don't update base register on abort in Thumb T1 LDM
Make sure the base register isn't updated if it is in the load listfor a Thumb LDM (T1 encoding) which aborts partway through the load.
target-arm: fix LDMIA bug on page boundarytarget-arm: fix LDMIA bug on page boundary
When consecutive memory locations are on page boundary, a base register may beloaded before page fault occurs. After page fault handling, it losts the memorylocation information. To solve this problem, loading a base register has to put back....
target-arm: Handle UNDEF cases for Neon VLD/VST multiple-structures
Correctly UNDEF for Neon VLD/VST "multiple structures" forms where thealign field is not valid.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Handle UNDEFs for Neon single element load/stores
Handle the UNDEF and UNPREDICTABLE cases for Neon "single element toone lane" VLD and "single element from one lane" VST.
target-arm: Set Invalid flag for NaN in float-to-int conversions
When we catch the special case of an input NaN in ARM float to inthelper functions, set the Invalid flag as well as returning thecorrect result.
Implement basic part of SA-1110/SA-1100
Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.Implemented: - IRQs - GPIO - PPC - RTC - UARTs (no IrDA/etc.) - OST reused from pxa25x
Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the...
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix some typos in comments and documentation
helpfull -> helpfulusefull -> usefulcotrol -> control
and a grammar fix.
target-arm: Don't overflow when calculating value for signed VABAL
In the VABAL instruction we take the absolute difference of twovalues of size x and store it in a result of size 2x. This meanswe have to be careful to calculate the absolute difference using...
target-arm: Handle UNDEF cases for Neon invalid modified-immediates
For Neon "one register and a modified immediate value" forms, thecombination op=1 cmode=1111 is unallocated and should UNDEF.All instructions of this form also UNDEF if Q 1 and Vd<0> 1....
target-arm: Handle UNDEF cases for Neon 3-regs-different-widths
Add missing UNDEF checks for instructions in the Neon "3 registers ofdifferent widths" data processing space.
target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms
Add missing checks for cases which must UNDEF in the Neon "2 registers anda scalar" data processing instruction space.
target-arm: Handle UNDEF cases for VEXT
VEXT must UNDEF if Q 1 && (Vd<0> 1 || Vr<0> 1 || Vm<0> 1)
target-arm: Simplify checking of size field in Neon 2reg-misc forms
Many of the Neon "2 register misc" instruction forms require invalidsize fields to cause the instruction to UNDEF. Pull this informationout into an array; this simplifies the code and also means we can do...
target-arm: Handle UNDEF cases for Neon 2 register misc forms
Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> 1 || Vm<0> 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q 1 || Vm<0> 1...
target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF
Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF itrather than allowing the helper function to index off the endof the register file.
target-arm: Handle UNDEF cases for VDUP (scalar)
Handle the UNDEF cases for VDUP: imm4 x000 Q 1 && Vd<0> == 1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Detect tininess before rounding for FP operations
The ARM architecture mandates that we detect tininess before rounding,so set the softfloat fp_status up appropriately.
target-arm: Collapse VSRI case into VSHL, VSLI
Collapse some switch cases for VSRI into those for VSHL, VSLI,since the bodies are the same. (This is not completely obviousfor the size < 3 case, but since for VSRI we know U=1 theGEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded...
target-arm: Use lookup table for size check on Neon 3-reg-same insns
Simplify the checks for invalid size values for the Neon "three registersof the same size" instruction forms (and add them where they were missing)by using a lookup table.
This includes adding symbolic constants for the op values in this space,...
target-arm: Handle UNDEF cases for Neon 3-regs-same insns
Correct the handling of UNDEF cases for the NEON "3 registers samesize" forms, by adding missing checks and rationalising some othersso they are done early enough to avoid leaking TCG temporaries....
target-arm: Simplify three-register pairwise code
Since we know that the case of (pairwise && q) has been caughtearlier, we can simplify the register setup code for each passin the three-register-same-size Neon loop.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>...
target-arm: Handle UNDEF cases for Neon "2 regs and shift" insns
Correctly handle all the UNDEF cases for Neon instructions of the"2 registers and shift" form, and make sure that we check for thesecases early enough not to leak TCG temporaries.
arm: basic support for ARMv4/ARMv4T emulation
Currently target-arm/ assumes at least ARMv5 core. Add support forhandling also ARMv4/ARMv4T. This changes the following instructions:
BX
BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-arm: Use global env in iwmmxt_helper.c helpers
Use the global 'env' variable in the helper functions in iwmmxt_helper.c.This means we don't need to pass env as an argument to them any more.
target-arm: Make Neon helper routines use correct FP status
Make the Neon helper routines use the correct FP status fromthe CPUEnv rather than using a dummy static one. This meansthey will correctly handle denormals and NaNs and will setFPSCR exception bits properly....
target-arm: Use global env in neon_helper.c helpers
Use the global 'env' variable in the helper functions in neon_helper.c.This means we don't need to pass env as an argument to them any more.
target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handling
Implementing the floating-point versions of VCLE #0 and VCLT #0 bydoing a GT comparison and inverting the result gives the wrongresult if the input is a NaN. Implement as a GT comparison with theoperands swapped instead....
target-arm: Correct ABD's handling of negative zeroes
Implement ABD by taking the absolute value of the differenceof the operands (as the ARM ARM specifies) rather than byflipping the order of the operands to the subtract basedon the results of a comparison. The latter approch gives...
target-arm: Use new softfloat min/max functions for VMAX, VMIN
Use the new softfloat min/max functions to implement the Neon VMAXand VMIN instructions. This allows us to get the right behaviourfor NaN and negative zero.
target-arm/helper.c: For float-int conversion helpers pass ints as ints
Correct the argument and return types for the float<->int conversion helperfunctions so that integer arguments and return values are declared asuint32_t/uint64_t, not float32/float64. This allows us to remove the...
target-arm: Return right result for Neon comparison with NaNs
Fix the helper functions implementing the Neon floating point comparisonops (VCGE, VCGT, VCEQ, VACGT, VACGE) to return the right answer whenone of the values being compared is a NaN.
target-arm/neon_helper.c: Use make_float32/float32_val macros
Use the softfloat make_float32 and float32_val macros to convert betweensoftfloat's float32 type and raw uint32_t types, rather than privateconversion functions.
target-arm: Fix VLD of single element to all lanes
Fix several bugs in VLD of single element to all lanes:
The "single element to all lanes" form of VLD1 differs from those forVLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded elementshould be written to one or two Dregs (rather than being a register...
target-arm: Don't leak TCG temp for UNDEFs in Neon load/store space
Move the allocation and freeing of the TCG temp used for the address forNeon load/store instructions so that we don't allocate the temporaryuntil we've done enough decoding to know that the instruction is not...
target-arm: use make_float32() to make constant floats for VRSQRTS
The preferred way to create a constant floating point value is to usemake_float32() rather than doing a runtime int32_to_float32().Convert the code in the VRSQRTS helper to work this way....
target-arm: Fix VRECPS edge cases handling
Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0
target-arm: Fix TCG temporary leaks for scalar VMULL
Fix a TCG temporary leak when translating 32-bit scalar VMULL.
target-arm: Set Q bit for overflow in SMUAD and SMLAD
SMUAD and SMLAD are supposed to set the Q bit if the addition ofthe two 16x16 multiply products and optional accumulator overflowsconsidered as a signed value. However we were only doing this checkfor the addition of the accumulator, not when adding the products,...
target-arm: Fix GE bits for v6media signed modulo arithmetic
Fix the signed modulo arithmetic helpers for the v6mediainstructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to setthe GE bits correctly (based on the result of the add or subtractbefore it is truncated to 16 bits, not after)....
target-arm: Fix UNDEF cases in Thumb load/store
Decode of Thumb load/store was merging together the cases of 'bit 11==0'(reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work forvalid instruction patterns but meant that we would not UNDEF for the...
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Implement a minimal set of cp14 debug registers
Newer ARM kernels try to probe for whether the CPU has hardware breakpointsupport. For this to work QEMU has to implement a minimal set of the cp14debug registers. The architecture requires v7 cores to implement debug...
target-arm: Use TCG temporary leak debugging facilities
Use the new TCG temporary leak debugging facilities tocheck that each ARM instruction does not leak temporaries.
target-arm: Remove ad-hoc leak checking code
This commit removes the ad-hoc resource leak checking code fromtarget-arm. This includes replacing all uses of new_tmp() withtcg_temp_new_i32() and all uses of dead_tmp() withtcg_temp_free_i32().
target-arm: Implement cp15 VA->PA translation
Implement VA->PA translations by cp15-c7 that went through unchangedpreviously.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Set carry flag correctly for Thumb2 ORNS
The code for Thumb2 ORNS (or negated and set flags) was trashinga TCG input register which was needed later for use in calculatingflags, with the effect that the carry flag was always set withthe wrong sense. Fix this by using the TCG orc op instead of...
target-arm: Handle VMOV between two core and VFP single regs
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry andVMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and apair of VFP single precision registers):
target-arm: Don't decode old cp15 WFI instructions on v7 cores
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-classinstruction, but in previous versions this functionality was providedvia a cp15 coprocessor register. Add correct feature checks to the...
target-arm: Introduce float64_256 and float64_512 constants.
These two constants will be used by helper functions such as recpe_f32and rsqrte_f32.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix support for VRECPE.
Now use the same algorithm as described in the ARM ARM.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix support for VRSQRTE.
target-arm: Fix shift by immediate and narrow where src, dest overlap
For Neon shifts by immediate and narrow, correctly handle the casewhere the source registers and the destination registers overlap(the second pass should use the original register contents, not the...
target-arm: Refactor to pull narrowing decode into separate function
Pull the code which decodes narrowing operations as being eithersigned/unsigned saturate or plain out into its own function.
target-arm: Fix rounding constant addition for Neon shifts
Handle cases where adding the rounding constant could overflow in Neonshift instructions: VRSHR, VRSRA, VQRSHRN, VQRSHRUN, VRSHRN.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>[peter.maydell@linaro.org: fix handling of large shifts in rshl_s32,...
target-arm: Fix signed VRSHL by large shift counts
Correctly handle VRSHL of signed values by a shift count of thewidth of the data type or larger, which must be special-cased in thershl_s* helper functions.
target-arm: Fix unsigned VRSHL.s8 and .s16 right shifts by type width
Fix handling of unsigned VRSHL.s8 and .s16 right shifts by the typewidth.
target-arm: fix unsigned 64 bit right shifts.
Fix range of shift amounts which always give 0 as result.
target-arm: Fix saturated values for Neon right shifts
Fix value returned by signed 8 and 16 bit qrshl helperswhen the result has saturated.
target-arm: fix Neon VQSHRN and VSHRN.
Call the normal shift helpers instead of the rounding ones.
target-arm: fix decoding of Neon 64 bit shifts.
Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN,VQRSHRN, VQRSHRUN, taking into account whether inputs are unsignedor not.
target-arm: Fix signed VQRSHL by large shift counts
Handle the case of signed VQRSHL by a shift count of the width of thedata type or larger, which must be special cased in the qrshl_s*helper functions.
target-arm: Fix unsigned VQRSHL by large shift counts
Correctly handle VQRSHL of unsigned values by a shift count of thewidth of the data type or larger, which must be special-cased in theqrshl_u* helper functions.
target-arm: Move Neon VZIP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsogive the correct answers where the inline implementation did not....
target-arm: Move Neon VUZP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsofix the handling of the quadword version of the instruction....
target-arm: Correct conversion of Thumb Neon dp encodings into ARM
We handle Thumb Neon data processing instructions by converting theminto the equivalent ARM encoding, as the two are very close. Howeverthe ARM encoding should have bit 28 set, not clear. This wasn't causing...
target-arm: Fix Neon VQDMLSL instruction
For VQDMLSL, negation has to occur after saturation, not before.
target-arm: Refactor handling of VQDMULL
Refactor the handling of VQDMULL so that it is dealt with inits own if() case rather than together with the accumulatinginstructions.
target-arm: Implement VMULL.P8
Implement VMULL.P8 (the 32x32->64 version of the polynomial multiplyinstruction).
arm: drop unused irq-related part of CPUARMState
These two fields were added as a part of ARMv7 support patch (back in2007), were never used by any code, so can be dropped.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Remove stray #include from middle of neon_helper.c
Remove a stray #include <stdio.h> from the middle of neon_helper.c:it was harmless but pointless since we include stdio.h at the topof the file anyway.
target-arm: Silence NaNs resulting from half-precision conversions
Silence the NaNs that may result from half-precision conversion,as we do for the other conversions.
target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 andVCVT.F32.F16) use ARM standard floating-point arithmetic, unlikethe VFP versions (VCVTB and VCVTT).
softfloat: Add float16 type and float16 NaN handling functions
Add a float16 type to softfloat, rather than using bits16 directly.Also add the missing functions float16_is_quiet_nan(),float16_is_signaling_nan() and float16_maybe_silence_nan(),which are needed for the float16 conversion routines....
target-arm: implement vsli.64, vsri.64
target-arm: fix VSHLL Neon instruction.
Fix bit mask used when widening the result of shift on narrow input.
target-arm: Fix 32 bit signed saturating narrow
The returned value when doing saturating signed 64->32 bitconversion of a negative number was incorrect due to a missing cast.
target-arm: Fix VQMOVUN Neon instruction.
VQMOVUN does a signed-to-unsigned saturating conversion. This isdifferent from both the signed-to-signed and unsigned-to-unsignedconversions already implemented, so we need a new set of helperfunctions (neon_unarrow_sat*)....
target-arm: Clean up handling of MPIDR
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architectureas the MPIDR. Clean up its implementation to remove A9 specific handling.
This commit includes fixing an error in the value returned for theMPIDR on A9, where we were erroneously claiming a cluster ID of 9....
target-arm: Fix decoding of preload and memory hint space
Correct the decoding of the ARM preload and memory hint space,by adding decoding of PLI, PLDW and the v7MP unallocated hintspace. This commit also corrects a slightly overexuberantdecoding of PLD which was not checking that bit 4...
target-arm: Fix decoding of Thumb preload and hint space
Refine the decoding of the Thumb preload and hint space, so weUNDEF on the patterns that are supposed to UNDEF rather than NOP.We also move the tests for this space earlier, so we don't emitharmless but unnecessary address generation code for preload...
target-arm: Add CPU feature flag for v7MP
Add a CPU feature flag for v7MP (the multiprocessing extensions); someinstructions exist only for v7MP and not for the base v7 architecture.
Set the right overflow bit for neon 32 and 64 bit saturating add/sub.
target-arm: Fix Neon vsra instructions.
This patch fixes the errors reported by my tests in VSRA.
target-arm: Fix Neon VQDMULH.S16 instructions
Correct an error in the implementation of the 16 bitforms of VQDMULH, bringing them into line with the32 bit implementation.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
Support saturation with shift=0.
This patch fixes corner-case saturations, when the target range iszero. It merely removes the guard against (sh == 0), and makes:_ssat(0x87654321, 1) return 0xffffffff and set the saturation flag_usat(0x87654321, 0) return 0 and set the saturation flag...
target-arm: Fix garbage collection of temporaries in Neon emulation.
Fix garbage collection of temporaries in Neon emulation.
target-arm: Fix loading of scalar value for Neon multiply-by-scalar
Fix the register and part of register we get the scalar from inthe various "multiply vector by scalar" ops (VMUL by scalarand friends).
target-arm: Log instruction start in TCG code
Add support for logging the start of instructions in TCGcode debug dumps for ARM targets.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
target-arm: Restore IT bits when resuming after an exception
We were not correctly restoring the IT bits when resuming executionafter taking an unexpected exception in the middle of an IT block.Fix this by tracking them along with PC changes and restoring in...