Statistics
| Branch: | Revision:

root / target-arm / helper.c @ 43fe9bdb

History | View | Annotate | Download (85.6 kB)

# Date Author Comment
43fe9bdb 05/23/2011 11:39 pm Peter Maydell

target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTS

The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormals
as special cases, so we must set the InputDenormal exception flag ourselves.

Signed-off-by: Peter Maydell <>...
1146a817 05/23/2011 11:39 pm Peter Maydell

target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fns

The functions which do the core estimation algorithms for the VRSQRTE
and VRECPE instructions should not set floating point exception flags,
so use a local fp status for doing these calculations....
ec444452 04/20/2011 02:01 pm Peter Maydell

target-arm: Set Invalid flag for NaN in float-to-int conversions

When we catch the special case of an input NaN in ARM float to int
helper functions, set the Invalid flag as well as returning the
correct result.

Signed-off-by: Peter Maydell <>...
5bc95aa2 04/20/2011 01:59 pm Dmitry Eremin-Solenikov

Implement basic part of SA-1110/SA-1100

Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.
Implemented:
- IRQs
- GPIO
- PPC
- RTC
- UARTs (no IrDA/etc.)
- OST reused from pxa25x

Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the...
7b59220e 04/17/2011 09:41 pm Lluís

move helpers.h to helper.h

This provides a consistent naming scheme across all targets.

Signed-off-by: Lluís Vilanova <>
Signed-off-by: Aurelien Jarno <>
61cc8701 04/16/2011 02:24 pm Stefan Weil

Fix some typos in comments and documentation

helpfull -> helpful
usefull -> useful
cotrol -> control

and a grammar fix.

Signed-off-by: Stefan Weil <>
Signed-off-by: Stefan Hajnoczi <>
9df38c47 04/13/2011 12:33 am Peter Maydell

target-arm: Detect tininess before rounding for FP operations

The ARM architecture mandates that we detect tininess before rounding,
so set the softfloat fp_status up appropriately.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
be5e7a76 04/10/2011 01:53 am Dmitry Eremin-Solenikov

arm: basic support for ARMv4/ARMv4T emulation

Currently target-arm/ assumes at least ARMv5 core. Add support for
handling also ARMv4/ARMv4T. This changes the following instructions:

BX

BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
622465e1 04/03/2011 06:19 pm Peter Maydell

target-arm/helper.c: For float-int conversion helpers pass ints as ints

Correct the argument and return types for the float<->int conversion helper
functions so that integer arguments and return values are declared as
uint32_t/uint64_t, not float32/float64. This allows us to remove the...
6aae3df1 03/22/2011 08:59 am Peter Maydell

target-arm: use make_float32() to make constant floats for VRSQRTS

The preferred way to create a constant floating point value is to use
make_float32() rather than doing a runtime int32_to_float32().
Convert the code in the VRSQRTS helper to work this way....
dda3ec49 03/22/2011 08:59 am Peter Maydell

target-arm: Fix VRECPS edge cases handling

Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0

Signed-off-by: Peter Maydell <>...
db6e2e65 03/22/2011 08:52 am Peter Maydell

target-arm: Fix GE bits for v6media signed modulo arithmetic

Fix the signed modulo arithmetic helpers for the v6media
instructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to set
the GE bits correctly (based on the result of the add or subtract
before it is truncated to 16 bits, not after)....
f8bf8606 03/07/2011 12:37 am Adam Lackorzynski

target-arm: Implement cp15 VA->PA translation

Implement VA->PA translations by cp15-c7 that went through unchanged
previously.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>
56bf4fe2 02/24/2011 09:53 am Christophe Lyon

target-arm: Introduce float64_256 and float64_512 constants.

These two constants will be used by helper functions such as recpe_f32
and rsqrte_f32.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>...
fe0e4872 02/24/2011 09:53 am Christophe Lyon

target-arm: fix support for VRECPE.

Now use the same algorithm as described in the ARM ARM.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
e07be5d2 02/24/2011 09:53 am Christophe Lyon

target-arm: fix support for VRSQRTE.

Now use the same algorithm as described in the ARM ARM.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
fb91678d 02/10/2011 07:28 pm Peter Maydell

target-arm: Silence NaNs resulting from half-precision conversions

Silence the NaNs that may result from half-precision conversion,
as we do for the other conversions.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
2d981da7 02/10/2011 07:28 pm Peter Maydell

target-arm: Use standard FPSCR for Neon half-precision operations

The Neon half-precision conversion operations (VCVT.F16.F32 and
VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike
the VFP versions (VCVTB and VCVTT).

Signed-off-by: Peter Maydell <>...
bb4d4bb3 02/10/2011 07:28 pm Peter Maydell

softfloat: Add float16 type and float16 NaN handling functions

Add a float16 type to softfloat, rather than using bits16 directly.
Also add the missing functions float16_is_quiet_nan(),
float16_is_signaling_nan() and float16_maybe_silence_nan(),
which are needed for the float16 conversion routines....
607b4b08 02/04/2011 10:30 pm Peter Maydell

target-arm: Clean up handling of MPIDR

The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture
as the MPIDR. Clean up its implementation to remove A9 specific handling.

This commit includes fixing an error in the value returned for the
MPIDR on A9, where we were erroneously claiming a cluster ID of 9....
e1bbf446 02/04/2011 10:30 pm Peter Maydell

target-arm: Add CPU feature flag for v7MP

Add a CPU feature flag for v7MP (the multiprocessing extensions); some
instructions exist only for v7MP and not for the base v7 architecture.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
9ea62f57 01/14/2011 09:39 pm Peter Maydell

target-arm: Fix implementation of VRSQRTS

The implementation of the ARM VRSQRTS instruction (which calculates
(3 - op1 * op2) / 2) was missing the division operation. It also
did not handle the special cases of (0,inf) and (inf,0).

Signed-off-by: Peter Maydell <>...
3a492f3a 01/14/2011 09:39 pm Peter Maydell

target-arm: Add support for 'Standard FPSCR Value' as used by Neon

Add support to the ARM helper routines for a second fp_status value
which should be used for operations which the ARM ARM indicates use
"ARM standard floating-point arithmetic" rather than being controlled...
71826966 01/14/2011 09:39 pm Peter Maydell

target-arm: Use the standard FPSCR value for VRSQRTS

VSQRTS always uses the standard FPSCR value as it is a Neon instruction.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>
Signed-off-by: Aurelien Jarno <>
39ea3d4e 01/14/2011 09:39 pm Peter Maydell

target-arm: Don't generate code specific to current CPU mode for SRS

When translating the SRS instruction, handle the "store registers
to stack of current mode" case in the helper function rather than
inline. This means the generated code does not make assumptions...
b12c390b 01/06/2011 11:16 pm Peter Maydell

target-arm: Set softfloat cumulative exc flags from correct FPSCR bits

When handling a write to the ARM FPSCR, set the softfloat cumulative
exception flags from the cumulative flags in the FPSCR, not the
exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host...
cecd8504 01/06/2011 11:16 pm Peter Maydell

target-arm: wire up the softfloat flush_input_to_zero flag

Wire up the new softfloat support for flushing input denormals
to zero on ARM. The FPSCR FZ bit enables flush-to-zero for
both inputs and outputs, but the reporting of when inputs are
flushed to zero is via a separate IDC bit rather than the UFC...
9c486ad6 12/27/2010 10:21 pm Mattias Holm

target-arm: correct cp15 c1_sys reset value for cortex-a8

Signed-off-by: Juha Riihimäki <>
Signed-off-by: Aurelien Jarno <>
16440c5f 12/27/2010 10:21 pm Juha Riihimäki

target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9

Signed-off-by: Juha Riihimäki <>
Signed-off-by: Aurelien Jarno <>
c0034328 12/27/2010 10:21 pm Juha Riihimäki

target-arm: fix vmsav6 access control

Override access control checks (including execute) for mmu translation
table descriptors assigned to manager domains.

Signed-off-by: Juha Riihimäki <>
Signed-off-by: Aurelien Jarno <>
09d9487f 12/07/2010 05:37 pm Peter Maydell

ARM: Return correct result for float-to-integer conversion of NaN

The ARM architecture mandates that converting a NaN value to
integer gives zero (if Invalid Operation FP exceptions are
not being trapped). This isn't the behaviour of the SoftFloat
library, so NaNs must be special-cased....
2d627737 12/07/2010 05:37 pm Peter Maydell

ARM: Return correct result for single<->double conversion of NaN

The ARM ARM defines that if the input to a single<->double conversion
is a NaN then the output is always forced to be a quiet NaN by setting
the most significant bit of the fraction part.

Signed-off-by: Peter Maydell <>...
26a5e69a 12/07/2010 05:37 pm Peter Maydell

ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point

VCVT of 16 bit fixed point to float should ignore the top 16 bits
of the source register. Cast to int16_t and friends rather than
int16 -- the former is guaranteed exactly 16 bits wide where the...
72f24d15 12/07/2010 05:37 pm Peter Maydell

ARM: Implement VCVT to 16 bit integer using new softfloat routines

Use the softfloat conversion routines for conversion to 16 bit
integers, because just casting to a 16 bit type truncates the
value rather than saturating it at 16-bit MAXINT/MININT.

Signed-off-by: Peter Maydell <>...
3a807dec 12/03/2010 03:09 pm Peter Maydell

ARM: enable XScale/iWMMXT in linux-user mode

In linux-user mode, the XScale/iWMMXT coprocessors must be enabled
at reset so that we can run code that uses these instructions.

Signed-off-by: Peter Maydell <>
01653295 12/03/2010 03:09 pm Peter Maydell

ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C code

Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C
code as well as generated code, so we can use them to read and
write the FPSCR when saving and restoring VFP registers across
signal handlers in linux-user mode....
9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...
4c4fd3f8 07/02/2010 12:45 am Chih-Min Chao

target-arm : fix parallel saturated subtraction implementation

Signed-off-by: Chih-Min Chao <>
Signed-off-by: Aurelien Jarno <>
e03c22a9 05/31/2010 08:40 pm Lars Munch

arm: fix arm kernel boot for non zero start addr

Booting an arm kernel has been broken a while when booting from non zero start
address. This is due to the order of events: board init loads the kernel and
sets register 15 to the start address and then qemu_system_reset reset the cpu...
4f78c9ad 04/05/2010 09:56 pm Paul Brook

Fix arm-linux-user

Only include hw/loader.h from target-arm/helper.c when building for
system emulation.

Signed-off-by: Paul Brook <>
983fe826 04/05/2010 09:43 pm Paul Brook

ARMv7-M reset fixes

Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board
reset routine to call this. Also load values directly from ROM as
images have not been copied yet.

Avoid clearing the NVIC pointer on cpu reset.

Signed-off-by: Paul Brook <>
3ad493fc 03/27/2010 03:14 pm Rabin Vincent

target-arm: disable PAGE_EXEC for XN pages

Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection
checking if the page is already in the TLB.

Signed-off-by: Rabin Vincent <>
Signed-off-by: Aurelien Jarno <>
d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...
4fcc562b 03/12/2010 08:34 pm Paul Brook

Remove cpu_get_phys_page_debug from userspace emulation

cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <>
30a8cac1 02/19/2010 05:20 pm Rabin Vincent

target-arm: support thumb exception handlers

When handling an exception, switch to the correct mode based on the
Thumb Exception (TE) bit in the SCTLR.

Signed-off-by: Rabin Vincent <>
3f26c122 02/06/2010 06:19 pm Riku Voipio

target-arm: refactor cp15.c13 register access

Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled...
426f5abc 11/22/2009 11:35 pm Paul Brook

ARM atomic ops rewrite

Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <>
60011498 11/19/2009 06:45 pm Paul Brook

ARM FP16 support

Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <>
10055562 11/19/2009 06:45 pm Paul Brook

ARM Cortex-A9 cpu support

Basic Cortex-A9 support.

Signed-off-by: Paul Brook <>
71b3c3de 10/27/2009 10:46 am Juha Riihimäki

target-arm: allow modifying vfp fpexc en bit only

All other bits except for the EN in the VFP FPEXC register are defined
as subarchitecture specific and real functionality for any of the
other bits has not been implemented in QEMU. However, current code
allows modifying all bits in the VFP FPEXC register leading to...
7bbcb0af 10/23/2009 01:05 am Aurelien Jarno

target-arm: use clz32() instead of a for loop

Signed-off-by: Aurelien Jarno <>
Acked-by: Laurent Desnogues <>
686eeb93 10/23/2009 01:05 am Aurelien Jarno

target-arm: fix sdiv helper

(INT32_MIN / -1) triggers an overflow, and the result depends on the
host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a
test to output the correct value.

Signed-off-by: Aurelien Jarno <>...
c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...
99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>
0bf46a40 04/24/2009 09:03 pm aliguori

qemu: introduce qemu_init_vcpu (Marcelo Tosatti)

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
533d177a 03/08/2009 12:10 am aurel32

Fix correct reset value for ARM CP15 c1 auxiliary control register

According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary control
register is 2, not zero (page 3.12).

Signed-off-by: Riku Voipio <>
Acked-by: Laurent Desnogues <>...
2b3ea315 03/07/2009 11:48 pm aurel32

clean build: Fix arm build warnings

Fix remaining arm warnings - except for the mess in the NetWinder FP
emulator.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6766 c046a42c-6fe2-441c-8c8c-71466251a162
0d0266a5 02/06/2009 12:06 am aliguori

targets: remove error handling from qemu_malloc() callers (Avi Kivity)

Signed-off-by: Avi Kivity <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
eca1bdf4 01/26/2009 09:54 pm aliguori

Log reset events (Jan Kiszka)

Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <>...
fe76d976 12/19/2008 04:33 pm pbrook

Implement flush-to-zero mode (denormal results are replaced with zero).

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6107 c046a42c-6fe2-441c-8c8c-71466251a162
5c7908ed 12/19/2008 03:53 pm pbrook

Implement default-NaN mode.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6106 c046a42c-6fe2-441c-8c8c-71466251a162
a49ea279 12/19/2008 03:37 pm pbrook

Implement ARMv7 cp15 cache ID registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
fe1479c3 12/19/2008 03:18 pm pbrook

Implement (very) basic Thumb2-EE support. This doesn't actually implement
EE state, just the associated system coprocessor registers. It is sufficient
to keep OS setup and context switching code happy.

Signed-off-by: Paul Brook <>
...
644ad806 12/19/2008 03:02 pm pbrook

Fix VFP fixed point conversion routines.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
d4934d18 12/19/2008 02:39 pm pbrook

Implement ARMv7 MMU access permissions.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6099 c046a42c-6fe2-441c-8c8c-71466251a162
b2fa1797 10/22/2008 10:22 pm pbrook

Fix ARMv6 translation table base address calculation.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
4be27dbb 10/22/2008 07:14 pm pbrook

Optimize redundant cp15 coprocessor access control register writes.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5512 c046a42c-6fe2-441c-8c8c-71466251a162
56aebc89 10/11/2008 08:55 pm pbrook

Add GDB XML register description support.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
a87aa10b 07/19/2008 01:46 pm balrog

ARMv6: fix SIMD add/sub carry flags (Vincent Palatin).

After a quick code review, it seems to be a bad cut-n-paste between
16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits by
pair instead of one at a time.
Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT...
22478e79 07/19/2008 01:12 pm balrog

Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).

helper.c
- copy reference c0_c2 to runtime c0_c2 and not c0_c1

op_helper.c
- remove old code (PARAM1, probably some left over from old dyngen)
that broke do_[us]sat

translate.c...
ab19b0ec 07/02/2008 07:44 pm pbrook

ARMv7-M interrupt stack alignment fix.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4823 c046a42c-6fe2-441c-8c8c-71466251a162
460a09c1 05/01/2008 03:04 pm pbrook

Fix incorrect argument types.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4291 c046a42c-6fe2-441c-8c8c-71466251a162
601d70b9 04/20/2008 04:03 am balrog

Remove an unused field and fix some non-code typos.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
66230e0d 04/20/2008 03:58 am balrog

Correct more ARM VFP 32/64 and signed/unsigned typos.

Fixes unreadable fonts in Maemo guest.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4221 c046a42c-6fe2-441c-8c8c-71466251a162
827df9f3 04/15/2008 12:05 am balrog

Add basic OMAP2 chip support.

Add the OMAP242x (arm1136 core) initialisation with basic on-chip
peripherals and update OMAP1 peripherals which are re-used in OMAP2.
Make palmte.c and sd.c errors go to stderr.
Allow disabling SD chipselect.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
6c95676b 04/13/2008 03:57 am balrog

Store the right TCG temp (typo).

Stops ARMv6 target from segfaulting early.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
ca10f867 04/12/2008 12:35 am aurel32

Remove osdep.c/qemu-img code duplication

(Kevin Wolf)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
1654b2d6 04/11/2008 07:55 am aurel32

Fix few spelling issues in comments

(Stefan Weil)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4187 c046a42c-6fe2-441c-8c8c-71466251a162
6fbe23d5 04/01/2008 08:19 pm pbrook

ARM N=Z=1 flag fix.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
ad69471c 03/31/2008 06:48 am pbrook

ARM TCG conversion 14/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162
8f8e3aa4 03/31/2008 06:48 am pbrook

ARM TCG conversion 13/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4150 c046a42c-6fe2-441c-8c8c-71466251a162
8984bd2e 03/31/2008 06:47 am pbrook

ARM TCG conversion 12/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4149 c046a42c-6fe2-441c-8c8c-71466251a162
5e3f878a 03/31/2008 06:47 am pbrook

ARM TCG conversion 11/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4148 c046a42c-6fe2-441c-8c8c-71466251a162
4373f3ce 03/31/2008 06:47 am pbrook

ARM TCG conversion 10/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
b0109805 03/31/2008 06:47 am pbrook

ARM TCG conversion 9/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
6ddbc6e4 03/31/2008 06:46 am pbrook

ARM TCG conversion 7/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
3670669c 03/31/2008 06:46 am pbrook

ARM TCG conversion 6/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4143 c046a42c-6fe2-441c-8c8c-71466251a162
1497c961 03/31/2008 06:45 am pbrook

ARM TCG conversion 4/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4141 c046a42c-6fe2-441c-8c8c-71466251a162
f51bbbfe 03/31/2008 06:45 am pbrook

ARM TCG conversion 2/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4139 c046a42c-6fe2-441c-8c8c-71466251a162
b26eefb6 03/31/2008 06:44 am pbrook

ARM TCG conversion 1/16.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4138 c046a42c-6fe2-441c-8c8c-71466251a162
01ba9816 12/09/2007 04:22 am ths

Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
2ad207d4 11/25/2007 01:22 am pbrook

Thumb semihosting fixes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3729 c046a42c-6fe2-441c-8c8c-71466251a162
2f4a40e5 11/13/2007 03:50 am balrog

Prevent cpsr_write/_read be put out of line in op.o (fixes a segfault on some platforms).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3633 c046a42c-6fe2-441c-8c8c-71466251a162
9ee6e8bb 11/11/2007 02:04 am pbrook

ARMv7 support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
aaed909a 11/10/2007 05:15 pm bellard

added cpu_model parameter to cpu_init()

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
405ee3ad 10/31/2007 02:47 am balrog

Invalidate TLBs when domains are changed (Matthew Warton).
Legalise cp15 pid register writes (Matthew Warton).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3494 c046a42c-6fe2-441c-8c8c-71466251a162
6ebbf390 10/14/2007 10:07 am j_mayer

Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions....
c732abe2 10/12/2007 09:47 am j_mayer

Unify '-cpu ?' option.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
5fafdf24 09/17/2007 12:08 am ths

find -type f | xargs sed -i 's/[\t ]$//g' # on most files

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2e23213f 08/01/2007 05:31 am balrog

Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162