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1
/*
2
 * PXA270-based Clamshell PDA platforms.
3
 *
4
 * Copyright (c) 2006 Openedhand Ltd.
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 * Written by Andrzej Zaborowski <balrog@zabor.org>
6
 *
7
 * This code is licensed under the GNU GPL v2.
8
 */
9

    
10
#include "vl.h"
11

    
12
#define spitz_printf(format, ...)        \
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    fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
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#undef REG_FMT
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#if TARGET_PHYS_ADDR_BITS == 32
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#define REG_FMT                        "0x%02x"
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#else
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#define REG_FMT                        "0x%02lx"
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#endif
20

    
21
/* Spitz Flash */
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#define FLASH_BASE                0x0c000000
23
#define FLASH_ECCLPLB                0x00        /* Line parity 7 - 0 bit */
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#define FLASH_ECCLPUB                0x04        /* Line parity 15 - 8 bit */
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#define FLASH_ECCCP                0x08        /* Column parity 5 - 0 bit */
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#define FLASH_ECCCNTR                0x0c        /* ECC byte counter */
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#define FLASH_ECCCLRR                0x10        /* Clear ECC */
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#define FLASH_FLASHIO                0x14        /* Flash I/O */
29
#define FLASH_FLASHCTL                0x18        /* Flash Control */
30

    
31
#define FLASHCTL_CE0                (1 << 0)
32
#define FLASHCTL_CLE                (1 << 1)
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#define FLASHCTL_ALE                (1 << 2)
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#define FLASHCTL_WP                (1 << 3)
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#define FLASHCTL_CE1                (1 << 4)
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#define FLASHCTL_RYBY                (1 << 5)
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#define FLASHCTL_NCE                (FLASHCTL_CE0 | FLASHCTL_CE1)
38

    
39
struct sl_nand_s {
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    target_phys_addr_t target_base;
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    struct nand_flash_s *nand;
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    uint8_t ctl;
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    struct ecc_state_s ecc;
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};
45

    
46
static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
47
{
48
    struct sl_nand_s *s = (struct sl_nand_s *) opaque;
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    int ryby;
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    addr -= s->target_base;
51

    
52
    switch (addr) {
53
#define BSHR(byte, from, to)        ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
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    case FLASH_ECCLPLB:
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        return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
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                BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
57

    
58
#define BSHL(byte, from, to)        ((s->ecc.lp[byte] << (to - from)) & (1 << to))
59
    case FLASH_ECCLPUB:
60
        return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
61
                BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
62

    
63
    case FLASH_ECCCP:
64
        return s->ecc.cp;
65

    
66
    case FLASH_ECCCNTR:
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        return s->ecc.count & 0xff;
68

    
69
    case FLASH_FLASHCTL:
70
        nand_getpins(s->nand, &ryby);
71
        if (ryby)
72
            return s->ctl | FLASHCTL_RYBY;
73
        else
74
            return s->ctl;
75

    
76
    case FLASH_FLASHIO:
77
        return ecc_digest(&s->ecc, nand_getio(s->nand));
78

    
79
    default:
80
        spitz_printf("Bad register offset " REG_FMT "\n", addr);
81
    }
82
    return 0;
83
}
84

    
85
static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
86
{
87
    struct sl_nand_s *s = (struct sl_nand_s *) opaque;
88
    addr -= s->target_base;
89

    
90
    if (addr == FLASH_FLASHIO)
91
        return ecc_digest(&s->ecc, nand_getio(s->nand)) |
92
                (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
93

    
94
    return sl_readb(opaque, addr);
95
}
96

    
97
static void sl_writeb(void *opaque, target_phys_addr_t addr,
98
                uint32_t value)
99
{
100
    struct sl_nand_s *s = (struct sl_nand_s *) opaque;
101
    addr -= s->target_base;
102

    
103
    switch (addr) {
104
    case FLASH_ECCCLRR:
105
        /* Value is ignored.  */
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        ecc_reset(&s->ecc);
107
        break;
108

    
109
    case FLASH_FLASHCTL:
110
        s->ctl = value & 0xff & ~FLASHCTL_RYBY;
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        nand_setpins(s->nand,
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                        s->ctl & FLASHCTL_CLE,
113
                        s->ctl & FLASHCTL_ALE,
114
                        s->ctl & FLASHCTL_NCE,
115
                        s->ctl & FLASHCTL_WP,
116
                        0);
117
        break;
118

    
119
    case FLASH_FLASHIO:
120
        nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
121
        break;
122

    
123
    default:
124
        spitz_printf("Bad register offset " REG_FMT "\n", addr);
125
    }
126
}
127

    
128
static void sl_save(QEMUFile *f, void *opaque)
129
{
130
    struct sl_nand_s *s = (struct sl_nand_s *) opaque;
131

    
132
    qemu_put_8s(f, &s->ctl);
133
    ecc_put(f, &s->ecc);
134
}
135

    
136
static int sl_load(QEMUFile *f, void *opaque, int version_id)
137
{
138
    struct sl_nand_s *s = (struct sl_nand_s *) opaque;
139

    
140
    qemu_get_8s(f, &s->ctl);
141
    ecc_get(f, &s->ecc);
142

    
143
    return 0;
144
}
145

    
146
enum {
147
    FLASH_128M,
148
    FLASH_1024M,
149
};
150

    
151
static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
152
{
153
    int iomemtype;
154
    struct sl_nand_s *s;
155
    CPUReadMemoryFunc *sl_readfn[] = {
156
        sl_readb,
157
        sl_readb,
158
        sl_readl,
159
    };
160
    CPUWriteMemoryFunc *sl_writefn[] = {
161
        sl_writeb,
162
        sl_writeb,
163
        sl_writeb,
164
    };
165

    
166
    s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
167
    s->target_base = FLASH_BASE;
168
    s->ctl = 0;
169
    if (size == FLASH_128M)
170
        s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
171
    else if (size == FLASH_1024M)
172
        s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
173

    
174
    iomemtype = cpu_register_io_memory(0, sl_readfn,
175
                    sl_writefn, s);
176
    cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
177

    
178
    register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
179
}
180

    
181
/* Spitz Keyboard */
182

    
183
#define SPITZ_KEY_STROBE_NUM        11
184
#define SPITZ_KEY_SENSE_NUM        7
185

    
186
static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
187
    12, 17, 91, 34, 36, 38, 39
188
};
189

    
190
static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
191
    88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
192
};
193

    
194
/* Eighth additional row maps the special keys */
195
static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
196
    { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
197
    {  -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
198
    { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25,  -1 ,  -1 ,  -1  },
199
    { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26,  -1 , 0x36,  -1  },
200
    { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34,  -1 , 0x1c, 0x2a,  -1  },
201
    { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33,  -1 , 0x48,  -1 ,  -1 , 0x38 },
202
    { 0x37, 0x3d,  -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d,  -1 ,  -1  },
203
    { 0x52, 0x43, 0x01, 0x47, 0x49,  -1 ,  -1 ,  -1 ,  -1 ,  -1 ,  -1  },
204
};
205

    
206
#define SPITZ_GPIO_AK_INT        13        /* Remote control */
207
#define SPITZ_GPIO_SYNC                16        /* Sync button */
208
#define SPITZ_GPIO_ON_KEY        95        /* Power button */
209
#define SPITZ_GPIO_SWA                97        /* Lid */
210
#define SPITZ_GPIO_SWB                96        /* Tablet mode */
211

    
212
/* The special buttons are mapped to unused keys */
213
static const int spitz_gpiomap[5] = {
214
    SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
215
    SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
216
};
217
static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
218

    
219
struct spitz_keyboard_s {
220
    struct pxa2xx_state_s *cpu;
221
    int keymap[0x80];
222
    uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
223
    uint16_t strobe_state;
224
    uint16_t sense_state;
225

    
226
    uint16_t pre_map[0x100];
227
    uint16_t modifiers;
228
    uint16_t imodifiers;
229
    uint8_t fifo[16];
230
    int fifopos, fifolen;
231
    QEMUTimer *kbdtimer;
232
};
233

    
234
static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
235
{
236
    int i;
237
    uint16_t strobe, sense = 0;
238
    for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
239
        strobe = s->keyrow[i] & s->strobe_state;
240
        if (strobe) {
241
            sense |= 1 << i;
242
            if (!(s->sense_state & (1 << i)))
243
                pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 1);
244
        } else if (s->sense_state & (1 << i))
245
            pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 0);
246
    }
247

    
248
    s->sense_state = sense;
249
}
250

    
251
static void spitz_keyboard_strobe(int line, int level,
252
                struct spitz_keyboard_s *s)
253
{
254
    int i;
255
    for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
256
        if (spitz_gpio_key_strobe[i] == line) {
257
            if (level)
258
                s->strobe_state |= 1 << i;
259
            else
260
                s->strobe_state &= ~(1 << i);
261

    
262
            spitz_keyboard_sense_update(s);
263
            break;
264
        }
265
}
266

    
267
static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
268
{
269
    int spitz_keycode = s->keymap[keycode & 0x7f];
270
    if (spitz_keycode == -1)
271
        return;
272

    
273
    /* Handle the additional keys */
274
    if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
275
        pxa2xx_gpio_set(s->cpu->gpio, spitz_gpiomap[spitz_keycode & 0xf],
276
                        (keycode < 0x80) ^
277
                        spitz_gpio_invert[spitz_keycode & 0xf]);
278
        return;
279
    }
280

    
281
    if (keycode & 0x80)
282
        s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
283
    else
284
        s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
285

    
286
    spitz_keyboard_sense_update(s);
287
}
288

    
289
#define SHIFT        (1 << 7)
290
#define CTRL        (1 << 8)
291
#define FN        (1 << 9)
292

    
293
#define QUEUE_KEY(c)        s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
294

    
295
static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
296
{
297
    uint16_t code;
298
    int mapcode;
299
    switch (keycode) {
300
    case 0x2a:        /* Left Shift */
301
        s->modifiers |= 1;
302
        break;
303
    case 0xaa:
304
        s->modifiers &= ~1;
305
        break;
306
    case 0x36:        /* Right Shift */
307
        s->modifiers |= 2;
308
        break;
309
    case 0xb6:
310
        s->modifiers &= ~2;
311
        break;
312
    case 0x1d:        /* Control */
313
        s->modifiers |= 4;
314
        break;
315
    case 0x9d:
316
        s->modifiers &= ~4;
317
        break;
318
    case 0x38:        /* Alt */
319
        s->modifiers |= 8;
320
        break;
321
    case 0xb8:
322
        s->modifiers &= ~8;
323
        break;
324
    }
325

    
326
    code = s->pre_map[mapcode = ((s->modifiers & 3) ?
327
            (keycode | SHIFT) :
328
            (keycode & ~SHIFT))];
329

    
330
    if (code != mapcode) {
331
#if 0
332
        if ((code & SHIFT) && !(s->modifiers & 1))
333
            QUEUE_KEY(0x2a | (keycode & 0x80));
334
        if ((code & CTRL ) && !(s->modifiers & 4))
335
            QUEUE_KEY(0x1d | (keycode & 0x80));
336
        if ((code & FN   ) && !(s->modifiers & 8))
337
            QUEUE_KEY(0x38 | (keycode & 0x80));
338
        if ((code & FN   ) && (s->modifiers & 1))
339
            QUEUE_KEY(0x2a | (~keycode & 0x80));
340
        if ((code & FN   ) && (s->modifiers & 2))
341
            QUEUE_KEY(0x36 | (~keycode & 0x80));
342
#else
343
        if (keycode & 0x80) {
344
            if ((s->imodifiers & 1   ) && !(s->modifiers & 1))
345
                QUEUE_KEY(0x2a | 0x80);
346
            if ((s->imodifiers & 4   ) && !(s->modifiers & 4))
347
                QUEUE_KEY(0x1d | 0x80);
348
            if ((s->imodifiers & 8   ) && !(s->modifiers & 8))
349
                QUEUE_KEY(0x38 | 0x80);
350
            if ((s->imodifiers & 0x10) && (s->modifiers & 1))
351
                QUEUE_KEY(0x2a);
352
            if ((s->imodifiers & 0x20) && (s->modifiers & 2))
353
                QUEUE_KEY(0x36);
354
            s->imodifiers = 0;
355
        } else {
356
            if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
357
                QUEUE_KEY(0x2a);
358
                s->imodifiers |= 1;
359
            }
360
            if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
361
                QUEUE_KEY(0x1d);
362
                s->imodifiers |= 4;
363
            }
364
            if ((code & FN   ) && !((s->modifiers | s->imodifiers) & 8)) {
365
                QUEUE_KEY(0x38);
366
                s->imodifiers |= 8;
367
            }
368
            if ((code & FN   ) && (s->modifiers & 1) &&
369
                            !(s->imodifiers & 0x10)) {
370
                QUEUE_KEY(0x2a | 0x80);
371
                s->imodifiers |= 0x10;
372
            }
373
            if ((code & FN   ) && (s->modifiers & 2) &&
374
                            !(s->imodifiers & 0x20)) {
375
                QUEUE_KEY(0x36 | 0x80);
376
                s->imodifiers |= 0x20;
377
            }
378
        }
379
#endif
380
    }
381

    
382
    QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
383
}
384

    
385
static void spitz_keyboard_tick(void *opaque)
386
{
387
    struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
388

    
389
    if (s->fifolen) {
390
        spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
391
        s->fifolen --;
392
        if (s->fifopos >= 16)
393
            s->fifopos = 0;
394
    }
395

    
396
    qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
397
}
398

    
399
static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
400
{
401
    int i;
402
    for (i = 0; i < 0x100; i ++)
403
        s->pre_map[i] = i;
404
    s->pre_map[0x02 | SHIFT        ] = 0x02 | SHIFT;        /* exclam */
405
    s->pre_map[0x28 | SHIFT        ] = 0x03 | SHIFT;        /* quotedbl */
406
    s->pre_map[0x04 | SHIFT        ] = 0x04 | SHIFT;        /* numbersign */
407
    s->pre_map[0x05 | SHIFT        ] = 0x05 | SHIFT;        /* dollar */
408
    s->pre_map[0x06 | SHIFT        ] = 0x06 | SHIFT;        /* percent */
409
    s->pre_map[0x08 | SHIFT        ] = 0x07 | SHIFT;        /* ampersand */
410
    s->pre_map[0x28                ] = 0x08 | SHIFT;        /* apostrophe */
411
    s->pre_map[0x0a | SHIFT        ] = 0x09 | SHIFT;        /* parenleft */
412
    s->pre_map[0x0b | SHIFT        ] = 0x0a | SHIFT;        /* parenright */
413
    s->pre_map[0x29 | SHIFT        ] = 0x0b | SHIFT;        /* asciitilde */
414
    s->pre_map[0x03 | SHIFT        ] = 0x0c | SHIFT;        /* at */
415
    s->pre_map[0xd3                ] = 0x0e | FN;                /* Delete */
416
    s->pre_map[0x3a                ] = 0x0f | FN;                /* Caps_Lock */
417
    s->pre_map[0x07 | SHIFT        ] = 0x11 | FN;                /* asciicircum */
418
    s->pre_map[0x0d                ] = 0x12 | FN;                /* equal */
419
    s->pre_map[0x0d | SHIFT        ] = 0x13 | FN;                /* plus */
420
    s->pre_map[0x1a                ] = 0x14 | FN;                /* bracketleft */
421
    s->pre_map[0x1b                ] = 0x15 | FN;                /* bracketright */
422
    s->pre_map[0x1a | SHIFT        ] = 0x16 | FN;                /* braceleft */
423
    s->pre_map[0x1b | SHIFT        ] = 0x17 | FN;                /* braceright */
424
    s->pre_map[0x27                ] = 0x22 | FN;                /* semicolon */
425
    s->pre_map[0x27 | SHIFT        ] = 0x23 | FN;                /* colon */
426
    s->pre_map[0x09 | SHIFT        ] = 0x24 | FN;                /* asterisk */
427
    s->pre_map[0x2b                ] = 0x25 | FN;                /* backslash */
428
    s->pre_map[0x2b | SHIFT        ] = 0x26 | FN;                /* bar */
429
    s->pre_map[0x0c | SHIFT        ] = 0x30 | FN;                /* underscore */
430
    s->pre_map[0x33 | SHIFT        ] = 0x33 | FN;                /* less */
431
    s->pre_map[0x35                ] = 0x33 | SHIFT;        /* slash */
432
    s->pre_map[0x34 | SHIFT        ] = 0x34 | FN;                /* greater */
433
    s->pre_map[0x35 | SHIFT        ] = 0x34 | SHIFT;        /* question */
434
    s->pre_map[0x49                ] = 0x48 | FN;                /* Page_Up */
435
    s->pre_map[0x51                ] = 0x50 | FN;                /* Page_Down */
436

    
437
    s->modifiers = 0;
438
    s->imodifiers = 0;
439
    s->fifopos = 0;
440
    s->fifolen = 0;
441
    s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
442
    spitz_keyboard_tick(s);
443
}
444

    
445
#undef SHIFT
446
#undef CTRL
447
#undef FN
448

    
449
static void spitz_keyboard_save(QEMUFile *f, void *opaque)
450
{
451
    struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
452
    int i;
453

    
454
    qemu_put_be16s(f, &s->sense_state);
455
    qemu_put_be16s(f, &s->strobe_state);
456
    for (i = 0; i < 5; i ++)
457
        qemu_put_byte(f, spitz_gpio_invert[i]);
458
}
459

    
460
static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
461
{
462
    struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
463
    int i;
464

    
465
    qemu_get_be16s(f, &s->sense_state);
466
    qemu_get_be16s(f, &s->strobe_state);
467
    for (i = 0; i < 5; i ++)
468
        spitz_gpio_invert[i] = qemu_get_byte(f);
469

    
470
    /* Release all pressed keys */
471
    memset(s->keyrow, 0, sizeof(s->keyrow));
472
    spitz_keyboard_sense_update(s);
473
    s->modifiers = 0;
474
    s->imodifiers = 0;
475
    s->fifopos = 0;
476
    s->fifolen = 0;
477

    
478
    return 0;
479
}
480

    
481
static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
482
{
483
    int i, j;
484
    struct spitz_keyboard_s *s;
485

    
486
    s = (struct spitz_keyboard_s *)
487
            qemu_mallocz(sizeof(struct spitz_keyboard_s));
488
    memset(s, 0, sizeof(struct spitz_keyboard_s));
489
    s->cpu = cpu;
490

    
491
    for (i = 0; i < 0x80; i ++)
492
        s->keymap[i] = -1;
493
    for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
494
        for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
495
            if (spitz_keymap[i][j] != -1)
496
                s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
497

    
498
    for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
499
        pxa2xx_gpio_handler_set(cpu->gpio, spitz_gpio_key_strobe[i],
500
                        (gpio_handler_t) spitz_keyboard_strobe, s);
501

    
502
    spitz_keyboard_pre_map(s);
503
    qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
504

    
505
    register_savevm("spitz_keyboard", 0, 0,
506
                    spitz_keyboard_save, spitz_keyboard_load, s);
507
}
508

    
509
/* SCOOP devices */
510

    
511
struct scoop_info_s {
512
    target_phys_addr_t target_base;
513
    uint16_t status;
514
    uint16_t power;
515
    uint32_t gpio_level;
516
    uint32_t gpio_dir;
517
    uint32_t prev_level;
518
    struct {
519
        gpio_handler_t fn;
520
        void *opaque;
521
    } handler[16];
522

    
523
    uint16_t mcr;
524
    uint16_t cdr;
525
    uint16_t ccr;
526
    uint16_t irr;
527
    uint16_t imr;
528
    uint16_t isr;
529
    uint16_t gprr;
530
};
531

    
532
#define SCOOP_MCR        0x00
533
#define SCOOP_CDR        0x04
534
#define SCOOP_CSR        0x08
535
#define SCOOP_CPR        0x0c
536
#define SCOOP_CCR        0x10
537
#define SCOOP_IRR_IRM        0x14
538
#define SCOOP_IMR        0x18
539
#define SCOOP_ISR        0x1c
540
#define SCOOP_GPCR        0x20
541
#define SCOOP_GPWR        0x24
542
#define SCOOP_GPRR        0x28
543

    
544
static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
545
    uint32_t level, diff;
546
    int bit;
547
    level = s->gpio_level & s->gpio_dir;
548

    
549
    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
550
        bit = ffs(diff) - 1;
551
        if (s->handler[bit].fn)
552
            s->handler[bit].fn(bit, (level >> bit) & 1,
553
                            s->handler[bit].opaque);
554
    }
555

    
556
    s->prev_level = level;
557
}
558

    
559
static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
560
{
561
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
562
    addr -= s->target_base;
563

    
564
    switch (addr) {
565
    case SCOOP_MCR:
566
        return s->mcr;
567
    case SCOOP_CDR:
568
        return s->cdr;
569
    case SCOOP_CSR:
570
        return s->status;
571
    case SCOOP_CPR:
572
        return s->power;
573
    case SCOOP_CCR:
574
        return s->ccr;
575
    case SCOOP_IRR_IRM:
576
        return s->irr;
577
    case SCOOP_IMR:
578
        return s->imr;
579
    case SCOOP_ISR:
580
        return s->isr;
581
    case SCOOP_GPCR:
582
        return s->gpio_dir;
583
    case SCOOP_GPWR:
584
        return s->gpio_level;
585
    case SCOOP_GPRR:
586
        return s->gprr;
587
    default:
588
        spitz_printf("Bad register offset " REG_FMT "\n", addr);
589
    }
590

    
591
    return 0;
592
}
593

    
594
static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
595
{
596
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
597
    addr -= s->target_base;
598
    value &= 0xffff;
599

    
600
    switch (addr) {
601
    case SCOOP_MCR:
602
        s->mcr = value;
603
        break;
604
    case SCOOP_CDR:
605
        s->cdr = value;
606
        break;
607
    case SCOOP_CPR:
608
        s->power = value;
609
        if (value & 0x80)
610
            s->power |= 0x8040;
611
        break;
612
    case SCOOP_CCR:
613
        s->ccr = value;
614
        break;
615
    case SCOOP_IRR_IRM:
616
        s->irr = value;
617
        break;
618
    case SCOOP_IMR:
619
        s->imr = value;
620
        break;
621
    case SCOOP_ISR:
622
        s->isr = value;
623
        break;
624
    case SCOOP_GPCR:
625
        s->gpio_dir = value;
626
        scoop_gpio_handler_update(s);
627
        break;
628
    case SCOOP_GPWR:
629
        s->gpio_level = value & s->gpio_dir;
630
        scoop_gpio_handler_update(s);
631
        break;
632
    case SCOOP_GPRR:
633
        s->gprr = value;
634
        break;
635
    default:
636
        spitz_printf("Bad register offset " REG_FMT "\n", addr);
637
    }
638
}
639

    
640
CPUReadMemoryFunc *scoop_readfn[] = {
641
    scoop_readb,
642
    scoop_readb,
643
    scoop_readb,
644
};
645
CPUWriteMemoryFunc *scoop_writefn[] = {
646
    scoop_writeb,
647
    scoop_writeb,
648
    scoop_writeb,
649
};
650

    
651
static inline void scoop_gpio_set(struct scoop_info_s *s, int line, int level)
652
{
653
    if (line >= 16) {
654
        spitz_printf("No GPIO pin %i\n", line);
655
        return;
656
    }
657

    
658
    if (level)
659
        s->gpio_level |= (1 << line);
660
    else
661
        s->gpio_level &= ~(1 << line);
662
}
663

    
664
static inline void scoop_gpio_handler_set(struct scoop_info_s *s, int line,
665
                gpio_handler_t handler, void *opaque) {
666
    if (line >= 16) {
667
        spitz_printf("No GPIO pin %i\n", line);
668
        return;
669
    }
670

    
671
    s->handler[line].fn = handler;
672
    s->handler[line].opaque = opaque;
673
}
674

    
675
static void scoop_save(QEMUFile *f, void *opaque)
676
{
677
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
678
    qemu_put_be16s(f, &s->status);
679
    qemu_put_be16s(f, &s->power);
680
    qemu_put_be32s(f, &s->gpio_level);
681
    qemu_put_be32s(f, &s->gpio_dir);
682
    qemu_put_be32s(f, &s->prev_level);
683
    qemu_put_be16s(f, &s->mcr);
684
    qemu_put_be16s(f, &s->cdr);
685
    qemu_put_be16s(f, &s->ccr);
686
    qemu_put_be16s(f, &s->irr);
687
    qemu_put_be16s(f, &s->imr);
688
    qemu_put_be16s(f, &s->isr);
689
    qemu_put_be16s(f, &s->gprr);
690
}
691

    
692
static int scoop_load(QEMUFile *f, void *opaque, int version_id)
693
{
694
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
695
    qemu_get_be16s(f, &s->status);
696
    qemu_get_be16s(f, &s->power);
697
    qemu_get_be32s(f, &s->gpio_level);
698
    qemu_get_be32s(f, &s->gpio_dir);
699
    qemu_get_be32s(f, &s->prev_level);
700
    qemu_get_be16s(f, &s->mcr);
701
    qemu_get_be16s(f, &s->cdr);
702
    qemu_get_be16s(f, &s->ccr);
703
    qemu_get_be16s(f, &s->irr);
704
    qemu_get_be16s(f, &s->imr);
705
    qemu_get_be16s(f, &s->isr);
706
    qemu_get_be16s(f, &s->gprr);
707

    
708
    return 0;
709
}
710

    
711
static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
712
                int count) {
713
    int iomemtype;
714
    struct scoop_info_s *s;
715

    
716
    s = (struct scoop_info_s *)
717
            qemu_mallocz(sizeof(struct scoop_info_s) * 2);
718
    memset(s, 0, sizeof(struct scoop_info_s) * count);
719
    s[0].target_base = 0x10800000;
720
    s[1].target_base = 0x08800040;
721

    
722
    /* Ready */
723
    s[0].status = 0x02;
724
    s[1].status = 0x02;
725

    
726
    iomemtype = cpu_register_io_memory(0, scoop_readfn,
727
                    scoop_writefn, &s[0]);
728
    cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
729
    register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]);
730

    
731
    if (count < 2)
732
        return s;
733

    
734
    iomemtype = cpu_register_io_memory(0, scoop_readfn,
735
                    scoop_writefn, &s[1]);
736
    cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
737
    register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]);
738

    
739
    return s;
740
}
741

    
742
/* LCD backlight controller */
743

    
744
#define LCDTG_RESCTL        0x00
745
#define LCDTG_PHACTRL        0x01
746
#define LCDTG_DUTYCTRL        0x02
747
#define LCDTG_POWERREG0        0x03
748
#define LCDTG_POWERREG1        0x04
749
#define LCDTG_GPOR3        0x05
750
#define LCDTG_PICTRL        0x06
751
#define LCDTG_POLCTRL        0x07
752

    
753
static int bl_intensity, bl_power;
754

    
755
static void spitz_bl_update(struct pxa2xx_state_s *s)
756
{
757
    if (bl_power && bl_intensity)
758
        spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
759
    else
760
        spitz_printf("LCD Backlight now off\n");
761
}
762

    
763
static void spitz_bl_bit5(int line, int level, void *opaque)
764
{
765
    int prev = bl_intensity;
766

    
767
    if (level)
768
        bl_intensity &= ~0x20;
769
    else
770
        bl_intensity |= 0x20;
771

    
772
    if (bl_power && prev != bl_intensity)
773
        spitz_bl_update((struct pxa2xx_state_s *) opaque);
774
}
775

    
776
static void spitz_bl_power(int line, int level, void *opaque)
777
{
778
    bl_power = !!level;
779
    spitz_bl_update((struct pxa2xx_state_s *) opaque);
780
}
781

    
782
static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
783
{
784
    int addr, value;
785
    addr = cmd >> 5;
786
    value = cmd & 0x1f;
787

    
788
    switch (addr) {
789
    case LCDTG_RESCTL:
790
        if (value)
791
            spitz_printf("LCD in QVGA mode\n");
792
        else
793
            spitz_printf("LCD in VGA mode\n");
794
        break;
795

    
796
    case LCDTG_DUTYCTRL:
797
        bl_intensity &= ~0x1f;
798
        bl_intensity |= value;
799
        if (bl_power)
800
            spitz_bl_update((struct pxa2xx_state_s *) opaque);
801
        break;
802

    
803
    case LCDTG_POWERREG0:
804
        /* Set common voltage to M62332FP */
805
        break;
806
    }
807
}
808

    
809
/* SSP devices */
810

    
811
#define CORGI_SSP_PORT                2
812

    
813
#define SPITZ_GPIO_LCDCON_CS        53
814
#define SPITZ_GPIO_ADS7846_CS        14
815
#define SPITZ_GPIO_MAX1111_CS        20
816
#define SPITZ_GPIO_TP_INT        11
817

    
818
static int lcd_en, ads_en, max_en;
819
static struct max111x_s *max1111;
820
static struct ads7846_state_s *ads7846;
821

    
822
/* "Demux" the signal based on current chipselect */
823
static uint32_t corgi_ssp_read(void *opaque)
824
{
825
    if (lcd_en)
826
        return 0;
827
    if (ads_en)
828
        return ads7846_read(ads7846);
829
    if (max_en)
830
        return max111x_read(max1111);
831
    return 0;
832
}
833

    
834
static void corgi_ssp_write(void *opaque, uint32_t value)
835
{
836
    if (lcd_en)
837
        spitz_lcdtg_dac_put(opaque, value);
838
    if (ads_en)
839
        ads7846_write(ads7846, value);
840
    if (max_en)
841
        max111x_write(max1111, value);
842
}
843

    
844
static void corgi_ssp_gpio_cs(int line, int level, struct pxa2xx_state_s *s)
845
{
846
    if (line == SPITZ_GPIO_LCDCON_CS)
847
        lcd_en = !level;
848
    else if (line == SPITZ_GPIO_ADS7846_CS)
849
        ads_en = !level;
850
    else if (line == SPITZ_GPIO_MAX1111_CS)
851
        max_en = !level;
852
}
853

    
854
#define MAX1111_BATT_VOLT        1
855
#define MAX1111_BATT_TEMP        2
856
#define MAX1111_ACIN_VOLT        3
857

    
858
#define SPITZ_BATTERY_TEMP        0xe0        /* About 2.9V */
859
#define SPITZ_BATTERY_VOLT        0xd0        /* About 4.0V */
860
#define SPITZ_CHARGEON_ACIN        0x80        /* About 5.0V */
861

    
862
static void spitz_adc_temp_on(int line, int level, void *opaque)
863
{
864
    if (!max1111)
865
        return;
866

    
867
    if (level)
868
        max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
869
    else
870
        max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
871
}
872

    
873
static void spitz_pendown_set(void *opaque, int line, int level)
874
{
875
    struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
876
    pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_TP_INT, level);
877
}
878

    
879
static void spitz_ssp_save(QEMUFile *f, void *opaque)
880
{
881
    qemu_put_be32(f, lcd_en);
882
    qemu_put_be32(f, ads_en);
883
    qemu_put_be32(f, max_en);
884
    qemu_put_be32(f, bl_intensity);
885
    qemu_put_be32(f, bl_power);
886
}
887

    
888
static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
889
{
890
    lcd_en = qemu_get_be32(f);
891
    ads_en = qemu_get_be32(f);
892
    max_en = qemu_get_be32(f);
893
    bl_intensity = qemu_get_be32(f);
894
    bl_power = qemu_get_be32(f);
895

    
896
    return 0;
897
}
898

    
899
static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
900
{
901
    lcd_en = ads_en = max_en = 0;
902

    
903
    ads7846 = ads7846_init(qemu_allocate_irqs(spitz_pendown_set, cpu, 1)[0]);
904

    
905
    max1111 = max1111_init(0);
906
    max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
907
    max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
908
    max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
909

    
910
    pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
911
                    corgi_ssp_write, cpu);
912

    
913
    pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
914
                    (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
915
    pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
916
                    (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
917
    pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
918
                    (gpio_handler_t) corgi_ssp_gpio_cs, cpu);
919

    
920
    bl_intensity = 0x20;
921
    bl_power = 0;
922

    
923
    register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu);
924
}
925

    
926
/* CF Microdrive */
927

    
928
static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu)
929
{
930
    struct pcmcia_card_s *md;
931
    BlockDriverState *bs = bs_table[0];
932

    
933
    if (bs && bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
934
        md = dscm1xxxx_init(bs);
935
        pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
936
    }
937
}
938

    
939
/* Wm8750 and Max7310 on I2C */
940

    
941
#define AKITA_MAX_ADDR        0x18
942
#define SPITZ_WM_ADDRL        0x1b
943
#define SPITZ_WM_ADDRH        0x1a
944

    
945
#define SPITZ_GPIO_WM        5
946

    
947
#ifdef HAS_AUDIO
948
static void spitz_wm8750_addr(int line, int level, void *opaque)
949
{
950
    i2c_slave *wm = (i2c_slave *) opaque;
951
    if (level)
952
        i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
953
    else
954
        i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
955
}
956
#endif
957

    
958
static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
959
{
960
    /* Attach the CPU on one end of our I2C bus.  */
961
    i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
962

    
963
#ifdef HAS_AUDIO
964
    AudioState *audio;
965
    i2c_slave *wm;
966

    
967
    audio = AUD_init();
968
    if (!audio)
969
        return;
970
    /* Attach a WM8750 to the bus */
971
    wm = wm8750_init(bus, audio);
972

    
973
    spitz_wm8750_addr(0, 0, wm);
974
    pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_WM, spitz_wm8750_addr, wm);
975
    /* .. and to the sound interface.  */
976
    cpu->i2s->opaque = wm;
977
    cpu->i2s->codec_out = wm8750_dac_dat;
978
    cpu->i2s->codec_in = wm8750_adc_dat;
979
    wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
980
#endif
981
}
982

    
983
static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
984
{
985
    /* Attach a Max7310 to Akita I2C bus.  */
986
    i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
987
                    AKITA_MAX_ADDR);
988
}
989

    
990
/* Other peripherals */
991

    
992
static void spitz_charge_switch(int line, int level, void *opaque)
993
{
994
    spitz_printf("Charging %s.\n", level ? "off" : "on");
995
}
996

    
997
static void spitz_discharge_switch(int line, int level, void *opaque)
998
{
999
    spitz_printf("Discharging %s.\n", level ? "on" : "off");
1000
}
1001

    
1002
static void spitz_greenled_switch(int line, int level, void *opaque)
1003
{
1004
    spitz_printf("Green LED %s.\n", level ? "on" : "off");
1005
}
1006

    
1007
static void spitz_orangeled_switch(int line, int level, void *opaque)
1008
{
1009
    spitz_printf("Orange LED %s.\n", level ? "on" : "off");
1010
}
1011

    
1012
#define SPITZ_SCP_LED_GREEN                1
1013
#define SPITZ_SCP_JK_B                        2
1014
#define SPITZ_SCP_CHRG_ON                3
1015
#define SPITZ_SCP_MUTE_L                4
1016
#define SPITZ_SCP_MUTE_R                5
1017
#define SPITZ_SCP_CF_POWER                6
1018
#define SPITZ_SCP_LED_ORANGE                7
1019
#define SPITZ_SCP_JK_A                        8
1020
#define SPITZ_SCP_ADC_TEMP_ON                9
1021
#define SPITZ_SCP2_IR_ON                1
1022
#define SPITZ_SCP2_AKIN_PULLUP                2
1023
#define SPITZ_SCP2_BACKLIGHT_CONT        7
1024
#define SPITZ_SCP2_BACKLIGHT_ON                8
1025
#define SPITZ_SCP2_MIC_BIAS                9
1026

    
1027
static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
1028
                struct scoop_info_s *scp, int num)
1029
{
1030
    scoop_gpio_handler_set(&scp[0], SPITZ_SCP_CHRG_ON,
1031
                    spitz_charge_switch, cpu);
1032
    scoop_gpio_handler_set(&scp[0], SPITZ_SCP_JK_B,
1033
                    spitz_discharge_switch, cpu);
1034
    scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_GREEN,
1035
                    spitz_greenled_switch, cpu);
1036
    scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_ORANGE,
1037
                    spitz_orangeled_switch, cpu);
1038

    
1039
    if (num >= 2) {
1040
        scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT,
1041
                        spitz_bl_bit5, cpu);
1042
        scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON,
1043
                        spitz_bl_power, cpu);
1044
    }
1045

    
1046
    scoop_gpio_handler_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON,
1047
                    spitz_adc_temp_on, cpu);
1048
}
1049

    
1050
#define SPITZ_GPIO_HSYNC                22
1051
#define SPITZ_GPIO_SD_DETECT                9
1052
#define SPITZ_GPIO_SD_WP                81
1053
#define SPITZ_GPIO_ON_RESET                89
1054
#define SPITZ_GPIO_BAT_COVER                90
1055
#define SPITZ_GPIO_CF1_IRQ                105
1056
#define SPITZ_GPIO_CF1_CD                94
1057
#define SPITZ_GPIO_CF2_IRQ                106
1058
#define SPITZ_GPIO_CF2_CD                93
1059

    
1060
int spitz_hsync;
1061

    
1062
static void spitz_lcd_hsync_handler(void *opaque)
1063
{
1064
    struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1065
    pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_HSYNC, spitz_hsync);
1066
    spitz_hsync ^= 1;
1067
}
1068

    
1069
static void spitz_mmc_coverswitch_change(void *opaque, int in)
1070
{
1071
    struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1072
    pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_DETECT, in);
1073
}
1074

    
1075
static void spitz_mmc_writeprotect_change(void *opaque, int wp)
1076
{
1077
    struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1078
    pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_WP, wp);
1079
}
1080

    
1081
static void spitz_pcmcia_cb(void *opaque, int line, int level)
1082
{
1083
    struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1084
    static const int gpio_map[] = {
1085
        SPITZ_GPIO_CF1_IRQ, SPITZ_GPIO_CF1_CD,
1086
        SPITZ_GPIO_CF2_IRQ, SPITZ_GPIO_CF2_CD,
1087
    };
1088
    pxa2xx_gpio_set(cpu->gpio, gpio_map[line], level);
1089
}
1090

    
1091
static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
1092
{
1093
    qemu_irq *pcmcia_cb;
1094
    /*
1095
     * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
1096
     * read to satisfy broken guests that poll-wait for hsync.
1097
     * Simulating a real hsync event would be less practical and
1098
     * wouldn't guarantee that a guest ever exits the loop.
1099
     */
1100
    spitz_hsync = 0;
1101
    pxa2xx_gpio_read_notifier(cpu->gpio, spitz_lcd_hsync_handler, cpu);
1102
    pxa2xx_lcd_vsync_cb(cpu->lcd, spitz_lcd_hsync_handler, cpu);
1103

    
1104
    /* MMC/SD host */
1105
    pxa2xx_mmci_handlers(cpu->mmc, cpu, spitz_mmc_writeprotect_change,
1106
                    spitz_mmc_coverswitch_change);
1107

    
1108
    /* Battery lock always closed */
1109
    pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_BAT_COVER, 1);
1110

    
1111
    /* Handle reset */
1112
    pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ON_RESET, pxa2xx_reset, cpu);
1113

    
1114
    /* PCMCIA signals: card's IRQ and Card-Detect */
1115
    pcmcia_cb = qemu_allocate_irqs(spitz_pcmcia_cb, cpu, slots * 2);
1116
    if (slots >= 1)
1117
        pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], pcmcia_cb[0], pcmcia_cb[1]);
1118
    if (slots >= 2)
1119
        pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], pcmcia_cb[2], pcmcia_cb[3]);
1120

    
1121
    /* Initialise the screen rotation related signals */
1122
    spitz_gpio_invert[3] = 0;        /* Always open */
1123
    if (graphic_rotate) {        /* Tablet mode */
1124
        spitz_gpio_invert[4] = 0;
1125
    } else {                        /* Portrait mode */
1126
        spitz_gpio_invert[4] = 1;
1127
    }
1128
    pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWA, spitz_gpio_invert[3]);
1129
    pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWB, spitz_gpio_invert[4]);
1130
}
1131

    
1132
/* Write the bootloader parameters memory area.  */
1133

    
1134
#define MAGIC_CHG(a, b, c, d)        ((d << 24) | (c << 16) | (b << 8) | a)
1135

    
1136
struct __attribute__ ((__packed__)) sl_param_info {
1137
    uint32_t comadj_keyword;
1138
    int32_t comadj;
1139

    
1140
    uint32_t uuid_keyword;
1141
    char uuid[16];
1142

    
1143
    uint32_t touch_keyword;
1144
    int32_t touch_xp;
1145
    int32_t touch_yp;
1146
    int32_t touch_xd;
1147
    int32_t touch_yd;
1148

    
1149
    uint32_t adadj_keyword;
1150
    int32_t adadj;
1151

    
1152
    uint32_t phad_keyword;
1153
    int32_t phadadj;
1154
} spitz_bootparam = {
1155
    .comadj_keyword        = MAGIC_CHG('C', 'M', 'A', 'D'),
1156
    .comadj                = 125,
1157
    .uuid_keyword        = MAGIC_CHG('U', 'U', 'I', 'D'),
1158
    .uuid                = { -1 },
1159
    .touch_keyword        = MAGIC_CHG('T', 'U', 'C', 'H'),
1160
    .touch_xp                = -1,
1161
    .adadj_keyword        = MAGIC_CHG('B', 'V', 'A', 'D'),
1162
    .adadj                = -1,
1163
    .phad_keyword        = MAGIC_CHG('P', 'H', 'A', 'D'),
1164
    .phadadj                = 0x01,
1165
};
1166

    
1167
static void sl_bootparam_write(uint32_t ptr)
1168
{
1169
    memcpy(phys_ram_base + ptr, &spitz_bootparam,
1170
                    sizeof(struct sl_param_info));
1171
}
1172

    
1173
#define SL_PXA_PARAM_BASE        0xa0000a00
1174

    
1175
/* Board init.  */
1176
enum spitz_model_e { spitz, akita, borzoi, terrier };
1177

    
1178
static void spitz_common_init(int ram_size, int vga_ram_size,
1179
                DisplayState *ds, const char *kernel_filename,
1180
                const char *kernel_cmdline, const char *initrd_filename,
1181
                const char *cpu_model, enum spitz_model_e model, int arm_id)
1182
{
1183
    uint32_t spitz_ram = 0x04000000;
1184
    uint32_t spitz_rom = 0x00800000;
1185
    struct pxa2xx_state_s *cpu;
1186
    struct scoop_info_s *scp;
1187

    
1188
    if (!cpu_model)
1189
        cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
1190

    
1191
    /* Setup CPU & memory */
1192
    if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
1193
        fprintf(stderr, "This platform requires %i bytes of memory\n",
1194
                        spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE);
1195
        exit(1);
1196
    }
1197
    cpu = pxa270_init(spitz_ram, ds, cpu_model);
1198

    
1199
    sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
1200

    
1201
    cpu_register_physical_memory(0, spitz_rom,
1202
                    qemu_ram_alloc(spitz_rom) | IO_MEM_ROM);
1203

    
1204
    /* Setup peripherals */
1205
    spitz_keyboard_register(cpu);
1206

    
1207
    spitz_ssp_attach(cpu);
1208

    
1209
    scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2);
1210

    
1211
    spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2);
1212

    
1213
    spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
1214

    
1215
    spitz_i2c_setup(cpu);
1216

    
1217
    if (model == akita)
1218
        spitz_akita_i2c_setup(cpu);
1219

    
1220
    if (model == terrier)
1221
        /* A 6.0 GB microdrive is permanently sitting in CF slot 1.  */
1222
        spitz_microdrive_attach(cpu);
1223
    else if (model != akita)
1224
        /* A 4.0 GB microdrive is permanently sitting in CF slot 1.  */
1225
        spitz_microdrive_attach(cpu);
1226

    
1227
    /* Setup initial (reset) machine state */
1228
    cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
1229

    
1230
    arm_load_kernel(cpu->env, spitz_ram, kernel_filename, kernel_cmdline,
1231
                    initrd_filename, arm_id, PXA2XX_SDRAM_BASE);
1232
    sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
1233
}
1234

    
1235
static void spitz_init(int ram_size, int vga_ram_size,
1236
                const char *boot_device, DisplayState *ds,
1237
                const char **fd_filename, int snapshot,
1238
                const char *kernel_filename, const char *kernel_cmdline,
1239
                const char *initrd_filename, const char *cpu_model)
1240
{
1241
    spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1242
                kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
1243
}
1244

    
1245
static void borzoi_init(int ram_size, int vga_ram_size,
1246
                const char *boot_device, DisplayState *ds,
1247
                const char **fd_filename, int snapshot,
1248
                const char *kernel_filename, const char *kernel_cmdline,
1249
                const char *initrd_filename, const char *cpu_model)
1250
{
1251
    spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1252
                kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
1253
}
1254

    
1255
static void akita_init(int ram_size, int vga_ram_size,
1256
                const char *boot_device, DisplayState *ds,
1257
                const char **fd_filename, int snapshot,
1258
                const char *kernel_filename, const char *kernel_cmdline,
1259
                const char *initrd_filename, const char *cpu_model)
1260
{
1261
    spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1262
                kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
1263
}
1264

    
1265
static void terrier_init(int ram_size, int vga_ram_size,
1266
                const char *boot_device, DisplayState *ds,
1267
                const char **fd_filename, int snapshot,
1268
                const char *kernel_filename, const char *kernel_cmdline,
1269
                const char *initrd_filename, const char *cpu_model)
1270
{
1271
    spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1272
                kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
1273
}
1274

    
1275
QEMUMachine akitapda_machine = {
1276
    "akita",
1277
    "Akita PDA (PXA270)",
1278
    akita_init,
1279
};
1280

    
1281
QEMUMachine spitzpda_machine = {
1282
    "spitz",
1283
    "Spitz PDA (PXA270)",
1284
    spitz_init,
1285
};
1286

    
1287
QEMUMachine borzoipda_machine = {
1288
    "borzoi",
1289
    "Borzoi PDA (PXA270)",
1290
    borzoi_init,
1291
};
1292

    
1293
QEMUMachine terrierpda_machine = {
1294
    "terrier",
1295
    "Terrier PDA (PXA270)",
1296
    terrier_init,
1297
};