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/*
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 *  CRIS virtual CPU header
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 *
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 *  Copyright (c) 2007 AXIS Communications AB
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 *  Written by Edgar E. Iglesias
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_CRIS_H
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#define CPU_CRIS_H
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#define TARGET_LONG_BITS 32
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#include "cpu-defs.h"
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE        EM_CRIS
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#define EXCP_MMU_EXEC    0
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#define EXCP_MMU_READ    1
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#define EXCP_MMU_WRITE   2
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#define EXCP_MMU_FLUSH   3
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#define EXCP_MMU_FAULT   4
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#define EXCP_BREAK      16 /* trap.  */
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/* Register aliases. R0 - R15 */
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#define R_FP  8
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#define R_SP  14
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#define R_ACR 15
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/* Support regs, P0 - P15  */
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#define PR_BZ  0
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#define PR_VR  1
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#define PR_PID 2
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#define PR_SRS 3
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#define PR_WZ  4
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#define PR_EXS 5
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#define PR_EDA 6
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#define PR_MOF 7
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#define PR_DZ  8
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#define PR_EBP 9
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#define PR_ERP 10
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#define PR_SRP 11
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#define PR_CCS 13
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#define PR_USP 14
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#define PR_SPC 15
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/* CPU flags.  */
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#define S_FLAG 0x200
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#define R_FLAG 0x100
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#define P_FLAG 0x80
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#define U_FLAG 0x40
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#define P_FLAG 0x80
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#define U_FLAG 0x40
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#define I_FLAG 0x20
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#define X_FLAG 0x10
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#define N_FLAG 0x08
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#define Z_FLAG 0x04
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#define V_FLAG 0x02
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#define C_FLAG 0x01
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#define ALU_FLAGS 0x1F
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/* Condition codes.  */
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#define CC_CC   0
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#define CC_CS   1
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#define CC_NE   2
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#define CC_EQ   3
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#define CC_VC   4
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#define CC_VS   5
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#define CC_PL   6
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#define CC_MI   7
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#define CC_LS   8
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#define CC_HI   9
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#define CC_GE  10
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#define CC_LT  11
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#define CC_GT  12
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#define CC_LE  13
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#define CC_A   14
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#define CC_P   15
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/* Internal flags for the implementation.  */
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#define F_DELAYSLOT 1
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#define NB_MMU_MODES 2
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typedef struct CPUCRISState {
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        uint32_t regs[16];
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        /* P0 - P15 are referred to as special registers in the docs.  */
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        uint32_t pregs[16];
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        /* Pseudo register for the PC. Not directly accessable on CRIS.  */
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        uint32_t pc;
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        /* Pseudo register for the kernel stack.  */
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        uint32_t ksp;
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        /* These are setup up by the guest code just before transfering the
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           control back to the host.  */
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        int jmp;
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        uint32_t btarget;
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        int btaken;
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        /* Condition flag tracking.  */
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        uint32_t cc_op;
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        uint32_t cc_mask;
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        uint32_t cc_dest;
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        uint32_t cc_src;
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        uint32_t cc_result;
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        /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
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        int cc_size;
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        /* Extended arithmetics.  */
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        int cc_x_live;
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        int cc_x;
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        int exception_index;
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        int interrupt_request;
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        int interrupt_vector;
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        int fault_vector;
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        int trap_vector;
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        uint32_t debug1;
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        uint32_t debug2;
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        uint32_t debug3;
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        struct
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        {
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                int exec_insns;
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                int exec_loads;
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                int exec_stores;
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        } stats;
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        /* FIXME: add a check in the translator to avoid writing to support
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           register sets beyond the 4th. The ISA allows up to 256! but in
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           practice there is no core that implements more than 4.
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           Support function registers are used to control units close to the
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           core. Accesses do not pass down the normal hierarchy.
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        */
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        uint32_t sregs[4][16];
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        /* Linear feedback shift reg in the mmu. Used to provide pseudo
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           randomness for the 'hint' the mmu gives to sw for chosing valid
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           sets on TLB refills.  */
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        uint32_t mmu_rand_lfsr;
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        /*
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         * We just store the stores to the tlbset here for later evaluation
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         * when the hw needs access to them.
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         *
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         * One for I and another for D.
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         */
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        struct
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        {
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                uint32_t hi;
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                uint32_t lo;
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        } tlbsets[2][4][16];
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        int features;
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        int user_mode_only;
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        int halted;
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        jmp_buf jmp_env;
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        CPU_COMMON
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} CPUCRISState;
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CPUCRISState *cpu_cris_init(const char *cpu_model);
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int cpu_cris_exec(CPUCRISState *s);
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void cpu_cris_close(CPUCRISState *s);
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void do_interrupt(CPUCRISState *env);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
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   is returned if the signal was handled by the virtual CPU.  */
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int cpu_cris_signal_handler(int host_signum, void *pinfo,
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                           void *puc);
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void cpu_cris_flush_flags(CPUCRISState *, int);
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void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
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                          int is_asi);
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enum {
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    CC_OP_DYNAMIC, /* Use env->cc_op  */
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    CC_OP_FLAGS,
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    CC_OP_LOGIC,
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    CC_OP_CMP,
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    CC_OP_MOVE,
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    CC_OP_MOVE_PD,
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    CC_OP_MOVE_SD,
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    CC_OP_ADD,
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    CC_OP_ADDC,
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    CC_OP_MCP,
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    CC_OP_ADDU,
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    CC_OP_SUB,
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    CC_OP_SUBU,
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    CC_OP_NEG,
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    CC_OP_BTST,
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    CC_OP_MULS,
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    CC_OP_MULU,
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    CC_OP_DSTEP,
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    CC_OP_BOUND,
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    CC_OP_OR,
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    CC_OP_AND,
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    CC_OP_XOR,
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    CC_OP_LSL,
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    CC_OP_LSR,
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    CC_OP_ASR,
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    CC_OP_LZ
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};
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#define CCF_C 0x01
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#define CCF_V 0x02
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#define CCF_Z 0x04
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#define CCF_N 0x08
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#define CCF_X 0x10
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#define CRIS_SSP    0
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#define CRIS_USP    1
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void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector);
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void cris_set_macsr(CPUCRISState *env, uint32_t val);
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void cris_switch_sp(CPUCRISState *env);
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void do_cris_semihosting(CPUCRISState *env, int nr);
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enum cris_features {
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    CRIS_FEATURE_CF_ISA_MUL,
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};
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static inline int cris_feature(CPUCRISState *env, int feature)
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{
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    return (env->features & (1u << feature)) != 0;
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}
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void register_cris_insns (CPUCRISState *env);
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/* CRIS uses 8k pages.  */
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#define TARGET_PAGE_BITS 13
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#define MMAP_SHIFT TARGET_PAGE_BITS
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#define CPUState CPUCRISState
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#define cpu_init cpu_cris_init
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#define cpu_exec cpu_cris_exec
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#define cpu_gen_code cpu_cris_gen_code
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#define cpu_signal_handler cpu_cris_signal_handler
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUState *env)
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{
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        return !!(env->pregs[PR_CCS] & U_FLAG);
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}
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/* Support function regs.  */
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#define SFR_RW_GC_CFG      0][0
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#define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
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#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
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#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
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#define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
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#define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
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#define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
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#define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
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#include "cpu-all.h"
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#endif