Revision 4556bd8b hw/dma.c
b/hw/dma.c | ||
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57 | 57 |
uint8_t flip_flop; |
58 | 58 |
int dshift; |
59 | 59 |
struct dma_regs regs[4]; |
60 |
qemu_irq *cpu_request_exit; |
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60 | 61 |
} dma_controllers[2]; |
61 | 62 |
|
62 | 63 |
enum { |
... | ... | |
444 | 445 |
/* request the emulator to transfer a new DMA memory block ASAP */ |
445 | 446 |
void DMA_schedule(int nchan) |
446 | 447 |
{ |
447 |
CPUState *env = cpu_single_env;
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|
448 |
if (env) |
|
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cpu_exit(env);
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448 |
struct dma_cont *d = &dma_controllers[nchan > 3];
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449 |
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qemu_irq_pulse(*d->cpu_request_exit);
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450 | 451 |
} |
451 | 452 |
|
452 | 453 |
static void dma_reset(void *opaque) |
... | ... | |
464 | 465 |
|
465 | 466 |
/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */ |
466 | 467 |
static void dma_init2(struct dma_cont *d, int base, int dshift, |
467 |
int page_base, int pageh_base) |
|
468 |
int page_base, int pageh_base, |
|
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qemu_irq *cpu_request_exit) |
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468 | 470 |
{ |
469 | 471 |
static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
470 | 472 |
int i; |
471 | 473 |
|
472 | 474 |
d->dshift = dshift; |
475 |
d->cpu_request_exit = cpu_request_exit; |
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473 | 476 |
for (i = 0; i < 8; i++) { |
474 | 477 |
register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
475 | 478 |
register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
... | ... | |
539 | 542 |
} |
540 | 543 |
}; |
541 | 544 |
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542 |
void DMA_init (int high_page_enable)
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void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
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543 | 546 |
{ |
544 | 547 |
dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
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high_page_enable ? 0x480 : -1); |
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high_page_enable ? 0x480 : -1, cpu_request_exit);
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546 | 549 |
dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
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high_page_enable ? 0x488 : -1); |
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high_page_enable ? 0x488 : -1, cpu_request_exit);
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548 | 551 |
vmstate_register (0, &vmstate_dma, &dma_controllers[0]); |
549 | 552 |
vmstate_register (1, &vmstate_dma, &dma_controllers[1]); |
550 | 553 |
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