Revision 45d827d2
b/configure | ||
---|---|---|
1605 | 1605 |
;; |
1606 | 1606 |
ppc) |
1607 | 1607 |
echo "TARGET_ARCH=ppc" >> $config_mak |
1608 |
echo "CONFIG_DYNGEN_OP=yes" >> $config_mak |
|
1609 | 1608 |
echo "#define TARGET_ARCH \"ppc\"" >> $config_h |
1610 | 1609 |
echo "#define TARGET_PPC 1" >> $config_h |
1611 |
echo "#define CONFIG_DYNGEN_OP 1" >> $config_h |
|
1612 | 1610 |
;; |
1613 | 1611 |
ppcemb) |
1614 | 1612 |
echo "TARGET_ARCH=ppcemb" >> $config_mak |
1615 | 1613 |
echo "TARGET_ABI_DIR=ppc" >> $config_mak |
1616 |
echo "CONFIG_DYNGEN_OP=yes" >> $config_mak |
|
1617 | 1614 |
echo "#define TARGET_ARCH \"ppcemb\"" >> $config_h |
1618 | 1615 |
echo "#define TARGET_PPC 1" >> $config_h |
1619 | 1616 |
echo "#define TARGET_PPCEMB 1" >> $config_h |
1620 |
echo "#define CONFIG_DYNGEN_OP 1" >> $config_h |
|
1621 | 1617 |
;; |
1622 | 1618 |
ppc64) |
1623 | 1619 |
echo "TARGET_ARCH=ppc64" >> $config_mak |
1624 | 1620 |
echo "TARGET_ABI_DIR=ppc" >> $config_mak |
1625 |
echo "CONFIG_DYNGEN_OP=yes" >> $config_mak |
|
1626 | 1621 |
echo "#define TARGET_ARCH \"ppc64\"" >> $config_h |
1627 | 1622 |
echo "#define TARGET_PPC 1" >> $config_h |
1628 | 1623 |
echo "#define TARGET_PPC64 1" >> $config_h |
1629 |
echo "#define CONFIG_DYNGEN_OP 1" >> $config_h |
|
1630 | 1624 |
;; |
1631 | 1625 |
ppc64abi32) |
1632 | 1626 |
echo "TARGET_ARCH=ppc64" >> $config_mak |
1633 | 1627 |
echo "TARGET_ABI_DIR=ppc" >> $config_mak |
1634 | 1628 |
echo "TARGET_ARCH2=ppc64abi32" >> $config_mak |
1635 |
echo "CONFIG_DYNGEN_OP=yes" >> $config_mak |
|
1636 | 1629 |
echo "#define TARGET_ARCH \"ppc64\"" >> $config_h |
1637 | 1630 |
echo "#define TARGET_PPC 1" >> $config_h |
1638 | 1631 |
echo "#define TARGET_PPC64 1" >> $config_h |
1639 | 1632 |
echo "#define TARGET_ABI32 1" >> $config_h |
1640 |
echo "#define CONFIG_DYNGEN_OP 1" >> $config_h |
|
1641 | 1633 |
;; |
1642 | 1634 |
sh4|sh4eb) |
1643 | 1635 |
echo "TARGET_ARCH=sh4" >> $config_mak |
b/target-ppc/cpu.h | ||
---|---|---|
295 | 295 |
|
296 | 296 |
/* SPR access micro-ops generations callbacks */ |
297 | 297 |
struct ppc_spr_t { |
298 |
void (*uea_read)(void *opaque, int spr_num); |
|
299 |
void (*uea_write)(void *opaque, int spr_num); |
|
298 |
void (*uea_read)(void *opaque, int gpr_num, int spr_num);
|
|
299 |
void (*uea_write)(void *opaque, int spr_num, int gpr_num);
|
|
300 | 300 |
#if !defined(CONFIG_USER_ONLY) |
301 |
void (*oea_read)(void *opaque, int spr_num); |
|
302 |
void (*oea_write)(void *opaque, int spr_num); |
|
303 |
void (*hea_read)(void *opaque, int spr_num); |
|
304 |
void (*hea_write)(void *opaque, int spr_num); |
|
301 |
void (*oea_read)(void *opaque, int gpr_num, int spr_num);
|
|
302 |
void (*oea_write)(void *opaque, int spr_num, int gpr_num);
|
|
303 |
void (*hea_read)(void *opaque, int gpr_num, int spr_num);
|
|
304 |
void (*hea_write)(void *opaque, int spr_num, int gpr_num);
|
|
305 | 305 |
#endif |
306 | 306 |
const char *name; |
307 | 307 |
}; |
... | ... | |
529 | 529 |
/* First are the most commonly used resources |
530 | 530 |
* during translated code execution |
531 | 531 |
*/ |
532 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
533 |
target_ulong t0; |
|
534 |
#endif |
|
535 |
|
|
536 | 532 |
/* general purpose registers */ |
537 | 533 |
target_ulong gpr[32]; |
538 | 534 |
#if !defined(TARGET_PPC64) |
... | ... | |
689 | 685 |
void dump_stack (CPUPPCState *env); |
690 | 686 |
|
691 | 687 |
#if !defined(CONFIG_USER_ONLY) |
692 |
target_ulong do_load_ibatu (CPUPPCState *env, int nr); |
|
693 |
target_ulong do_load_ibatl (CPUPPCState *env, int nr); |
|
694 |
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
|
695 |
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
|
696 |
target_ulong do_load_dbatu (CPUPPCState *env, int nr); |
|
697 |
target_ulong do_load_dbatl (CPUPPCState *env, int nr); |
|
698 |
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
|
699 |
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
|
700 |
void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value); |
|
701 |
void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value); |
|
702 |
target_ulong do_load_sdr1 (CPUPPCState *env); |
|
703 |
void do_store_sdr1 (CPUPPCState *env, target_ulong value); |
|
688 |
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
|
689 |
void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
|
690 |
void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
|
691 |
void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
|
692 |
void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value); |
|
693 |
void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value); |
|
694 |
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); |
|
704 | 695 |
#if defined(TARGET_PPC64) |
705 |
target_ulong ppc_load_asr (CPUPPCState *env); |
|
706 | 696 |
void ppc_store_asr (CPUPPCState *env, target_ulong value); |
707 | 697 |
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr); |
708 | 698 |
void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs); |
709 | 699 |
#endif /* defined(TARGET_PPC64) */ |
710 |
#if 0 // Unused |
|
711 |
target_ulong do_load_sr (CPUPPCState *env, int srnum); |
|
712 |
#endif |
|
713 |
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
|
700 |
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
|
714 | 701 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
715 | 702 |
void ppc_store_msr (CPUPPCState *env, target_ulong value); |
716 | 703 |
|
b/target-ppc/exec.h | ||
---|---|---|
32 | 32 |
#define USE_PRECISE_EMULATION 0 |
33 | 33 |
|
34 | 34 |
register struct CPUPPCState *env asm(AREG0); |
35 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
36 |
/* no registers can be used */ |
|
37 |
#define T0 (env->t0) |
|
38 | 35 |
#define TDX "%016" PRIx64 |
39 |
#else |
|
40 |
register target_ulong T0 asm(AREG1); |
|
41 |
#define TDX "%016lx" |
|
42 |
#endif |
|
43 |
|
|
44 |
#if defined (DEBUG_OP) |
|
45 |
# define RETURN() __asm__ __volatile__("nop" : : : "memory"); |
|
46 |
#else |
|
47 |
# define RETURN() __asm__ __volatile__("" : : : "memory"); |
|
48 |
#endif |
|
49 | 36 |
|
50 | 37 |
#if !defined(CONFIG_USER_ONLY) |
51 | 38 |
#include "softmmu_exec.h" |
b/target-ppc/helper.c | ||
---|---|---|
1800 | 1800 |
#endif |
1801 | 1801 |
} |
1802 | 1802 |
|
1803 |
target_ulong do_load_ibatu (CPUPPCState *env, int nr) |
|
1804 |
{ |
|
1805 |
return env->IBAT[0][nr]; |
|
1806 |
} |
|
1807 |
|
|
1808 |
target_ulong do_load_ibatl (CPUPPCState *env, int nr) |
|
1809 |
{ |
|
1810 |
return env->IBAT[1][nr]; |
|
1811 |
} |
|
1812 |
|
|
1813 |
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
|
1803 |
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
|
1814 | 1804 |
{ |
1815 | 1805 |
target_ulong mask; |
1816 | 1806 |
|
... | ... | |
1836 | 1826 |
} |
1837 | 1827 |
} |
1838 | 1828 |
|
1839 |
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
|
|
1829 |
void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
|
|
1840 | 1830 |
{ |
1841 | 1831 |
dump_store_bat(env, 'I', 1, nr, value); |
1842 | 1832 |
env->IBAT[1][nr] = value; |
1843 | 1833 |
} |
1844 | 1834 |
|
1845 |
target_ulong do_load_dbatu (CPUPPCState *env, int nr) |
|
1846 |
{ |
|
1847 |
return env->DBAT[0][nr]; |
|
1848 |
} |
|
1849 |
|
|
1850 |
target_ulong do_load_dbatl (CPUPPCState *env, int nr) |
|
1851 |
{ |
|
1852 |
return env->DBAT[1][nr]; |
|
1853 |
} |
|
1854 |
|
|
1855 |
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
|
1835 |
void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
|
1856 | 1836 |
{ |
1857 | 1837 |
target_ulong mask; |
1858 | 1838 |
|
... | ... | |
1878 | 1858 |
} |
1879 | 1859 |
} |
1880 | 1860 |
|
1881 |
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
|
|
1861 |
void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
|
|
1882 | 1862 |
{ |
1883 | 1863 |
dump_store_bat(env, 'D', 1, nr, value); |
1884 | 1864 |
env->DBAT[1][nr] = value; |
1885 | 1865 |
} |
1886 | 1866 |
|
1887 |
void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
|
|
1867 |
void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
|
|
1888 | 1868 |
{ |
1889 | 1869 |
target_ulong mask; |
1890 | 1870 |
int do_inval; |
... | ... | |
1921 | 1901 |
} |
1922 | 1902 |
} |
1923 | 1903 |
|
1924 |
void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
|
|
1904 |
void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
|
|
1925 | 1905 |
{ |
1926 | 1906 |
target_ulong mask; |
1927 | 1907 |
int do_inval; |
... | ... | |
2075 | 2055 |
/*****************************************************************************/ |
2076 | 2056 |
/* Special registers manipulation */ |
2077 | 2057 |
#if defined(TARGET_PPC64) |
2078 |
target_ulong ppc_load_asr (CPUPPCState *env) |
|
2079 |
{ |
|
2080 |
return env->asr; |
|
2081 |
} |
|
2082 |
|
|
2083 | 2058 |
void ppc_store_asr (CPUPPCState *env, target_ulong value) |
2084 | 2059 |
{ |
2085 | 2060 |
if (env->asr != value) { |
... | ... | |
2089 | 2064 |
} |
2090 | 2065 |
#endif |
2091 | 2066 |
|
2092 |
target_ulong do_load_sdr1 (CPUPPCState *env) |
|
2093 |
{ |
|
2094 |
return env->sdr1; |
|
2095 |
} |
|
2096 |
|
|
2097 |
void do_store_sdr1 (CPUPPCState *env, target_ulong value) |
|
2067 |
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value) |
|
2098 | 2068 |
{ |
2099 | 2069 |
#if defined (DEBUG_MMU) |
2100 | 2070 |
if (loglevel != 0) { |
... | ... | |
2110 | 2080 |
} |
2111 | 2081 |
} |
2112 | 2082 |
|
2113 |
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
|
|
2083 |
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
|
|
2114 | 2084 |
{ |
2115 | 2085 |
#if defined (DEBUG_MMU) |
2116 | 2086 |
if (loglevel != 0) { |
b/target-ppc/helper.h | ||
---|---|---|
184 | 184 |
DEF_HELPER_1(slbie, void, tl) |
185 | 185 |
#endif |
186 | 186 |
DEF_HELPER_1(load_sr, tl, tl); |
187 |
DEF_HELPER_2(store_sr, void, tl, tl);
|
|
187 |
DEF_HELPER_2(store_sr, void, tl, tl) |
|
188 | 188 |
|
189 | 189 |
DEF_HELPER_1(602_mfrom, tl, tl) |
190 | 190 |
#endif |
... | ... | |
200 | 200 |
DEF_HELPER_2(divso, tl, tl, tl) |
201 | 201 |
|
202 | 202 |
DEF_HELPER_1(load_dcr, tl, tl); |
203 |
DEF_HELPER_2(store_dcr, void, tl, tl); |
|
203 |
DEF_HELPER_2(store_dcr, void, tl, tl) |
|
204 |
|
|
205 |
DEF_HELPER_1(load_dump_spr, void, i32) |
|
206 |
DEF_HELPER_1(store_dump_spr, void, i32) |
|
207 |
DEF_HELPER_0(load_tbl, tl) |
|
208 |
DEF_HELPER_0(load_tbu, tl) |
|
209 |
DEF_HELPER_0(load_atbl, tl) |
|
210 |
DEF_HELPER_0(load_atbu, tl) |
|
211 |
DEF_HELPER_0(load_601_rtcl, tl) |
|
212 |
DEF_HELPER_0(load_601_rtcu, tl) |
|
213 |
#if !defined(CONFIG_USER_ONLY) |
|
214 |
#if defined(TARGET_PPC64) |
|
215 |
DEF_HELPER_1(store_asr, void, tl) |
|
216 |
#endif |
|
217 |
DEF_HELPER_1(store_sdr1, void, tl) |
|
218 |
DEF_HELPER_1(store_tbl, void, tl) |
|
219 |
DEF_HELPER_1(store_tbu, void, tl) |
|
220 |
DEF_HELPER_1(store_atbl, void, tl) |
|
221 |
DEF_HELPER_1(store_atbu, void, tl) |
|
222 |
DEF_HELPER_1(store_601_rtcl, void, tl) |
|
223 |
DEF_HELPER_1(store_601_rtcu, void, tl) |
|
224 |
DEF_HELPER_0(load_decr, tl) |
|
225 |
DEF_HELPER_1(store_decr, void, tl) |
|
226 |
DEF_HELPER_1(store_hid0_601, void, tl) |
|
227 |
DEF_HELPER_2(store_403_pbr, void, i32, tl) |
|
228 |
DEF_HELPER_0(load_40x_pit, tl) |
|
229 |
DEF_HELPER_1(store_40x_pit, void, tl) |
|
230 |
DEF_HELPER_1(store_40x_dbcr0, void, tl) |
|
231 |
DEF_HELPER_1(store_40x_sler, void, tl) |
|
232 |
DEF_HELPER_1(store_booke_tcr, void, tl) |
|
233 |
DEF_HELPER_1(store_booke_tsr, void, tl) |
|
234 |
DEF_HELPER_2(store_ibatl, void, i32, tl) |
|
235 |
DEF_HELPER_2(store_ibatu, void, i32, tl) |
|
236 |
DEF_HELPER_2(store_dbatl, void, i32, tl) |
|
237 |
DEF_HELPER_2(store_dbatu, void, i32, tl) |
|
238 |
DEF_HELPER_2(store_601_batl, void, i32, tl) |
|
239 |
DEF_HELPER_2(store_601_batu, void, i32, tl) |
|
240 |
#endif |
|
204 | 241 |
|
205 | 242 |
#include "def-helper.h" |
/dev/null | ||
---|---|---|
1 |
/* |
|
2 |
* PowerPC emulation micro-operations for qemu. |
|
3 |
* |
|
4 |
* Copyright (c) 2003-2007 Jocelyn Mayer |
|
5 |
* |
|
6 |
* This library is free software; you can redistribute it and/or |
|
7 |
* modify it under the terms of the GNU Lesser General Public |
|
8 |
* License as published by the Free Software Foundation; either |
|
9 |
* version 2 of the License, or (at your option) any later version. |
|
10 |
* |
|
11 |
* This library is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|
14 |
* Lesser General Public License for more details. |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU Lesser General Public |
|
17 |
* License along with this library; if not, write to the Free Software |
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 |
*/ |
|
20 |
|
|
21 |
//#define DEBUG_OP |
|
22 |
|
|
23 |
#include "config.h" |
|
24 |
#include "exec.h" |
|
25 |
#include "host-utils.h" |
|
26 |
#include "helper_regs.h" |
|
27 |
#include "op_helper.h" |
|
28 |
|
|
29 |
#if !defined(CONFIG_USER_ONLY) |
|
30 |
void OPPROTO op_load_sdr1 (void) |
|
31 |
{ |
|
32 |
T0 = env->sdr1; |
|
33 |
RETURN(); |
|
34 |
} |
|
35 |
|
|
36 |
void OPPROTO op_store_sdr1 (void) |
|
37 |
{ |
|
38 |
do_store_sdr1(env, T0); |
|
39 |
RETURN(); |
|
40 |
} |
|
41 |
|
|
42 |
#if defined (TARGET_PPC64) |
|
43 |
void OPPROTO op_load_asr (void) |
|
44 |
{ |
|
45 |
T0 = env->asr; |
|
46 |
RETURN(); |
|
47 |
} |
|
48 |
|
|
49 |
void OPPROTO op_store_asr (void) |
|
50 |
{ |
|
51 |
ppc_store_asr(env, T0); |
|
52 |
RETURN(); |
|
53 |
} |
|
54 |
#endif |
|
55 |
#endif |
|
56 |
|
|
57 |
/* SPR */ |
|
58 |
void OPPROTO op_load_spr (void) |
|
59 |
{ |
|
60 |
T0 = env->spr[PARAM1]; |
|
61 |
RETURN(); |
|
62 |
} |
|
63 |
|
|
64 |
void OPPROTO op_store_spr (void) |
|
65 |
{ |
|
66 |
env->spr[PARAM1] = T0; |
|
67 |
RETURN(); |
|
68 |
} |
|
69 |
|
|
70 |
void OPPROTO op_load_dump_spr (void) |
|
71 |
{ |
|
72 |
T0 = ppc_load_dump_spr(PARAM1); |
|
73 |
RETURN(); |
|
74 |
} |
|
75 |
|
|
76 |
void OPPROTO op_store_dump_spr (void) |
|
77 |
{ |
|
78 |
ppc_store_dump_spr(PARAM1, T0); |
|
79 |
RETURN(); |
|
80 |
} |
|
81 |
|
|
82 |
void OPPROTO op_mask_spr (void) |
|
83 |
{ |
|
84 |
env->spr[PARAM1] &= ~T0; |
|
85 |
RETURN(); |
|
86 |
} |
|
87 |
|
|
88 |
void OPPROTO op_load_tbl (void) |
|
89 |
{ |
|
90 |
T0 = cpu_ppc_load_tbl(env); |
|
91 |
RETURN(); |
|
92 |
} |
|
93 |
|
|
94 |
void OPPROTO op_load_tbu (void) |
|
95 |
{ |
|
96 |
T0 = cpu_ppc_load_tbu(env); |
|
97 |
RETURN(); |
|
98 |
} |
|
99 |
|
|
100 |
void OPPROTO op_load_atbl (void) |
|
101 |
{ |
|
102 |
T0 = cpu_ppc_load_atbl(env); |
|
103 |
RETURN(); |
|
104 |
} |
|
105 |
|
|
106 |
void OPPROTO op_load_atbu (void) |
|
107 |
{ |
|
108 |
T0 = cpu_ppc_load_atbu(env); |
|
109 |
RETURN(); |
|
110 |
} |
|
111 |
|
|
112 |
#if !defined(CONFIG_USER_ONLY) |
|
113 |
void OPPROTO op_store_tbl (void) |
|
114 |
{ |
|
115 |
cpu_ppc_store_tbl(env, T0); |
|
116 |
RETURN(); |
|
117 |
} |
|
118 |
|
|
119 |
void OPPROTO op_store_tbu (void) |
|
120 |
{ |
|
121 |
cpu_ppc_store_tbu(env, T0); |
|
122 |
RETURN(); |
|
123 |
} |
|
124 |
|
|
125 |
void OPPROTO op_store_atbl (void) |
|
126 |
{ |
|
127 |
cpu_ppc_store_atbl(env, T0); |
|
128 |
RETURN(); |
|
129 |
} |
|
130 |
|
|
131 |
void OPPROTO op_store_atbu (void) |
|
132 |
{ |
|
133 |
cpu_ppc_store_atbu(env, T0); |
|
134 |
RETURN(); |
|
135 |
} |
|
136 |
|
|
137 |
void OPPROTO op_load_decr (void) |
|
138 |
{ |
|
139 |
T0 = cpu_ppc_load_decr(env); |
|
140 |
RETURN(); |
|
141 |
} |
|
142 |
|
|
143 |
void OPPROTO op_store_decr (void) |
|
144 |
{ |
|
145 |
cpu_ppc_store_decr(env, T0); |
|
146 |
RETURN(); |
|
147 |
} |
|
148 |
|
|
149 |
void OPPROTO op_load_ibat (void) |
|
150 |
{ |
|
151 |
T0 = env->IBAT[PARAM1][PARAM2]; |
|
152 |
RETURN(); |
|
153 |
} |
|
154 |
|
|
155 |
void OPPROTO op_store_ibatu (void) |
|
156 |
{ |
|
157 |
do_store_ibatu(env, PARAM1, T0); |
|
158 |
RETURN(); |
|
159 |
} |
|
160 |
|
|
161 |
void OPPROTO op_store_ibatl (void) |
|
162 |
{ |
|
163 |
#if 1 |
|
164 |
env->IBAT[1][PARAM1] = T0; |
|
165 |
#else |
|
166 |
do_store_ibatl(env, PARAM1, T0); |
|
167 |
#endif |
|
168 |
RETURN(); |
|
169 |
} |
|
170 |
|
|
171 |
void OPPROTO op_load_dbat (void) |
|
172 |
{ |
|
173 |
T0 = env->DBAT[PARAM1][PARAM2]; |
|
174 |
RETURN(); |
|
175 |
} |
|
176 |
|
|
177 |
void OPPROTO op_store_dbatu (void) |
|
178 |
{ |
|
179 |
do_store_dbatu(env, PARAM1, T0); |
|
180 |
RETURN(); |
|
181 |
} |
|
182 |
|
|
183 |
void OPPROTO op_store_dbatl (void) |
|
184 |
{ |
|
185 |
#if 1 |
|
186 |
env->DBAT[1][PARAM1] = T0; |
|
187 |
#else |
|
188 |
do_store_dbatl(env, PARAM1, T0); |
|
189 |
#endif |
|
190 |
RETURN(); |
|
191 |
} |
|
192 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
|
193 |
|
|
194 |
/* Return from interrupt */ |
|
195 |
#if !defined(CONFIG_USER_ONLY) |
|
196 |
/* Exception vectors */ |
|
197 |
void OPPROTO op_store_excp_prefix (void) |
|
198 |
{ |
|
199 |
T0 &= env->ivpr_mask; |
|
200 |
env->excp_prefix = T0; |
|
201 |
RETURN(); |
|
202 |
} |
|
203 |
|
|
204 |
void OPPROTO op_store_excp_vector (void) |
|
205 |
{ |
|
206 |
T0 &= env->ivor_mask; |
|
207 |
env->excp_vectors[PARAM1] = T0; |
|
208 |
RETURN(); |
|
209 |
} |
|
210 |
#endif |
|
211 |
|
|
212 |
/* 601 specific */ |
|
213 |
void OPPROTO op_load_601_rtcl (void) |
|
214 |
{ |
|
215 |
T0 = cpu_ppc601_load_rtcl(env); |
|
216 |
RETURN(); |
|
217 |
} |
|
218 |
|
|
219 |
void OPPROTO op_load_601_rtcu (void) |
|
220 |
{ |
|
221 |
T0 = cpu_ppc601_load_rtcu(env); |
|
222 |
RETURN(); |
|
223 |
} |
|
224 |
|
|
225 |
#if !defined(CONFIG_USER_ONLY) |
|
226 |
void OPPROTO op_store_601_rtcl (void) |
|
227 |
{ |
|
228 |
cpu_ppc601_store_rtcl(env, T0); |
|
229 |
RETURN(); |
|
230 |
} |
|
231 |
|
|
232 |
void OPPROTO op_store_601_rtcu (void) |
|
233 |
{ |
|
234 |
cpu_ppc601_store_rtcu(env, T0); |
|
235 |
RETURN(); |
|
236 |
} |
|
237 |
|
|
238 |
void OPPROTO op_store_hid0_601 (void) |
|
239 |
{ |
|
240 |
do_store_hid0_601(); |
|
241 |
RETURN(); |
|
242 |
} |
|
243 |
|
|
244 |
void OPPROTO op_load_601_bat (void) |
|
245 |
{ |
|
246 |
T0 = env->IBAT[PARAM1][PARAM2]; |
|
247 |
RETURN(); |
|
248 |
} |
|
249 |
|
|
250 |
void OPPROTO op_store_601_batl (void) |
|
251 |
{ |
|
252 |
do_store_ibatl_601(env, PARAM1, T0); |
|
253 |
RETURN(); |
|
254 |
} |
|
255 |
|
|
256 |
void OPPROTO op_store_601_batu (void) |
|
257 |
{ |
|
258 |
do_store_ibatu_601(env, PARAM1, T0); |
|
259 |
RETURN(); |
|
260 |
} |
|
261 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
|
262 |
|
|
263 |
/* SPR micro-ops */ |
|
264 |
/* 440 specific */ |
|
265 |
#if !defined(CONFIG_USER_ONLY) |
|
266 |
void OPPROTO op_store_pir (void) |
|
267 |
{ |
|
268 |
env->spr[SPR_PIR] = T0 & 0x0000000FUL; |
|
269 |
RETURN(); |
|
270 |
} |
|
271 |
|
|
272 |
void OPPROTO op_load_403_pb (void) |
|
273 |
{ |
|
274 |
do_load_403_pb(PARAM1); |
|
275 |
RETURN(); |
|
276 |
} |
|
277 |
|
|
278 |
void OPPROTO op_store_403_pb (void) |
|
279 |
{ |
|
280 |
do_store_403_pb(PARAM1); |
|
281 |
RETURN(); |
|
282 |
} |
|
283 |
|
|
284 |
void OPPROTO op_load_40x_pit (void) |
|
285 |
{ |
|
286 |
T0 = load_40x_pit(env); |
|
287 |
RETURN(); |
|
288 |
} |
|
289 |
|
|
290 |
void OPPROTO op_store_40x_pit (void) |
|
291 |
{ |
|
292 |
store_40x_pit(env, T0); |
|
293 |
RETURN(); |
|
294 |
} |
|
295 |
|
|
296 |
void OPPROTO op_store_40x_dbcr0 (void) |
|
297 |
{ |
|
298 |
store_40x_dbcr0(env, T0); |
|
299 |
RETURN(); |
|
300 |
} |
|
301 |
|
|
302 |
void OPPROTO op_store_40x_sler (void) |
|
303 |
{ |
|
304 |
store_40x_sler(env, T0); |
|
305 |
RETURN(); |
|
306 |
} |
|
307 |
|
|
308 |
void OPPROTO op_store_booke_tcr (void) |
|
309 |
{ |
|
310 |
store_booke_tcr(env, T0); |
|
311 |
RETURN(); |
|
312 |
} |
|
313 |
|
|
314 |
void OPPROTO op_store_booke_tsr (void) |
|
315 |
{ |
|
316 |
store_booke_tsr(env, T0); |
|
317 |
RETURN(); |
|
318 |
} |
|
319 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
|
320 |
|
b/target-ppc/op_helper.c | ||
---|---|---|
22 | 22 |
#include "helper.h" |
23 | 23 |
|
24 | 24 |
#include "helper_regs.h" |
25 |
#include "op_helper.h" |
|
26 | 25 |
|
27 | 26 |
//#define DEBUG_OP |
28 | 27 |
//#define DEBUG_EXCEPTIONS |
... | ... | |
65 | 64 |
} |
66 | 65 |
} |
67 | 66 |
|
68 |
target_ulong ppc_load_dump_spr (int sprn) |
|
67 |
/*****************************************************************************/ |
|
68 |
/* SPR accesses */ |
|
69 |
void helper_load_dump_spr (uint32_t sprn) |
|
69 | 70 |
{ |
70 | 71 |
if (loglevel != 0) { |
71 | 72 |
fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n", |
72 | 73 |
sprn, sprn, env->spr[sprn]); |
73 | 74 |
} |
74 |
|
|
75 |
return env->spr[sprn]; |
|
76 | 75 |
} |
77 | 76 |
|
78 |
void ppc_store_dump_spr (int sprn, target_ulong val)
|
|
77 |
void helper_store_dump_spr (uint32_t sprn)
|
|
79 | 78 |
{ |
80 | 79 |
if (loglevel != 0) { |
81 |
fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n", |
|
82 |
sprn, sprn, env->spr[sprn], val); |
|
80 |
fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n", |
|
81 |
sprn, sprn, env->spr[sprn]); |
|
82 |
} |
|
83 |
} |
|
84 |
|
|
85 |
target_ulong helper_load_tbl (void) |
|
86 |
{ |
|
87 |
return cpu_ppc_load_tbl(env); |
|
88 |
} |
|
89 |
|
|
90 |
target_ulong helper_load_tbu (void) |
|
91 |
{ |
|
92 |
return cpu_ppc_load_tbu(env); |
|
93 |
} |
|
94 |
|
|
95 |
target_ulong helper_load_atbl (void) |
|
96 |
{ |
|
97 |
return cpu_ppc_load_atbl(env); |
|
98 |
} |
|
99 |
|
|
100 |
target_ulong helper_load_atbu (void) |
|
101 |
{ |
|
102 |
return cpu_ppc_load_atbu(env); |
|
103 |
} |
|
104 |
|
|
105 |
target_ulong helper_load_601_rtcl (void) |
|
106 |
{ |
|
107 |
return cpu_ppc601_load_rtcl(env); |
|
108 |
} |
|
109 |
|
|
110 |
target_ulong helper_load_601_rtcu (void) |
|
111 |
{ |
|
112 |
return cpu_ppc601_load_rtcu(env); |
|
113 |
} |
|
114 |
|
|
115 |
#if !defined(CONFIG_USER_ONLY) |
|
116 |
#if defined (TARGET_PPC64) |
|
117 |
void helper_store_asr (target_ulong val) |
|
118 |
{ |
|
119 |
ppc_store_asr(env, val); |
|
120 |
} |
|
121 |
#endif |
|
122 |
|
|
123 |
void helper_store_sdr1 (target_ulong val) |
|
124 |
{ |
|
125 |
ppc_store_sdr1(env, val); |
|
126 |
} |
|
127 |
|
|
128 |
void helper_store_tbl (target_ulong val) |
|
129 |
{ |
|
130 |
cpu_ppc_store_tbl(env, val); |
|
131 |
} |
|
132 |
|
|
133 |
void helper_store_tbu (target_ulong val) |
|
134 |
{ |
|
135 |
cpu_ppc_store_tbu(env, val); |
|
136 |
} |
|
137 |
|
|
138 |
void helper_store_atbl (target_ulong val) |
|
139 |
{ |
|
140 |
cpu_ppc_store_atbl(env, val); |
|
141 |
} |
|
142 |
|
|
143 |
void helper_store_atbu (target_ulong val) |
|
144 |
{ |
|
145 |
cpu_ppc_store_atbu(env, val); |
|
146 |
} |
|
147 |
|
|
148 |
void helper_store_601_rtcl (target_ulong val) |
|
149 |
{ |
|
150 |
cpu_ppc601_store_rtcl(env, val); |
|
151 |
} |
|
152 |
|
|
153 |
void helper_store_601_rtcu (target_ulong val) |
|
154 |
{ |
|
155 |
cpu_ppc601_store_rtcu(env, val); |
|
156 |
} |
|
157 |
|
|
158 |
target_ulong helper_load_decr (void) |
|
159 |
{ |
|
160 |
return cpu_ppc_load_decr(env); |
|
161 |
} |
|
162 |
|
|
163 |
void helper_store_decr (target_ulong val) |
|
164 |
{ |
|
165 |
cpu_ppc_store_decr(env, val); |
|
166 |
} |
|
167 |
|
|
168 |
void helper_store_hid0_601 (target_ulong val) |
|
169 |
{ |
|
170 |
target_ulong hid0; |
|
171 |
|
|
172 |
hid0 = env->spr[SPR_HID0]; |
|
173 |
if ((val ^ hid0) & 0x00000008) { |
|
174 |
/* Change current endianness */ |
|
175 |
env->hflags &= ~(1 << MSR_LE); |
|
176 |
env->hflags_nmsr &= ~(1 << MSR_LE); |
|
177 |
env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); |
|
178 |
env->hflags |= env->hflags_nmsr; |
|
179 |
if (loglevel != 0) { |
|
180 |
fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n", |
|
181 |
__func__, val & 0x8 ? 'l' : 'b', env->hflags); |
|
182 |
} |
|
83 | 183 |
} |
84 |
env->spr[sprn] = val; |
|
184 |
env->spr[SPR_HID0] = (uint32_t)val; |
|
185 |
} |
|
186 |
|
|
187 |
void helper_store_403_pbr (uint32_t num, target_ulong value) |
|
188 |
{ |
|
189 |
if (likely(env->pb[num] != value)) { |
|
190 |
env->pb[num] = value; |
|
191 |
/* Should be optimized */ |
|
192 |
tlb_flush(env, 1); |
|
193 |
} |
|
194 |
} |
|
195 |
|
|
196 |
target_ulong helper_load_40x_pit (void) |
|
197 |
{ |
|
198 |
return load_40x_pit(env); |
|
199 |
} |
|
200 |
|
|
201 |
void helper_store_40x_pit (target_ulong val) |
|
202 |
{ |
|
203 |
store_40x_pit(env, val); |
|
204 |
} |
|
205 |
|
|
206 |
void helper_store_40x_dbcr0 (target_ulong val) |
|
207 |
{ |
|
208 |
store_40x_dbcr0(env, val); |
|
209 |
} |
|
210 |
|
|
211 |
void helper_store_40x_sler (target_ulong val) |
|
212 |
{ |
|
213 |
store_40x_sler(env, val); |
|
214 |
} |
|
215 |
|
|
216 |
void helper_store_booke_tcr (target_ulong val) |
|
217 |
{ |
|
218 |
store_booke_tcr(env, val); |
|
219 |
} |
|
220 |
|
|
221 |
void helper_store_booke_tsr (target_ulong val) |
|
222 |
{ |
|
223 |
store_booke_tsr(env, val); |
|
224 |
} |
|
225 |
|
|
226 |
void helper_store_ibatu (uint32_t nr, target_ulong val) |
|
227 |
{ |
|
228 |
ppc_store_ibatu(env, nr, val); |
|
229 |
} |
|
230 |
|
|
231 |
void helper_store_ibatl (uint32_t nr, target_ulong val) |
|
232 |
{ |
|
233 |
ppc_store_ibatl(env, nr, val); |
|
234 |
} |
|
235 |
|
|
236 |
void helper_store_dbatu (uint32_t nr, target_ulong val) |
|
237 |
{ |
|
238 |
ppc_store_dbatu(env, nr, val); |
|
85 | 239 |
} |
86 | 240 |
|
241 |
void helper_store_dbatl (uint32_t nr, target_ulong val) |
|
242 |
{ |
|
243 |
ppc_store_dbatl(env, nr, val); |
|
244 |
} |
|
245 |
|
|
246 |
void helper_store_601_batl (uint32_t nr, target_ulong val) |
|
247 |
{ |
|
248 |
ppc_store_ibatl_601(env, nr, val); |
|
249 |
} |
|
250 |
|
|
251 |
void helper_store_601_batu (uint32_t nr, target_ulong val) |
|
252 |
{ |
|
253 |
ppc_store_ibatu_601(env, nr, val); |
|
254 |
} |
|
255 |
#endif |
|
256 |
|
|
87 | 257 |
/*****************************************************************************/ |
88 | 258 |
/* Memory load and stores */ |
89 | 259 |
|
... | ... | |
1678 | 1848 |
{ |
1679 | 1849 |
do_rfi(env->lr, env->ctr, 0x0000FFFF, 0); |
1680 | 1850 |
} |
1681 |
|
|
1682 |
void do_store_hid0_601 (void) |
|
1683 |
{ |
|
1684 |
uint32_t hid0; |
|
1685 |
|
|
1686 |
hid0 = env->spr[SPR_HID0]; |
|
1687 |
if ((T0 ^ hid0) & 0x00000008) { |
|
1688 |
/* Change current endianness */ |
|
1689 |
env->hflags &= ~(1 << MSR_LE); |
|
1690 |
env->hflags_nmsr &= ~(1 << MSR_LE); |
|
1691 |
env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE); |
|
1692 |
env->hflags |= env->hflags_nmsr; |
|
1693 |
if (loglevel != 0) { |
|
1694 |
fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n", |
|
1695 |
__func__, T0 & 0x8 ? 'l' : 'b', env->hflags); |
|
1696 |
} |
|
1697 |
} |
|
1698 |
env->spr[SPR_HID0] = T0; |
|
1699 |
} |
|
1700 | 1851 |
#endif |
1701 | 1852 |
|
1702 | 1853 |
/*****************************************************************************/ |
... | ... | |
1709 | 1860 |
if (likely(arg < 602)) { |
1710 | 1861 |
#if defined(USE_MFROM_ROM_TABLE) |
1711 | 1862 |
#include "mfrom_table.c" |
1712 |
return mfrom_ROM_table[T0];
|
|
1863 |
return mfrom_ROM_table[arg];
|
|
1713 | 1864 |
#else |
1714 | 1865 |
double d; |
1715 | 1866 |
/* Extremly decomposed: |
... | ... | |
1747 | 1898 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
1748 | 1899 |
} else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) { |
1749 | 1900 |
if (loglevel != 0) { |
1750 |
fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
|
|
1901 |
fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
|
|
1751 | 1902 |
} |
1752 | 1903 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
1753 | 1904 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
... | ... | |
1765 | 1916 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
1766 | 1917 |
} else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) { |
1767 | 1918 |
if (loglevel != 0) { |
1768 |
fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
|
|
1919 |
fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
|
|
1769 | 1920 |
} |
1770 | 1921 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
1771 | 1922 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
... | ... | |
1796 | 1947 |
do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1, |
1797 | 1948 |
~((target_ulong)0x3FFF0000), 0); |
1798 | 1949 |
} |
1799 |
|
|
1800 |
void do_load_403_pb (int num) |
|
1801 |
{ |
|
1802 |
T0 = env->pb[num]; |
|
1803 |
} |
|
1804 |
|
|
1805 |
void do_store_403_pb (int num) |
|
1806 |
{ |
|
1807 |
if (likely(env->pb[num] != T0)) { |
|
1808 |
env->pb[num] = T0; |
|
1809 |
/* Should be optimized */ |
|
1810 |
tlb_flush(env, 1); |
|
1811 |
} |
|
1812 |
} |
|
1813 | 1950 |
#endif |
1814 | 1951 |
|
1815 | 1952 |
/* 440 specific */ |
... | ... | |
2539 | 2676 |
|
2540 | 2677 |
void helper_store_sr (target_ulong sr_num, target_ulong val) |
2541 | 2678 |
{ |
2542 |
do_store_sr(env, sr_num, val);
|
|
2679 |
ppc_store_sr(env, sr_num, val);
|
|
2543 | 2680 |
} |
2544 | 2681 |
|
2545 | 2682 |
/* SLB management */ |
/dev/null | ||
---|---|---|
1 |
/* |
|
2 |
* PowerPC emulation helpers header for qemu. |
|
3 |
* |
|
4 |
* Copyright (c) 2003-2007 Jocelyn Mayer |
|
5 |
* |
|
6 |
* This library is free software; you can redistribute it and/or |
|
7 |
* modify it under the terms of the GNU Lesser General Public |
|
8 |
* License as published by the Free Software Foundation; either |
|
9 |
* version 2 of the License, or (at your option) any later version. |
|
10 |
* |
|
11 |
* This library is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|
14 |
* Lesser General Public License for more details. |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU Lesser General Public |
|
17 |
* License along with this library; if not, write to the Free Software |
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 |
*/ |
|
20 |
|
|
21 |
/* Registers load and stores */ |
|
22 |
#if defined(TARGET_PPC64) |
|
23 |
void do_store_pri (int prio); |
|
24 |
#endif |
|
25 |
target_ulong ppc_load_dump_spr (int sprn); |
|
26 |
void ppc_store_dump_spr (int sprn, target_ulong val); |
|
27 |
|
|
28 |
/* Misc */ |
|
29 |
/* POWER / PowerPC 601 specific helpers */ |
|
30 |
#if !defined(CONFIG_USER_ONLY) |
|
31 |
void do_store_hid0_601 (void); |
|
32 |
#endif |
|
33 |
|
|
34 |
/* PowerPC 403 specific helpers */ |
|
35 |
#if !defined(CONFIG_USER_ONLY) |
|
36 |
void do_load_403_pb (int num); |
|
37 |
void do_store_403_pb (int num); |
|
38 |
#endif |
b/target-ppc/translate.c | ||
---|---|---|
38 | 38 |
#define GDBSTUB_SINGLE_STEP 0x4 |
39 | 39 |
|
40 | 40 |
/* Include definitions for instructions classes and implementations flags */ |
41 |
//#define DO_SINGLE_STEP
|
|
41 |
#define DO_SINGLE_STEP |
|
42 | 42 |
//#define PPC_DEBUG_DISAS |
43 | 43 |
//#define DO_PPC_STATISTICS |
44 | 44 |
//#define OPTIMIZE_FPRF_UPDATE |
... | ... | |
71 | 71 |
static TCGv_i32 cpu_fpscr; |
72 | 72 |
static TCGv_i32 cpu_access_type; |
73 | 73 |
|
74 |
/* dyngen register indexes */ |
|
75 |
static TCGv cpu_T[1]; |
|
76 |
|
|
77 | 74 |
#include "gen-icount.h" |
78 | 75 |
|
79 | 76 |
void ppc_translate_init(void) |
... | ... | |
86 | 83 |
return; |
87 | 84 |
|
88 | 85 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
89 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
90 |
cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0"); |
|
91 |
#else |
|
92 |
cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0"); |
|
93 |
#endif |
|
94 | 86 |
|
95 | 87 |
p = cpu_reg_names; |
96 | 88 |
|
... | ... | |
3886 | 3878 |
/* mfspr */ |
3887 | 3879 |
static always_inline void gen_op_mfspr (DisasContext *ctx) |
3888 | 3880 |
{ |
3889 |
void (*read_cb)(void *opaque, int sprn); |
|
3881 |
void (*read_cb)(void *opaque, int gprn, int sprn);
|
|
3890 | 3882 |
uint32_t sprn = SPR(ctx->opcode); |
3891 | 3883 |
|
3892 | 3884 |
#if !defined(CONFIG_USER_ONLY) |
... | ... | |
3899 | 3891 |
read_cb = ctx->spr_cb[sprn].uea_read; |
3900 | 3892 |
if (likely(read_cb != NULL)) { |
3901 | 3893 |
if (likely(read_cb != SPR_NOACCESS)) { |
3902 |
(*read_cb)(ctx, sprn); |
|
3903 |
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); |
|
3894 |
(*read_cb)(ctx, rD(ctx->opcode), sprn); |
|
3904 | 3895 |
} else { |
3905 | 3896 |
/* Privilege exception */ |
3906 | 3897 |
/* This is a hack to avoid warnings when running Linux: |
... | ... | |
3972 | 3963 |
GEN_EXCP_PRIVREG(ctx); |
3973 | 3964 |
return; |
3974 | 3965 |
} |
3975 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
|
3976 | 3966 |
if (ctx->opcode & 0x00010000) { |
3977 | 3967 |
/* Special form that does not need any synchronisation */ |
3978 | 3968 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
4004 | 3994 |
GEN_EXCP_PRIVREG(ctx); |
4005 | 3995 |
return; |
4006 | 3996 |
} |
4007 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
|
4008 | 3997 |
if (ctx->opcode & 0x00010000) { |
4009 | 3998 |
/* Special form that does not need any synchronisation */ |
4010 | 3999 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
4041 | 4030 |
/* mtspr */ |
4042 | 4031 |
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
4043 | 4032 |
{ |
4044 |
void (*write_cb)(void *opaque, int sprn); |
|
4033 |
void (*write_cb)(void *opaque, int sprn, int gprn);
|
|
4045 | 4034 |
uint32_t sprn = SPR(ctx->opcode); |
4046 | 4035 |
|
4047 | 4036 |
#if !defined(CONFIG_USER_ONLY) |
... | ... | |
4054 | 4043 |
write_cb = ctx->spr_cb[sprn].uea_write; |
4055 | 4044 |
if (likely(write_cb != NULL)) { |
4056 | 4045 |
if (likely(write_cb != SPR_NOACCESS)) { |
4057 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); |
|
4058 |
(*write_cb)(ctx, sprn); |
|
4046 |
(*write_cb)(ctx, sprn, rS(ctx->opcode)); |
|
4059 | 4047 |
} else { |
4060 | 4048 |
/* Privilege exception */ |
4061 | 4049 |
if (loglevel != 0) { |
b/target-ppc/translate_init.c | ||
---|---|---|
66 | 66 |
/* Generic callbacks: |
67 | 67 |
* do nothing but store/retrieve spr value |
68 | 68 |
*/ |
69 |
#ifdef PPC_DUMP_SPR_ACCESSES |
|
70 |
static void spr_read_generic (void *opaque, int sprn) |
|
71 |
{ |
|
72 |
gen_op_load_dump_spr(sprn); |
|
73 |
} |
|
74 |
|
|
75 |
static void spr_write_generic (void *opaque, int sprn) |
|
69 |
static void spr_read_generic (void *opaque, int gprn, int sprn) |
|
76 | 70 |
{ |
77 |
gen_op_store_dump_spr(sprn); |
|
78 |
} |
|
79 |
#else |
|
80 |
static void spr_read_generic (void *opaque, int sprn) |
|
81 |
{ |
|
82 |
gen_op_load_spr(sprn); |
|
71 |
gen_load_spr(cpu_gpr[gprn], sprn); |
|
72 |
#ifdef PPC_DUMP_SPR_ACCESSES |
|
73 |
{ |
|
74 |
TCGv t0 = tcg_const_i32(sprn); |
|
75 |
gen_helper_load_dump_spr(t0); |
|
76 |
tcg_temp_free_i32(t0); |
|
77 |
} |
|
78 |
#endif |
|
83 | 79 |
} |
84 | 80 |
|
85 |
static void spr_write_generic (void *opaque, int sprn) |
|
81 |
static void spr_write_generic (void *opaque, int sprn, int gprn)
|
|
86 | 82 |
{ |
87 |
gen_op_store_spr(sprn); |
|
88 |
} |
|
83 |
gen_store_spr(sprn, cpu_gpr[gprn]); |
|
84 |
#ifdef PPC_DUMP_SPR_ACCESSES |
|
85 |
{ |
|
86 |
TCGv t0 = tcg_const_i32(sprn); |
|
87 |
gen_helper_store_dump_spr(t0); |
|
88 |
tcg_temp_free_i32(t0); |
|
89 |
} |
|
89 | 90 |
#endif |
91 |
} |
|
90 | 92 |
|
91 | 93 |
#if !defined(CONFIG_USER_ONLY) |
92 |
static void spr_write_clear (void *opaque, int sprn) |
|
94 |
static void spr_write_clear (void *opaque, int sprn, int gprn)
|
|
93 | 95 |
{ |
94 |
gen_op_mask_spr(sprn); |
|
96 |
TCGv t0 = tcg_temp_new(); |
|
97 |
TCGv t1 = tcg_temp_new(); |
|
98 |
gen_load_spr(t0, sprn); |
|
99 |
tcg_gen_neg_tl(t1, cpu_gpr[gprn]); |
|
100 |
tcg_gen_and_tl(t0, t0, t1); |
|
101 |
gen_store_spr(sprn, t0); |
|
102 |
tcg_temp_free(t0); |
|
103 |
tcg_temp_free(t1); |
|
95 | 104 |
} |
96 | 105 |
#endif |
97 | 106 |
|
98 | 107 |
/* SPR common to all PowerPC */ |
99 | 108 |
/* XER */ |
100 |
static void spr_read_xer (void *opaque, int sprn) |
|
109 |
static void spr_read_xer (void *opaque, int gprn, int sprn)
|
|
101 | 110 |
{ |
102 |
tcg_gen_mov_tl(cpu_T[0], cpu_xer);
|
|
111 |
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
|
|
103 | 112 |
} |
104 | 113 |
|
105 |
static void spr_write_xer (void *opaque, int sprn) |
|
114 |
static void spr_write_xer (void *opaque, int sprn, int gprn)
|
|
106 | 115 |
{ |
107 |
tcg_gen_mov_tl(cpu_xer, cpu_T[0]);
|
|
116 |
tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
|
|
108 | 117 |
} |
109 | 118 |
|
110 | 119 |
/* LR */ |
111 |
static void spr_read_lr (void *opaque, int sprn) |
|
120 |
static void spr_read_lr (void *opaque, int gprn, int sprn)
|
|
112 | 121 |
{ |
113 |
tcg_gen_mov_tl(cpu_T[0], cpu_lr);
|
|
122 |
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
|
|
114 | 123 |
} |
115 | 124 |
|
116 |
static void spr_write_lr (void *opaque, int sprn) |
|
125 |
static void spr_write_lr (void *opaque, int sprn, int gprn)
|
|
117 | 126 |
{ |
118 |
tcg_gen_mov_tl(cpu_lr, cpu_T[0]);
|
|
127 |
tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
|
|
119 | 128 |
} |
120 | 129 |
|
121 | 130 |
/* CTR */ |
122 |
static void spr_read_ctr (void *opaque, int sprn) |
|
131 |
static void spr_read_ctr (void *opaque, int gprn, int sprn)
|
|
123 | 132 |
{ |
124 |
tcg_gen_mov_tl(cpu_T[0], cpu_ctr);
|
|
133 |
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
|
|
125 | 134 |
} |
126 | 135 |
|
127 |
static void spr_write_ctr (void *opaque, int sprn) |
|
136 |
static void spr_write_ctr (void *opaque, int sprn, int gprn)
|
|
128 | 137 |
{ |
129 |
tcg_gen_mov_tl(cpu_ctr, cpu_T[0]);
|
|
138 |
tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
|
|
130 | 139 |
} |
131 | 140 |
|
132 | 141 |
/* User read access to SPR */ |
... | ... | |
135 | 144 |
/* UPMCx */ |
136 | 145 |
/* USIA */ |
137 | 146 |
/* UDECR */ |
138 |
static void spr_read_ureg (void *opaque, int sprn) |
|
147 |
static void spr_read_ureg (void *opaque, int gprn, int sprn)
|
|
139 | 148 |
{ |
140 |
gen_op_load_spr(sprn + 0x10);
|
|
149 |
gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
|
|
141 | 150 |
} |
142 | 151 |
|
143 | 152 |
/* SPR common to all non-embedded PowerPC */ |
144 | 153 |
/* DECR */ |
145 | 154 |
#if !defined(CONFIG_USER_ONLY) |
146 |
static void spr_read_decr (void *opaque, int sprn) |
|
155 |
static void spr_read_decr (void *opaque, int gprn, int sprn)
|
|
147 | 156 |
{ |
148 |
gen_op_load_decr();
|
|
157 |
gen_helper_load_decr(cpu_gpr[gprn]);
|
|
149 | 158 |
} |
150 | 159 |
|
151 |
static void spr_write_decr (void *opaque, int sprn) |
|
160 |
static void spr_write_decr (void *opaque, int sprn, int gprn)
|
|
152 | 161 |
{ |
153 |
gen_op_store_decr();
|
|
162 |
gen_helper_store_decr(cpu_gpr[gprn]);
|
|
154 | 163 |
} |
155 | 164 |
#endif |
156 | 165 |
|
157 | 166 |
/* SPR common to all non-embedded PowerPC, except 601 */ |
158 | 167 |
/* Time base */ |
159 |
static void spr_read_tbl (void *opaque, int sprn) |
|
168 |
static void spr_read_tbl (void *opaque, int gprn, int sprn)
|
|
160 | 169 |
{ |
161 |
gen_op_load_tbl();
|
|
170 |
gen_helper_load_tbl(cpu_gpr[gprn]);
|
|
162 | 171 |
} |
163 | 172 |
|
164 |
static void spr_read_tbu (void *opaque, int sprn) |
|
173 |
static void spr_read_tbu (void *opaque, int gprn, int sprn)
|
|
165 | 174 |
{ |
166 |
gen_op_load_tbu();
|
|
175 |
gen_helper_load_tbu(cpu_gpr[gprn]);
|
|
167 | 176 |
} |
168 | 177 |
|
169 | 178 |
__attribute__ (( unused )) |
170 |
static void spr_read_atbl (void *opaque, int sprn) |
|
179 |
static void spr_read_atbl (void *opaque, int gprn, int sprn)
|
|
171 | 180 |
{ |
172 |
gen_op_load_atbl();
|
|
181 |
gen_helper_load_atbl(cpu_gpr[gprn]);
|
|
173 | 182 |
} |
174 | 183 |
|
175 | 184 |
__attribute__ (( unused )) |
176 |
static void spr_read_atbu (void *opaque, int sprn) |
|
185 |
static void spr_read_atbu (void *opaque, int gprn, int sprn)
|
|
177 | 186 |
{ |
178 |
gen_op_load_atbu();
|
|
187 |
gen_helper_load_atbu(cpu_gpr[gprn]);
|
|
179 | 188 |
} |
180 | 189 |
|
181 | 190 |
#if !defined(CONFIG_USER_ONLY) |
182 |
static void spr_write_tbl (void *opaque, int sprn) |
|
191 |
static void spr_write_tbl (void *opaque, int sprn, int gprn)
|
|
183 | 192 |
{ |
184 |
gen_op_store_tbl();
|
|
193 |
gen_helper_store_tbl(cpu_gpr[gprn]);
|
|
185 | 194 |
} |
186 | 195 |
|
187 |
static void spr_write_tbu (void *opaque, int sprn) |
|
196 |
static void spr_write_tbu (void *opaque, int sprn, int gprn)
|
|
188 | 197 |
{ |
189 |
gen_op_store_tbu();
|
|
198 |
gen_helper_store_tbu(cpu_gpr[gprn]);
|
|
190 | 199 |
} |
191 | 200 |
|
192 | 201 |
__attribute__ (( unused )) |
193 |
static void spr_write_atbl (void *opaque, int sprn) |
|
202 |
static void spr_write_atbl (void *opaque, int sprn, int gprn)
|
|
194 | 203 |
{ |
195 |
gen_op_store_atbl();
|
|
204 |
gen_helper_store_atbl(cpu_gpr[gprn]);
|
|
196 | 205 |
} |
197 | 206 |
|
198 | 207 |
__attribute__ (( unused )) |
199 |
static void spr_write_atbu (void *opaque, int sprn) |
|
208 |
static void spr_write_atbu (void *opaque, int sprn, int gprn)
|
|
200 | 209 |
{ |
201 |
gen_op_store_atbu();
|
|
210 |
gen_helper_store_atbu(cpu_gpr[gprn]);
|
|
202 | 211 |
} |
203 | 212 |
#endif |
204 | 213 |
|
205 | 214 |
#if !defined(CONFIG_USER_ONLY) |
206 | 215 |
/* IBAT0U...IBAT0U */ |
207 | 216 |
/* IBAT0L...IBAT7L */ |
208 |
static void spr_read_ibat (void *opaque, int sprn) |
|
217 |
static void spr_read_ibat (void *opaque, int gprn, int sprn)
|
|
209 | 218 |
{ |
210 |
gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
|
|
219 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
|
|
211 | 220 |
} |
212 | 221 |
|
213 |
static void spr_read_ibat_h (void *opaque, int sprn) |
|
222 |
static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
|
|
214 | 223 |
{ |
215 |
gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
|
|
224 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
|
|
216 | 225 |
} |
217 | 226 |
|
218 |
static void spr_write_ibatu (void *opaque, int sprn) |
|
227 |
static void spr_write_ibatu (void *opaque, int sprn, int gprn)
|
|
219 | 228 |
{ |
220 |
gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2); |
|
229 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
|
230 |
gen_helper_store_ibatu(t0, cpu_gpr[gprn]); |
|
231 |
tcg_temp_free_i32(t0); |
|
221 | 232 |
} |
222 | 233 |
|
223 |
static void spr_write_ibatu_h (void *opaque, int sprn) |
|
234 |
static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
|
|
224 | 235 |
{ |
225 |
gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2); |
|
236 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2); |
|
237 |
gen_helper_store_ibatu(t0, cpu_gpr[gprn]); |
|
238 |
tcg_temp_free_i32(t0); |
|
226 | 239 |
} |
227 | 240 |
|
228 |
static void spr_write_ibatl (void *opaque, int sprn) |
|
241 |
static void spr_write_ibatl (void *opaque, int sprn, int gprn)
|
|
229 | 242 |
{ |
230 |
gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2); |
|
243 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); |
|
244 |
gen_helper_store_ibatl(t0, cpu_gpr[gprn]); |
|
245 |
tcg_temp_free_i32(t0); |
|
231 | 246 |
} |
232 | 247 |
|
233 |
static void spr_write_ibatl_h (void *opaque, int sprn) |
|
248 |
static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
|
|
234 | 249 |
{ |
235 |
gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2); |
|
250 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2); |
|
251 |
gen_helper_store_ibatl(t0, cpu_gpr[gprn]); |
|
252 |
tcg_temp_free_i32(t0); |
|
236 | 253 |
} |
237 | 254 |
|
238 | 255 |
/* DBAT0U...DBAT7U */ |
239 | 256 |
/* DBAT0L...DBAT7L */ |
240 |
static void spr_read_dbat (void *opaque, int sprn) |
|
257 |
static void spr_read_dbat (void *opaque, int gprn, int sprn)
|
|
241 | 258 |
{ |
242 |
gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
|
|
259 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
|
|
243 | 260 |
} |
244 | 261 |
|
245 |
static void spr_read_dbat_h (void *opaque, int sprn) |
|
262 |
static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
|
|
246 | 263 |
{ |
247 |
gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
|
|
264 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
|
|
248 | 265 |
} |
249 | 266 |
|
250 |
static void spr_write_dbatu (void *opaque, int sprn) |
|
267 |
static void spr_write_dbatu (void *opaque, int sprn, int gprn)
|
|
251 | 268 |
{ |
252 |
gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2); |
|
269 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); |
|
270 |
gen_helper_store_dbatu(t0, cpu_gpr[gprn]); |
|
271 |
tcg_temp_free_i32(t0); |
|
253 | 272 |
} |
254 | 273 |
|
255 |
static void spr_write_dbatu_h (void *opaque, int sprn) |
|
274 |
static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
|
|
256 | 275 |
{ |
257 |
gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4); |
|
276 |
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
|
277 |
gen_helper_store_dbatu(t0, cpu_gpr[gprn]); |
|
278 |
tcg_temp_free_i32(t0); |
|
258 | 279 |
} |
259 | 280 |
|
260 |
static void spr_write_dbatl (void *opaque, int sprn) |
|
281 |
static void spr_write_dbatl (void *opaque, int sprn, int gprn)
|
|
261 | 282 |
{ |
262 |
gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2); |
|
283 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); |
|
284 |
gen_helper_store_dbatl(t0, cpu_gpr[gprn]); |
|
285 |
tcg_temp_free_i32(t0); |
|
263 | 286 |
} |
264 | 287 |
|
265 |
static void spr_write_dbatl_h (void *opaque, int sprn) |
|
288 |
static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
|
|
266 | 289 |
{ |
267 |
gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4); |
|
290 |
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
|
291 |
gen_helper_store_dbatl(t0, cpu_gpr[gprn]); |
|
292 |
tcg_temp_free_i32(t0); |
|
268 | 293 |
} |
269 | 294 |
|
270 | 295 |
/* SDR1 */ |
271 |
static void spr_read_sdr1 (void *opaque, int sprn) |
|
296 |
static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
|
|
272 | 297 |
{ |
273 |
gen_op_load_sdr1();
|
|
298 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
|
|
274 | 299 |
} |
275 | 300 |
|
276 |
static void spr_write_sdr1 (void *opaque, int sprn) |
|
301 |
static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
|
|
277 | 302 |
{ |
278 |
gen_op_store_sdr1();
|
|
303 |
gen_helper_store_sdr1(cpu_gpr[gprn]);
|
|
279 | 304 |
} |
280 | 305 |
|
281 | 306 |
/* 64 bits PowerPC specific SPRs */ |
282 | 307 |
/* ASR */ |
283 | 308 |
#if defined(TARGET_PPC64) |
284 |
static void spr_read_asr (void *opaque, int sprn) |
|
309 |
static void spr_read_asr (void *opaque, int gprn, int sprn)
|
|
285 | 310 |
{ |
286 |
gen_op_load_asr();
|
|
311 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
|
|
287 | 312 |
} |
288 | 313 |
|
289 |
static void spr_write_asr (void *opaque, int sprn) |
|
314 |
static void spr_write_asr (void *opaque, int sprn, int gprn)
|
|
290 | 315 |
{ |
291 |
gen_op_store_asr();
|
|
316 |
gen_helper_store_asr(cpu_gpr[gprn]);
|
|
292 | 317 |
} |
293 | 318 |
#endif |
294 | 319 |
#endif |
295 | 320 |
|
296 | 321 |
/* PowerPC 601 specific registers */ |
297 | 322 |
/* RTC */ |
298 |
static void spr_read_601_rtcl (void *opaque, int sprn) |
|
323 |
static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
|
|
299 | 324 |
{ |
300 |
gen_op_load_601_rtcl();
|
|
325 |
gen_helper_load_601_rtcl(cpu_gpr[gprn]);
|
|
301 | 326 |
} |
302 | 327 |
|
303 |
static void spr_read_601_rtcu (void *opaque, int sprn) |
|
328 |
static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
|
|
304 | 329 |
{ |
305 |
gen_op_load_601_rtcu();
|
|
330 |
gen_helper_load_601_rtcu(cpu_gpr[gprn]);
|
|
306 | 331 |
} |
307 | 332 |
|
308 | 333 |
#if !defined(CONFIG_USER_ONLY) |
309 |
static void spr_write_601_rtcu (void *opaque, int sprn) |
|
334 |
static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
|
|
310 | 335 |
{ |
311 |
gen_op_store_601_rtcu();
|
|
336 |
gen_helper_store_601_rtcu(cpu_gpr[gprn]);
|
|
312 | 337 |
} |
313 | 338 |
|
314 |
static void spr_write_601_rtcl (void *opaque, int sprn) |
|
339 |
static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
|
|
315 | 340 |
{ |
316 |
gen_op_store_601_rtcl();
|
|
341 |
gen_helper_store_601_rtcl(cpu_gpr[gprn]);
|
|
317 | 342 |
} |
318 | 343 |
|
319 |
static void spr_write_hid0_601 (void *opaque, int sprn) |
|
344 |
static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
|
|
320 | 345 |
{ |
321 | 346 |
DisasContext *ctx = opaque; |
322 | 347 |
|
323 |
gen_op_store_hid0_601();
|
|
348 |
gen_helper_store_hid0_601(cpu_gpr[gprn]);
|
|
324 | 349 |
/* Must stop the translation as endianness may have changed */ |
325 | 350 |
GEN_STOP(ctx); |
326 | 351 |
} |
... | ... | |
328 | 353 |
|
329 | 354 |
/* Unified bats */ |
330 | 355 |
#if !defined(CONFIG_USER_ONLY) |
331 |
static void spr_read_601_ubat (void *opaque, int sprn) |
|
356 |
static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
|
|
332 | 357 |
{ |
333 |
gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
|
|
358 |
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
|
|
334 | 359 |
} |
335 | 360 |
|
336 |
static void spr_write_601_ubatu (void *opaque, int sprn) |
|
361 |
static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
|
|
337 | 362 |
{ |
338 |
gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2); |
|
363 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
|
364 |
gen_helper_store_601_batl(t0, cpu_gpr[gprn]); |
|
365 |
tcg_temp_free_i32(t0); |
|
339 | 366 |
} |
340 | 367 |
|
341 |
static void spr_write_601_ubatl (void *opaque, int sprn) |
|
368 |
static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
|
|
342 | 369 |
{ |
343 |
gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2); |
|
370 |
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
|
371 |
gen_helper_store_601_batu(t0, cpu_gpr[gprn]); |
|
372 |
tcg_temp_free_i32(t0); |
|
344 | 373 |
} |
345 | 374 |
#endif |
346 | 375 |
|
347 | 376 |
/* PowerPC 40x specific registers */ |
348 | 377 |
#if !defined(CONFIG_USER_ONLY) |
349 |
static void spr_read_40x_pit (void *opaque, int sprn) |
|
378 |
static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
|
|
350 | 379 |
{ |
351 |
gen_op_load_40x_pit();
|
|
380 |
gen_helper_load_40x_pit(cpu_gpr[gprn]);
|
|
352 | 381 |
} |
353 | 382 |
|
354 |
static void spr_write_40x_pit (void *opaque, int sprn) |
|
383 |
static void spr_write_40x_pit (void *opaque, int sprn, int gprn) |
Also available in: Unified diff