Archipelago » qemu

				 s->cirrus_mmio_io_addr);

}

                         unsigned long vga_ram_offset, int vga_ram_size)

{

    PCICirrusVGAState *d;

    device_id = CIRRUS_ID_CLGD5446;

    /* setup PCI configuration registers */

                                                 sizeof(PCICirrusVGAState), 

    pci_conf = d->dev.config;

    pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);

    pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);

}

/* hd_table must contain 4 block drivers */

{

    PCIIDEState *d;

    uint8_t *pci_conf;

    int i;

                                           NULL, NULL);

    pci_conf = d->dev.config;

    pci_conf[0x00] = 0x86; // Intel

/* hd_table must contain 4 block drivers */

/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */

{

    PCIIDEState *d;

    uint8_t *pci_conf;

    /* register a function 1 of PIIX3 */

                                           NULL, NULL);

    pci_conf = d->dev.config;

    pci_conf[0x00] = 0x86; // Intel

    register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);

}

{

    PCINE2000State *d;

    NE2000State *s;

    uint8_t *pci_conf;

                                              NULL, NULL);

    pci_conf = d->dev.config;

    pci_conf[0x00] = 0xec; // Realtek 8029

#endif

}

{

    openpic_t *opp;

    uint8_t *pci_conf;

    /* XXX: for now, only one CPU is supported */

    if (nb_cpus != 1)

        return NULL;

    if (opp == NULL)

        return NULL;

    pci_conf = opp->pci_dev.config;

    int ret, linux_boot, initrd_size, i, nb_nics1, fd;

    unsigned long bios_offset, vga_bios_offset;

    int bios_size, isa_bios_size;

    linux_boot = (kernel_filename != NULL);

    /* allocate RAM */

    }

    if (pci_enabled) {

    }

    /* init basic PC hardware */

    if (cirrus_vga_enabled) {

        if (pci_enabled) {

                                vga_ram_size);

        } else {

            isa_cirrus_vga_init(ds, phys_ram_base + ram_size, ram_size, 

                                vga_ram_size);

        }

    } else {

    }

    rtc_state = rtc_init(0x70, 8);

    if (pci_enabled) {

        for(i = 0; i < nb_nics; i++) {

        }

    } else {

        nb_nics1 = nb_nics;

        if (nb_nics1 > NE2000_NB_MAX)

    cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);

}

{

    PCIDevice *d;

    /* Note: this code is strongly inspirated from the corresponding code

       in PearPC */

    d->config[0x00] = 0x6b; // vendor_id

    int ret, linux_boot, i, fd;

    unsigned long bios_offset;

    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    linux_boot = (kernel_filename != NULL);

    /* allocate RAM */

    cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);

    isa_mem_base = 0x80000000;

    /* Register 8 MB of ISA IO space */

    PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);

    cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);

    /* init basic PC hardware */

    /* XXX: suppress that */

    pic_init();

    serial_init(0x3f8, 4, fd);

    for(i = 0; i < nb_nics; i++) {

    }

    ide0_mem_index = pmac_ide_init(&bs_table[0], openpic, 0x13);

    adb_kbd_init(&adb_bus);

    adb_mouse_init(&adb_bus);

    nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);

    int ret, linux_boot, i, nb_nics1, fd;

    unsigned long bios_offset;

    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    sysctrl = qemu_mallocz(sizeof(sysctrl_t));

    if (sysctrl == NULL)

    cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);

    isa_mem_base = 0xc0000000;

    /* Register 64 KB of ISA IO space */

    PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);

    cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory);

    /* init basic PC hardware */

    rtc_init(0x70, 8);

    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);

    //    pic_init(openpic);

                         /* XXX: need an option to load a NVRAM image */

                         0,

                         graphic_width, graphic_height, graphic_depth);

}

}

{

    VGAState *s;

    cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, 

                                 vga_io_memory);

        PCIDevice *d;

        uint8_t *pci_conf;

                                sizeof(PCIDevice),

        pci_conf = d->config;

        pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)

        pci_conf[0x01] = 0x12;

extern target_phys_addr_t pci_mem_base;

typedef struct PCIDevice PCIDevice;

typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 

    uint8_t config[256];

    /* the following fields are read only */

    int devfn;

    char name[64];

    PCIIORegion io_regions[PCI_NUM_REGIONS];

    int irq_index;

};

                               PCIConfigReadFunc *config_read, 

                               PCIConfigWriteFunc *config_write);

extern struct PIIX3State *piix3_state;

void pci_bios_init(void);

void pci_info(void);

/* temporary: will be moved in platform specific file */

/* openpic.c */

typedef struct openpic_t openpic_t;

void openpic_set_irq (openpic_t *opp, int n_IRQ, int level);

/* vga.c */

    s->dpy_resize(s, w, h);

}

void vga_update_display(void);

void vga_invalidate_display(void);

void vga_screen_dump(const char *filename);

/* cirrus_vga.c */

                         unsigned long vga_ram_offset, int vga_ram_size);

void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 

                         unsigned long vga_ram_offset, int vga_ram_size);

void isa_ide_init(int iobase, int iobase2, int irq,

                  BlockDriverState *hd0, BlockDriverState *hd1);

int pmac_ide_init (BlockDriverState **hd_table,

                   openpic_t *openpic, int irq);

/* ne2000.c */

void isa_ne2000_init(int base, int irq, NetDriverState *nd);

/* pckbd.c */