Revision 47103572 hw/openpic.c
| b/hw/openpic.c | ||
|---|---|---|
| 164 | 164 |
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| 165 | 165 |
struct openpic_t {
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| 166 | 166 |
PCIDevice pci_dev; |
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SetIRQFunc *set_irq; |
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int mem_index; |
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/* Global registers */ |
| 169 | 170 |
uint32_t frep; /* Feature reporting register */ |
| ... | ... | |
| 264 | 265 |
IRQ_setbit(&dst->raised, n_IRQ); |
| 265 | 266 |
if (priority > dst->raised.priority) {
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IRQ_get_next(opp, &dst->raised); |
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DPRINTF("Raise CPU IRQ\n");
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cpu_interrupt(dst->env, CPU_INTERRUPT_HARD);
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DPRINTF("Raise CPU IRQ fn %p env %p\n", opp->set_irq, dst->env);
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opp->set_irq(dst->env, OPENPIC_EVT_INT, 1);
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} |
| 270 | 271 |
} |
| 271 | 272 |
|
| ... | ... | |
| 532 | 533 |
/* XXX: Should be able to reset any CPU */ |
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if (val & 1) {
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DPRINTF("Reset CPU IRQ\n");
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// cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
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// opp->set_irq(dst->env, OPENPIC_EVT_RESET, 1);
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} |
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break; |
| 538 | 539 |
#if MAX_IPI > 0 |
| ... | ... | |
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src = &opp->src[n_IRQ]; |
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if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) {
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DPRINTF("Raise CPU IRQ\n");
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cpu_interrupt(dst->env, CPU_INTERRUPT_HARD);
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opp->set_irq(dst->env, OPENPIC_EVT_INT, 1);
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} |
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} |
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break; |
| ... | ... | |
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#endif |
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} |
| 965 | 966 |
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openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
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CPUPPCState **envp) |
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openpic_t *openpic_init (PCIBus *bus, SetIRQFunc *set_irq,
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int *pmem_index, int nb_cpus, CPUPPCState **envp)
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{
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openpic_t *opp; |
| 970 | 971 |
uint8_t *pci_conf; |
| ... | ... | |
| 994 | 995 |
} else {
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opp = qemu_mallocz(sizeof(openpic_t)); |
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} |
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|
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opp->set_irq = set_irq; |
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| 998 | 999 |
opp->mem_index = cpu_register_io_memory(0, openpic_read, |
| 999 | 1000 |
openpic_write, opp); |
| 1000 | 1001 |
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