Revision 47103572 hw/ppc_prep.c
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/* |
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* QEMU PPC PREP hardware System Emulator |
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* |
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* Copyright (c) 2003-2004 Jocelyn Mayer
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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#endif |
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} |
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static uint32_t speaker_ioport_read(void *opaque, uint32_t addr) |
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static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
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{
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#if 0 |
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int out; |
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out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); |
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dummy_refresh_clock ^= 1; |
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return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | |
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(dummy_refresh_clock << 4); |
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(dummy_refresh_clock << 4);
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#endif |
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return 0; |
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} |
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static void pic_irq_request(void *opaque, int level) |
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static void pic_irq_request (void *opaque, int level)
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{
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if (level) |
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cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
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else |
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cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
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ppc_set_irq(opaque, PPC_INTERRUPT_EXT, level); |
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} |
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/* PCI intack register */ |
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/* Read-only register (?) */ |
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static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) |
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static void _PPC_intack_write (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{
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// printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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} |
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/* Special port 92 */ |
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/* Check soft reset asked */ |
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if (val & 0x01) {
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// cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
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// cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
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} |
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/* Check LE mode */ |
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if (val & 0x02) {
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