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/*
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 * Texas Instruments OMAP processors.
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 *
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 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 * MA 02111-1307 USA
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 */
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#ifndef hw_omap_h
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# define hw_omap_h                "omap.h"
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# define OMAP_EMIFS_BASE        0x00000000
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# define OMAP2_Q0_BASE                0x00000000
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# define OMAP_CS0_BASE                0x00000000
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# define OMAP_CS1_BASE                0x04000000
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# define OMAP_CS2_BASE                0x08000000
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# define OMAP_CS3_BASE                0x0c000000
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# define OMAP_EMIFF_BASE        0x10000000
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# define OMAP_IMIF_BASE                0x20000000
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# define OMAP_LOCALBUS_BASE        0x30000000
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# define OMAP2_Q1_BASE                0x40000000
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# define OMAP2_L4_BASE                0x48000000
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# define OMAP2_SRAM_BASE        0x40200000
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# define OMAP2_L3_BASE                0x68000000
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# define OMAP2_Q2_BASE                0x80000000
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# define OMAP2_Q3_BASE                0xc0000000
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# define OMAP_MPUI_BASE                0xe1000000
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# define OMAP730_SRAM_SIZE        0x00032000
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# define OMAP15XX_SRAM_SIZE        0x00030000
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# define OMAP16XX_SRAM_SIZE        0x00004000
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# define OMAP1611_SRAM_SIZE        0x0003e800
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# define OMAP242X_SRAM_SIZE        0x000a0000
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# define OMAP243X_SRAM_SIZE        0x00010000
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# define OMAP_CS0_SIZE                0x04000000
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# define OMAP_CS1_SIZE                0x04000000
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# define OMAP_CS2_SIZE                0x04000000
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# define OMAP_CS3_SIZE                0x04000000
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/* omap_clk.c */
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struct omap_mpu_state_s;
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typedef struct clk *omap_clk;
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omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
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void omap_clk_init(struct omap_mpu_state_s *mpu);
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void omap_clk_adduser(struct clk *clk, qemu_irq user);
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void omap_clk_get(omap_clk clk);
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void omap_clk_put(omap_clk clk);
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void omap_clk_onoff(omap_clk clk, int on);
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void omap_clk_canidle(omap_clk clk, int can);
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void omap_clk_setrate(omap_clk clk, int divide, int multiply);
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int64_t omap_clk_getrate(omap_clk clk);
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void omap_clk_reparent(omap_clk clk, omap_clk parent);
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66
/* omap[123].c */
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struct omap_l4_s;
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struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
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struct omap_target_agent_s;
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struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
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target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
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                int iotype);
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# define l4_register_io_memory        cpu_register_io_memory
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struct omap_intr_handler_s;
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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                unsigned long size, unsigned char nbanks, qemu_irq **pins,
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                qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
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struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
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                int size, int nbanks, qemu_irq **pins,
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                qemu_irq parent_irq, qemu_irq parent_fiq,
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                omap_clk fclk, omap_clk iclk);
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void omap_inth_reset(struct omap_intr_handler_s *s);
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struct omap_prcm_s;
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struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
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                qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
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                struct omap_mpu_state_s *mpu);
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struct omap_sysctl_s;
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struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
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                omap_clk iclk, struct omap_mpu_state_s *mpu);
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struct omap_sdrc_s;
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struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
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struct omap_gpmc_s;
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struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
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                void (*base_upd)(void *opaque, target_phys_addr_t new),
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                void (*unmap)(void *opaque), void *opaque);
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/*
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 * Common IRQ numbers for level 1 interrupt handler
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 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
107
 */
108
# define OMAP_INT_CAMERA                1
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# define OMAP_INT_FIQ                        3
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# define OMAP_INT_RTDX                        6
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# define OMAP_INT_DSP_MMU_ABORT                7
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# define OMAP_INT_HOST                        8
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# define OMAP_INT_ABORT                        9
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# define OMAP_INT_BRIDGE_PRIV                13
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# define OMAP_INT_GPIO_BANK1                14
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# define OMAP_INT_UART3                        15
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# define OMAP_INT_TIMER3                16
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# define OMAP_INT_DMA_CH0_6                19
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# define OMAP_INT_DMA_CH1_7                20
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# define OMAP_INT_DMA_CH2_8                21
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# define OMAP_INT_DMA_CH3                22
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# define OMAP_INT_DMA_CH4                23
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# define OMAP_INT_DMA_CH5                24
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# define OMAP_INT_DMA_LCD                25
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# define OMAP_INT_TIMER1                26
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# define OMAP_INT_WD_TIMER                27
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# define OMAP_INT_BRIDGE_PUB                28
128
# define OMAP_INT_TIMER2                30
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# define OMAP_INT_LCD_CTRL                31
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131
/*
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 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
133
 */
134
# define OMAP_INT_15XX_IH2_IRQ                0
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# define OMAP_INT_15XX_LB_MMU                17
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# define OMAP_INT_15XX_LOCAL_BUS        29
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/*
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 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
140
 */
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# define OMAP_INT_1510_SPI_TX                4
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# define OMAP_INT_1510_SPI_RX                5
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# define OMAP_INT_1510_DSP_MAILBOX1        10
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# define OMAP_INT_1510_DSP_MAILBOX2        11
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146
/*
147
 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
148
 */
149
# define OMAP_INT_310_McBSP2_TX                4
150
# define OMAP_INT_310_McBSP2_RX                5
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# define OMAP_INT_310_HSB_MAILBOX1        12
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# define OMAP_INT_310_HSAB_MMU                18
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/*
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 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
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 */
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# define OMAP_INT_1610_IH2_IRQ                0
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# define OMAP_INT_1610_IH2_FIQ                2
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# define OMAP_INT_1610_McBSP2_TX        4
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# define OMAP_INT_1610_McBSP2_RX        5
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# define OMAP_INT_1610_DSP_MAILBOX1        10
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# define OMAP_INT_1610_DSP_MAILBOX2        11
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# define OMAP_INT_1610_LCD_LINE                12
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# define OMAP_INT_1610_GPTIMER1                17
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# define OMAP_INT_1610_GPTIMER2                18
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# define OMAP_INT_1610_SSR_FIFO_0        29
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/*
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 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
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 */
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# define OMAP_INT_730_IH2_FIQ                0
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# define OMAP_INT_730_IH2_IRQ                1
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# define OMAP_INT_730_USB_NON_ISO        2
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# define OMAP_INT_730_USB_ISO                3
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# define OMAP_INT_730_ICR                4
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# define OMAP_INT_730_EAC                5
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# define OMAP_INT_730_GPIO_BANK1        6
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# define OMAP_INT_730_GPIO_BANK2        7
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# define OMAP_INT_730_GPIO_BANK3        8
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# define OMAP_INT_730_McBSP2TX                10
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# define OMAP_INT_730_McBSP2RX                11
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# define OMAP_INT_730_McBSP2RX_OVF        12
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# define OMAP_INT_730_LCD_LINE                14
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# define OMAP_INT_730_GSM_PROTECT        15
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# define OMAP_INT_730_TIMER3                16
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# define OMAP_INT_730_GPIO_BANK5        17
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# define OMAP_INT_730_GPIO_BANK6        18
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# define OMAP_INT_730_SPGIO_WR                29
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/*
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 * Common IRQ numbers for level 2 interrupt handler
192
 */
193
# define OMAP_INT_KEYBOARD                1
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# define OMAP_INT_uWireTX                2
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# define OMAP_INT_uWireRX                3
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# define OMAP_INT_I2C                        4
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# define OMAP_INT_MPUIO                        5
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# define OMAP_INT_USB_HHC_1                6
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# define OMAP_INT_McBSP3TX                10
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# define OMAP_INT_McBSP3RX                11
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# define OMAP_INT_McBSP1TX                12
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# define OMAP_INT_McBSP1RX                13
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# define OMAP_INT_UART1                        14
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# define OMAP_INT_UART2                        15
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# define OMAP_INT_USB_W2FC                20
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# define OMAP_INT_1WIRE                        21
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# define OMAP_INT_OS_TIMER                22
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# define OMAP_INT_OQN                        23
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# define OMAP_INT_GAUGE_32K                24
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# define OMAP_INT_RTC_TIMER                25
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# define OMAP_INT_RTC_ALARM                26
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# define OMAP_INT_DSP_MMU                28
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/*
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 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
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 */
217
# define OMAP_INT_1510_BT_MCSI1TX        16
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# define OMAP_INT_1510_BT_MCSI1RX        17
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# define OMAP_INT_1510_SoSSI_MATCH        19
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# define OMAP_INT_1510_MEM_STICK        27
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# define OMAP_INT_1510_COM_SPI_RO        31
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223
/*
224
 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
225
 */
226
# define OMAP_INT_310_FAC                0
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# define OMAP_INT_310_USB_HHC_2                7
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# define OMAP_INT_310_MCSI1_FE                16
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# define OMAP_INT_310_MCSI2_FE                17
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# define OMAP_INT_310_USB_W2FC_ISO        29
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# define OMAP_INT_310_USB_W2FC_NON_ISO        30
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# define OMAP_INT_310_McBSP2RX_OF        31
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234
/*
235
 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
236
 */
237
# define OMAP_INT_1610_FAC                0
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# define OMAP_INT_1610_USB_HHC_2        7
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# define OMAP_INT_1610_USB_OTG                8
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# define OMAP_INT_1610_SoSSI                9
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# define OMAP_INT_1610_BT_MCSI1TX        16
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# define OMAP_INT_1610_BT_MCSI1RX        17
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# define OMAP_INT_1610_SoSSI_MATCH        19
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# define OMAP_INT_1610_MEM_STICK        27
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# define OMAP_INT_1610_McBSP2RX_OF        31
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# define OMAP_INT_1610_STI                32
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# define OMAP_INT_1610_STI_WAKEUP        33
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# define OMAP_INT_1610_GPTIMER3                34
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# define OMAP_INT_1610_GPTIMER4                35
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# define OMAP_INT_1610_GPTIMER5                36
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# define OMAP_INT_1610_GPTIMER6                37
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# define OMAP_INT_1610_GPTIMER7                38
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# define OMAP_INT_1610_GPTIMER8                39
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# define OMAP_INT_1610_GPIO_BANK2        40
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# define OMAP_INT_1610_GPIO_BANK3        41
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# define OMAP_INT_1610_MMC2                42
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# define OMAP_INT_1610_CF                43
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# define OMAP_INT_1610_WAKE_UP_REQ        46
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# define OMAP_INT_1610_GPIO_BANK4        48
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# define OMAP_INT_1610_SPI                49
261
# define OMAP_INT_1610_DMA_CH6                53
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# define OMAP_INT_1610_DMA_CH7                54
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# define OMAP_INT_1610_DMA_CH8                55
264
# define OMAP_INT_1610_DMA_CH9                56
265
# define OMAP_INT_1610_DMA_CH10                57
266
# define OMAP_INT_1610_DMA_CH11                58
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# define OMAP_INT_1610_DMA_CH12                59
268
# define OMAP_INT_1610_DMA_CH13                60
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# define OMAP_INT_1610_DMA_CH14                61
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# define OMAP_INT_1610_DMA_CH15                62
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# define OMAP_INT_1610_NAND                63
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/*
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 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
275
 */
276
# define OMAP_INT_730_HW_ERRORS                0
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# define OMAP_INT_730_NFIQ_PWR_FAIL        1
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# define OMAP_INT_730_CFCD                2
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# define OMAP_INT_730_CFIREQ                3
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# define OMAP_INT_730_I2C                4
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# define OMAP_INT_730_PCC                5
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# define OMAP_INT_730_MPU_EXT_NIRQ        6
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# define OMAP_INT_730_SPI_100K_1        7
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# define OMAP_INT_730_SYREN_SPI                8
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# define OMAP_INT_730_VLYNQ                9
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# define OMAP_INT_730_GPIO_BANK4        10
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# define OMAP_INT_730_McBSP1TX                11
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# define OMAP_INT_730_McBSP1RX                12
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# define OMAP_INT_730_McBSP1RX_OF        13
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# define OMAP_INT_730_UART_MODEM_IRDA_2        14
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# define OMAP_INT_730_UART_MODEM_1        15
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# define OMAP_INT_730_MCSI                16
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# define OMAP_INT_730_uWireTX                17
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# define OMAP_INT_730_uWireRX                18
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# define OMAP_INT_730_SMC_CD                19
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# define OMAP_INT_730_SMC_IREQ                20
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# define OMAP_INT_730_HDQ_1WIRE                21
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# define OMAP_INT_730_TIMER32K                22
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# define OMAP_INT_730_MMC_SDIO                23
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# define OMAP_INT_730_UPLD                24
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# define OMAP_INT_730_USB_HHC_1                27
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# define OMAP_INT_730_USB_HHC_2                28
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# define OMAP_INT_730_USB_GENI                29
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# define OMAP_INT_730_USB_OTG                30
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# define OMAP_INT_730_CAMERA_IF                31
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# define OMAP_INT_730_RNG                32
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# define OMAP_INT_730_DUAL_MODE_TIMER        33
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# define OMAP_INT_730_DBB_RF_EN                34
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# define OMAP_INT_730_MPUIO_KEYPAD        35
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# define OMAP_INT_730_SHA1_MD5                36
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# define OMAP_INT_730_SPI_100K_2        37
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# define OMAP_INT_730_RNG_IDLE                38
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# define OMAP_INT_730_MPUIO                39
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# define OMAP_INT_730_LLPC_LCD_CTRL_OFF        40
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# define OMAP_INT_730_LLPC_OE_FALLING        41
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# define OMAP_INT_730_LLPC_OE_RISING        42
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# define OMAP_INT_730_LLPC_VSYNC        43
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# define OMAP_INT_730_WAKE_UP_REQ        46
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# define OMAP_INT_730_DMA_CH6                53
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# define OMAP_INT_730_DMA_CH7                54
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# define OMAP_INT_730_DMA_CH8                55
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# define OMAP_INT_730_DMA_CH9                56
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# define OMAP_INT_730_DMA_CH10                57
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# define OMAP_INT_730_DMA_CH11                58
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# define OMAP_INT_730_DMA_CH12                59
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# define OMAP_INT_730_DMA_CH13                60
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# define OMAP_INT_730_DMA_CH14                61
328
# define OMAP_INT_730_DMA_CH15                62
329
# define OMAP_INT_730_NAND                63
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/*
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 * OMAP-24xx common IRQ numbers
333
 */
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# define OMAP_INT_24XX_STI                4
335
# define OMAP_INT_24XX_SYS_NIRQ                7
336
# define OMAP_INT_24XX_L3_IRQ                10
337
# define OMAP_INT_24XX_PRCM_MPU_IRQ        11
338
# define OMAP_INT_24XX_SDMA_IRQ0        12
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# define OMAP_INT_24XX_SDMA_IRQ1        13
340
# define OMAP_INT_24XX_SDMA_IRQ2        14
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# define OMAP_INT_24XX_SDMA_IRQ3        15
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# define OMAP_INT_243X_MCBSP2_IRQ        16
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# define OMAP_INT_243X_MCBSP3_IRQ        17
344
# define OMAP_INT_243X_MCBSP4_IRQ        18
345
# define OMAP_INT_243X_MCBSP5_IRQ        19
346
# define OMAP_INT_24XX_GPMC_IRQ                20
347
# define OMAP_INT_24XX_GUFFAW_IRQ        21
348
# define OMAP_INT_24XX_IVA_IRQ                22
349
# define OMAP_INT_24XX_EAC_IRQ                23
350
# define OMAP_INT_24XX_CAM_IRQ                24
351
# define OMAP_INT_24XX_DSS_IRQ                25
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# define OMAP_INT_24XX_MAIL_U0_MPU        26
353
# define OMAP_INT_24XX_DSP_UMA                27
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# define OMAP_INT_24XX_DSP_MMU                28
355
# define OMAP_INT_24XX_GPIO_BANK1        29
356
# define OMAP_INT_24XX_GPIO_BANK2        30
357
# define OMAP_INT_24XX_GPIO_BANK3        31
358
# define OMAP_INT_24XX_GPIO_BANK4        32
359
# define OMAP_INT_243X_GPIO_BANK5        33
360
# define OMAP_INT_24XX_MAIL_U3_MPU        34
361
# define OMAP_INT_24XX_WDT3                35
362
# define OMAP_INT_24XX_WDT4                36
363
# define OMAP_INT_24XX_GPTIMER1                37
364
# define OMAP_INT_24XX_GPTIMER2                38
365
# define OMAP_INT_24XX_GPTIMER3                39
366
# define OMAP_INT_24XX_GPTIMER4                40
367
# define OMAP_INT_24XX_GPTIMER5                41
368
# define OMAP_INT_24XX_GPTIMER6                42
369
# define OMAP_INT_24XX_GPTIMER7                43
370
# define OMAP_INT_24XX_GPTIMER8                44
371
# define OMAP_INT_24XX_GPTIMER9                45
372
# define OMAP_INT_24XX_GPTIMER10        46
373
# define OMAP_INT_24XX_GPTIMER11        47
374
# define OMAP_INT_24XX_GPTIMER12        48
375
# define OMAP_INT_24XX_PKA_IRQ                50
376
# define OMAP_INT_24XX_SHA1MD5_IRQ        51
377
# define OMAP_INT_24XX_RNG_IRQ                52
378
# define OMAP_INT_24XX_MG_IRQ                53
379
# define OMAP_INT_24XX_I2C1_IRQ                56
380
# define OMAP_INT_24XX_I2C2_IRQ                57
381
# define OMAP_INT_24XX_MCBSP1_IRQ_TX        59
382
# define OMAP_INT_24XX_MCBSP1_IRQ_RX        60
383
# define OMAP_INT_24XX_MCBSP2_IRQ_TX        62
384
# define OMAP_INT_24XX_MCBSP2_IRQ_RX        63
385
# define OMAP_INT_243X_MCBSP1_IRQ        64
386
# define OMAP_INT_24XX_MCSPI1_IRQ        65
387
# define OMAP_INT_24XX_MCSPI2_IRQ        66
388
# define OMAP_INT_24XX_SSI1_IRQ0        67
389
# define OMAP_INT_24XX_SSI1_IRQ1        68
390
# define OMAP_INT_24XX_SSI2_IRQ0        69
391
# define OMAP_INT_24XX_SSI2_IRQ1        70
392
# define OMAP_INT_24XX_SSI_GDD_IRQ        71
393
# define OMAP_INT_24XX_UART1_IRQ        72
394
# define OMAP_INT_24XX_UART2_IRQ        73
395
# define OMAP_INT_24XX_UART3_IRQ        74
396
# define OMAP_INT_24XX_USB_IRQ_GEN        75
397
# define OMAP_INT_24XX_USB_IRQ_NISO        76
398
# define OMAP_INT_24XX_USB_IRQ_ISO        77
399
# define OMAP_INT_24XX_USB_IRQ_HGEN        78
400
# define OMAP_INT_24XX_USB_IRQ_HSOF        79
401
# define OMAP_INT_24XX_USB_IRQ_OTG        80
402
# define OMAP_INT_24XX_VLYNQ_IRQ        81
403
# define OMAP_INT_24XX_MMC_IRQ                83
404
# define OMAP_INT_24XX_MS_IRQ                84
405
# define OMAP_INT_24XX_FAC_IRQ                85
406
# define OMAP_INT_24XX_MCSPI3_IRQ        91
407
# define OMAP_INT_243X_HS_USB_MC        92
408
# define OMAP_INT_243X_HS_USB_DMA        93
409
# define OMAP_INT_243X_CARKIT                94
410
# define OMAP_INT_34XX_GPTIMER12        95
411

    
412
/* omap_dma.c */
413
enum omap_dma_model {
414
    omap_dma_3_0,
415
    omap_dma_3_1,
416
    omap_dma_3_2,
417
    omap_dma_4,
418
};
419

    
420
struct omap_dma_s;
421
struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
422
                qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
423
                enum omap_dma_model model);
424
struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
425
                struct omap_mpu_state_s *mpu, int fifo,
426
                int chans, omap_clk iclk, omap_clk fclk);
427
void omap_dma_reset(struct omap_dma_s *s);
428

    
429
struct dma_irq_map {
430
    int ih;
431
    int intr;
432
};
433

    
434
/* Only used in OMAP DMA 3.x gigacells */
435
enum omap_dma_port {
436
    emiff = 0,
437
    emifs,
438
    imif,        /* omap16xx: ocp_t1 */
439
    tipb,
440
    local,        /* omap16xx: ocp_t2 */
441
    tipb_mpui,
442
    __omap_dma_port_last,
443
};
444

    
445
typedef enum {
446
    constant = 0,
447
    post_incremented,
448
    single_index,
449
    double_index,
450
} omap_dma_addressing_t;
451

    
452
/* Only used in OMAP DMA 3.x gigacells */
453
struct omap_dma_lcd_channel_s {
454
    enum omap_dma_port src;
455
    target_phys_addr_t src_f1_top;
456
    target_phys_addr_t src_f1_bottom;
457
    target_phys_addr_t src_f2_top;
458
    target_phys_addr_t src_f2_bottom;
459

    
460
    /* Used in OMAP DMA 3.2 gigacell */
461
    unsigned char brust_f1;
462
    unsigned char pack_f1;
463
    unsigned char data_type_f1;
464
    unsigned char brust_f2;
465
    unsigned char pack_f2;
466
    unsigned char data_type_f2;
467
    unsigned char end_prog;
468
    unsigned char repeat;
469
    unsigned char auto_init;
470
    unsigned char priority;
471
    unsigned char fs;
472
    unsigned char running;
473
    unsigned char bs;
474
    unsigned char omap_3_1_compatible_disable;
475
    unsigned char dst;
476
    unsigned char lch_type;
477
    int16_t element_index_f1;
478
    int16_t element_index_f2;
479
    int32_t frame_index_f1;
480
    int32_t frame_index_f2;
481
    uint16_t elements_f1;
482
    uint16_t frames_f1;
483
    uint16_t elements_f2;
484
    uint16_t frames_f2;
485
    omap_dma_addressing_t mode_f1;
486
    omap_dma_addressing_t mode_f2;
487

    
488
    /* Destination port is fixed.  */
489
    int interrupts;
490
    int condition;
491
    int dual;
492

    
493
    int current_frame;
494
    ram_addr_t phys_framebuffer[2];
495
    qemu_irq irq;
496
    struct omap_mpu_state_s *mpu;
497
} *omap_dma_get_lcdch(struct omap_dma_s *s);
498

    
499
/*
500
 * DMA request numbers for OMAP1
501
 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
502
 */
503
# define OMAP_DMA_NO_DEVICE                0
504
# define OMAP_DMA_MCSI1_TX                1
505
# define OMAP_DMA_MCSI1_RX                2
506
# define OMAP_DMA_I2C_RX                3
507
# define OMAP_DMA_I2C_TX                4
508
# define OMAP_DMA_EXT_NDMA_REQ0                5
509
# define OMAP_DMA_EXT_NDMA_REQ1                6
510
# define OMAP_DMA_UWIRE_TX                7
511
# define OMAP_DMA_MCBSP1_TX                8
512
# define OMAP_DMA_MCBSP1_RX                9
513
# define OMAP_DMA_MCBSP3_TX                10
514
# define OMAP_DMA_MCBSP3_RX                11
515
# define OMAP_DMA_UART1_TX                12
516
# define OMAP_DMA_UART1_RX                13
517
# define OMAP_DMA_UART2_TX                14
518
# define OMAP_DMA_UART2_RX                15
519
# define OMAP_DMA_MCBSP2_TX                16
520
# define OMAP_DMA_MCBSP2_RX                17
521
# define OMAP_DMA_UART3_TX                18
522
# define OMAP_DMA_UART3_RX                19
523
# define OMAP_DMA_CAMERA_IF_RX                20
524
# define OMAP_DMA_MMC_TX                21
525
# define OMAP_DMA_MMC_RX                22
526
# define OMAP_DMA_NAND                        23        /* Not in OMAP310 */
527
# define OMAP_DMA_IRQ_LCD_LINE                24        /* Not in OMAP310 */
528
# define OMAP_DMA_MEMORY_STICK                25        /* Not in OMAP310 */
529
# define OMAP_DMA_USB_W2FC_RX0                26
530
# define OMAP_DMA_USB_W2FC_RX1                27
531
# define OMAP_DMA_USB_W2FC_RX2                28
532
# define OMAP_DMA_USB_W2FC_TX0                29
533
# define OMAP_DMA_USB_W2FC_TX1                30
534
# define OMAP_DMA_USB_W2FC_TX2                31
535

    
536
/* These are only for 1610 */
537
# define OMAP_DMA_CRYPTO_DES_IN                32
538
# define OMAP_DMA_SPI_TX                33
539
# define OMAP_DMA_SPI_RX                34
540
# define OMAP_DMA_CRYPTO_HASH                35
541
# define OMAP_DMA_CCP_ATTN                36
542
# define OMAP_DMA_CCP_FIFO_NOT_EMPTY        37
543
# define OMAP_DMA_CMT_APE_TX_CHAN_0        38
544
# define OMAP_DMA_CMT_APE_RV_CHAN_0        39
545
# define OMAP_DMA_CMT_APE_TX_CHAN_1        40
546
# define OMAP_DMA_CMT_APE_RV_CHAN_1        41
547
# define OMAP_DMA_CMT_APE_TX_CHAN_2        42
548
# define OMAP_DMA_CMT_APE_RV_CHAN_2        43
549
# define OMAP_DMA_CMT_APE_TX_CHAN_3        44
550
# define OMAP_DMA_CMT_APE_RV_CHAN_3        45
551
# define OMAP_DMA_CMT_APE_TX_CHAN_4        46
552
# define OMAP_DMA_CMT_APE_RV_CHAN_4        47
553
# define OMAP_DMA_CMT_APE_TX_CHAN_5        48
554
# define OMAP_DMA_CMT_APE_RV_CHAN_5        49
555
# define OMAP_DMA_CMT_APE_TX_CHAN_6        50
556
# define OMAP_DMA_CMT_APE_RV_CHAN_6        51
557
# define OMAP_DMA_CMT_APE_TX_CHAN_7        52
558
# define OMAP_DMA_CMT_APE_RV_CHAN_7        53
559
# define OMAP_DMA_MMC2_TX                54
560
# define OMAP_DMA_MMC2_RX                55
561
# define OMAP_DMA_CRYPTO_DES_OUT        56
562

    
563
/*
564
 * DMA request numbers for the OMAP2
565
 */
566
# define OMAP24XX_DMA_NO_DEVICE                0
567
# define OMAP24XX_DMA_XTI_DMA                1        /* Not in OMAP2420 */
568
# define OMAP24XX_DMA_EXT_DMAREQ0        2
569
# define OMAP24XX_DMA_EXT_DMAREQ1        3
570
# define OMAP24XX_DMA_GPMC                4
571
# define OMAP24XX_DMA_GFX                5        /* Not in OMAP2420 */
572
# define OMAP24XX_DMA_DSS                6
573
# define OMAP24XX_DMA_VLYNQ_TX                7        /* Not in OMAP2420 */
574
# define OMAP24XX_DMA_CWT                8        /* Not in OMAP2420 */
575
# define OMAP24XX_DMA_AES_TX                9        /* Not in OMAP2420 */
576
# define OMAP24XX_DMA_AES_RX                10        /* Not in OMAP2420 */
577
# define OMAP24XX_DMA_DES_TX                11        /* Not in OMAP2420 */
578
# define OMAP24XX_DMA_DES_RX                12        /* Not in OMAP2420 */
579
# define OMAP24XX_DMA_SHA1MD5_RX        13        /* Not in OMAP2420 */
580
# define OMAP24XX_DMA_EXT_DMAREQ2        14
581
# define OMAP24XX_DMA_EXT_DMAREQ3        15
582
# define OMAP24XX_DMA_EXT_DMAREQ4        16
583
# define OMAP24XX_DMA_EAC_AC_RD                17
584
# define OMAP24XX_DMA_EAC_AC_WR                18
585
# define OMAP24XX_DMA_EAC_MD_UL_RD        19
586
# define OMAP24XX_DMA_EAC_MD_UL_WR        20
587
# define OMAP24XX_DMA_EAC_MD_DL_RD        21
588
# define OMAP24XX_DMA_EAC_MD_DL_WR        22
589
# define OMAP24XX_DMA_EAC_BT_UL_RD        23
590
# define OMAP24XX_DMA_EAC_BT_UL_WR        24
591
# define OMAP24XX_DMA_EAC_BT_DL_RD        25
592
# define OMAP24XX_DMA_EAC_BT_DL_WR        26
593
# define OMAP24XX_DMA_I2C1_TX                27
594
# define OMAP24XX_DMA_I2C1_RX                28
595
# define OMAP24XX_DMA_I2C2_TX                29
596
# define OMAP24XX_DMA_I2C2_RX                30
597
# define OMAP24XX_DMA_MCBSP1_TX                31
598
# define OMAP24XX_DMA_MCBSP1_RX                32
599
# define OMAP24XX_DMA_MCBSP2_TX                33
600
# define OMAP24XX_DMA_MCBSP2_RX                34
601
# define OMAP24XX_DMA_SPI1_TX0                35
602
# define OMAP24XX_DMA_SPI1_RX0                36
603
# define OMAP24XX_DMA_SPI1_TX1                37
604
# define OMAP24XX_DMA_SPI1_RX1                38
605
# define OMAP24XX_DMA_SPI1_TX2                39
606
# define OMAP24XX_DMA_SPI1_RX2                40
607
# define OMAP24XX_DMA_SPI1_TX3                41
608
# define OMAP24XX_DMA_SPI1_RX3                42
609
# define OMAP24XX_DMA_SPI2_TX0                43
610
# define OMAP24XX_DMA_SPI2_RX0                44
611
# define OMAP24XX_DMA_SPI2_TX1                45
612
# define OMAP24XX_DMA_SPI2_RX1                46
613

    
614
# define OMAP24XX_DMA_UART1_TX                49
615
# define OMAP24XX_DMA_UART1_RX                50
616
# define OMAP24XX_DMA_UART2_TX                51
617
# define OMAP24XX_DMA_UART2_RX                52
618
# define OMAP24XX_DMA_UART3_TX                53
619
# define OMAP24XX_DMA_UART3_RX                54
620
# define OMAP24XX_DMA_USB_W2FC_TX0        55
621
# define OMAP24XX_DMA_USB_W2FC_RX0        56
622
# define OMAP24XX_DMA_USB_W2FC_TX1        57
623
# define OMAP24XX_DMA_USB_W2FC_RX1        58
624
# define OMAP24XX_DMA_USB_W2FC_TX2        59
625
# define OMAP24XX_DMA_USB_W2FC_RX2        60
626
# define OMAP24XX_DMA_MMC1_TX                61
627
# define OMAP24XX_DMA_MMC1_RX                62
628
# define OMAP24XX_DMA_MS                63        /* Not in OMAP2420 */
629
# define OMAP24XX_DMA_EXT_DMAREQ5        64
630

    
631
/* omap[123].c */
632
struct omap_mpu_timer_s;
633
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
634
                qemu_irq irq, omap_clk clk);
635

    
636
struct omap_gp_timer_s;
637
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
638
                qemu_irq irq, omap_clk fclk, omap_clk iclk);
639

    
640
struct omap_watchdog_timer_s;
641
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
642
                qemu_irq irq, omap_clk clk);
643

    
644
struct omap_32khz_timer_s;
645
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
646
                qemu_irq irq, omap_clk clk);
647

    
648
void omap_synctimer_init(struct omap_target_agent_s *ta,
649
                struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
650

    
651
struct omap_tipb_bridge_s;
652
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
653
                qemu_irq abort_irq, omap_clk clk);
654

    
655
struct omap_uart_s;
656
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
657
                qemu_irq irq, omap_clk fclk, omap_clk iclk,
658
                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
659
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
660
                qemu_irq irq, omap_clk fclk, omap_clk iclk,
661
                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
662
void omap_uart_reset(struct omap_uart_s *s);
663

    
664
struct omap_mpuio_s;
665
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
666
                qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
667
                omap_clk clk);
668
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
669
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
670
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
671

    
672
struct omap_gpio_s;
673
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
674
                qemu_irq irq, omap_clk clk);
675
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
676
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
677

    
678
struct omap_gpif_s;
679
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
680
                qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
681
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
682
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
683

    
684
struct uwire_slave_s {
685
    uint16_t (*receive)(void *opaque);
686
    void (*send)(void *opaque, uint16_t data);
687
    void *opaque;
688
};
689
struct omap_uwire_s;
690
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
691
                qemu_irq *irq, qemu_irq dma, omap_clk clk);
692
void omap_uwire_attach(struct omap_uwire_s *s,
693
                struct uwire_slave_s *slave, int chipselect);
694

    
695
struct omap_mcspi_s;
696
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
697
                qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
698
void omap_mcspi_attach(struct omap_mcspi_s *s,
699
                uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
700
                int chipselect);
701

    
702
struct omap_rtc_s;
703
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
704
                qemu_irq *irq, omap_clk clk);
705

    
706
struct i2s_codec_s {
707
    void *opaque;
708

    
709
    /* The CPU can call this if it is generating the clock signal on the
710
     * i2s port.  The CODEC can ignore it if it is set up as a clock
711
     * master and generates its own clock.  */
712
    void (*set_rate)(void *opaque, int in, int out);
713

    
714
    void (*tx_swallow)(void *opaque);
715
    qemu_irq rx_swallow;
716
    qemu_irq tx_start;
717

    
718
    int tx_rate;
719
    int cts;
720
    int rx_rate;
721
    int rts;
722

    
723
    struct i2s_fifo_s {
724
        uint8_t *fifo;
725
        int len;
726
        int start;
727
        int size;
728
    } in, out;
729
};
730
struct omap_mcbsp_s;
731
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
732
                qemu_irq *irq, qemu_irq *dma, omap_clk clk);
733
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
734

    
735
struct omap_lpg_s;
736
struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
737

    
738
void omap_tap_init(struct omap_target_agent_s *ta,
739
                struct omap_mpu_state_s *mpu);
740

    
741
/* omap_lcdc.c */
742
struct omap_lcd_panel_s;
743
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
744
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
745
                struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
746
                ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
747

    
748
/* omap_dss.c */
749
struct rfbi_chip_s {
750
    void *opaque;
751
    void (*write)(void *opaque, int dc, uint16_t value);
752
    void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
753
    uint16_t (*read)(void *opaque, int dc);
754
};
755
struct omap_dss_s;
756
void omap_dss_reset(struct omap_dss_s *s);
757
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
758
                target_phys_addr_t l3_base, DisplayState *ds,
759
                qemu_irq irq, qemu_irq drq,
760
                omap_clk fck1, omap_clk fck2, omap_clk ck54m,
761
                omap_clk ick1, omap_clk ick2);
762
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
763

    
764
/* omap_mmc.c */
765
struct omap_mmc_s;
766
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
767
                BlockDriverState *bd,
768
                qemu_irq irq, qemu_irq dma[], omap_clk clk);
769
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
770
                BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
771
                omap_clk fclk, omap_clk iclk);
772
void omap_mmc_reset(struct omap_mmc_s *s);
773
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
774
void omap_mmc_enable(struct omap_mmc_s *s, int enable);
775

    
776
/* omap_i2c.c */
777
struct omap_i2c_s;
778
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
779
                qemu_irq irq, qemu_irq *dma, omap_clk clk);
780
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
781
                qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
782
void omap_i2c_reset(struct omap_i2c_s *s);
783
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
784

    
785
# define cpu_is_omap310(cpu)                (cpu->mpu_model == omap310)
786
# define cpu_is_omap1510(cpu)                (cpu->mpu_model == omap1510)
787
# define cpu_is_omap1610(cpu)                (cpu->mpu_model == omap1610)
788
# define cpu_is_omap1710(cpu)                (cpu->mpu_model == omap1710)
789
# define cpu_is_omap2410(cpu)                (cpu->mpu_model == omap2410)
790
# define cpu_is_omap2420(cpu)                (cpu->mpu_model == omap2420)
791
# define cpu_is_omap2430(cpu)                (cpu->mpu_model == omap2430)
792
# define cpu_is_omap3430(cpu)                (cpu->mpu_model == omap3430)
793

    
794
# define cpu_is_omap15xx(cpu)                \
795
        (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
796
# define cpu_is_omap16xx(cpu)                \
797
        (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
798
# define cpu_is_omap24xx(cpu)                \
799
        (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
800

    
801
# define cpu_class_omap1(cpu)                \
802
        (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
803
# define cpu_class_omap2(cpu)                cpu_is_omap24xx(cpu)
804
# define cpu_class_omap3(cpu)                cpu_is_omap3430(cpu)
805

    
806
struct omap_mpu_state_s {
807
    enum omap_mpu_model {
808
        omap310,
809
        omap1510,
810
        omap1610,
811
        omap1710,
812
        omap2410,
813
        omap2420,
814
        omap2422,
815
        omap2423,
816
        omap2430,
817
        omap3430,
818
    } mpu_model;
819

    
820
    CPUState *env;
821

    
822
    qemu_irq *irq[2];
823
    qemu_irq *drq;
824

    
825
    qemu_irq wakeup;
826

    
827
    struct omap_dma_port_if_s {
828
        uint32_t (*read[3])(struct omap_mpu_state_s *s,
829
                        target_phys_addr_t offset);
830
        void (*write[3])(struct omap_mpu_state_s *s,
831
                        target_phys_addr_t offset, uint32_t value);
832
        int (*addr_valid)(struct omap_mpu_state_s *s,
833
                        target_phys_addr_t addr);
834
    } port[__omap_dma_port_last];
835

    
836
    unsigned long sdram_size;
837
    unsigned long sram_size;
838

    
839
    /* MPUI-TIPB peripherals */
840
    struct omap_uart_s *uart[3];
841

    
842
    struct omap_gpio_s *gpio;
843

    
844
    struct omap_mcbsp_s *mcbsp1;
845
    struct omap_mcbsp_s *mcbsp3;
846

    
847
    /* MPU public TIPB peripherals */
848
    struct omap_32khz_timer_s *os_timer;
849

    
850
    struct omap_mmc_s *mmc;
851

    
852
    struct omap_mpuio_s *mpuio;
853

    
854
    struct omap_uwire_s *microwire;
855

    
856
    struct {
857
        uint8_t output;
858
        uint8_t level;
859
        uint8_t enable;
860
        int clk;
861
    } pwl;
862

    
863
    struct {
864
        uint8_t frc;
865
        uint8_t vrc;
866
        uint8_t gcr;
867
        omap_clk clk;
868
    } pwt;
869

    
870
    struct omap_i2c_s *i2c[2];
871

    
872
    struct omap_rtc_s *rtc;
873

    
874
    struct omap_mcbsp_s *mcbsp2;
875

    
876
    struct omap_lpg_s *led[2];
877

    
878
    /* MPU private TIPB peripherals */
879
    struct omap_intr_handler_s *ih[2];
880

    
881
    struct omap_dma_s *dma;
882

    
883
    struct omap_mpu_timer_s *timer[3];
884
    struct omap_watchdog_timer_s *wdt;
885

    
886
    struct omap_lcd_panel_s *lcd;
887

    
888
    target_phys_addr_t ulpd_pm_base;
889
    uint32_t ulpd_pm_regs[21];
890
    int64_t ulpd_gauge_start;
891

    
892
    target_phys_addr_t pin_cfg_base;
893
    uint32_t func_mux_ctrl[14];
894
    uint32_t comp_mode_ctrl[1];
895
    uint32_t pull_dwn_ctrl[4];
896
    uint32_t gate_inh_ctrl[1];
897
    uint32_t voltage_ctrl[1];
898
    uint32_t test_dbg_ctrl[1];
899
    uint32_t mod_conf_ctrl[1];
900
    int compat1509;
901

    
902
    uint32_t mpui_ctrl;
903
    target_phys_addr_t mpui_base;
904

    
905
    struct omap_tipb_bridge_s *private_tipb;
906
    struct omap_tipb_bridge_s *public_tipb;
907

    
908
    target_phys_addr_t tcmi_base;
909
    uint32_t tcmi_regs[17];
910

    
911
    struct dpll_ctl_s {
912
        target_phys_addr_t base;
913
        uint16_t mode;
914
        omap_clk dpll;
915
    } dpll[3];
916

    
917
    omap_clk clks;
918
    struct {
919
        target_phys_addr_t mpu_base;
920
        target_phys_addr_t dsp_base;
921

    
922
        int cold_start;
923
        int clocking_scheme;
924
        uint16_t arm_ckctl;
925
        uint16_t arm_idlect1;
926
        uint16_t arm_idlect2;
927
        uint16_t arm_ewupct;
928
        uint16_t arm_rstct1;
929
        uint16_t arm_rstct2;
930
        uint16_t arm_ckout1;
931
        int dpll1_mode;
932
        uint16_t dsp_idlect1;
933
        uint16_t dsp_idlect2;
934
        uint16_t dsp_rstct2;
935
    } clkm;
936

    
937
    /* OMAP2-only peripherals */
938
    struct omap_l4_s *l4;
939

    
940
    struct omap_gp_timer_s *gptimer[12];
941

    
942
    target_phys_addr_t tap_base;
943

    
944
    struct omap_synctimer_s {
945
        target_phys_addr_t base;
946
        uint32_t val;
947
        uint16_t readh;
948
    } synctimer;
949

    
950
    struct omap_prcm_s *prcm;
951
    struct omap_sdrc_s *sdrc;
952
    struct omap_gpmc_s *gpmc;
953
    struct omap_sysctl_s *sysc;
954

    
955
    struct omap_gpif_s *gpif;
956

    
957
    struct omap_mcspi_s *mcspi[2];
958

    
959
    struct omap_dss_s *dss;
960
};
961

    
962
/* omap1.c */
963
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
964
                DisplayState *ds, const char *core);
965

    
966
/* omap2.c */
967
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
968
                DisplayState *ds, const char *core);
969

    
970
# if TARGET_PHYS_ADDR_BITS == 32
971
#  define OMAP_FMT_plx "%#08x"
972
# elif TARGET_PHYS_ADDR_BITS == 64
973
#  define OMAP_FMT_plx "%#08" PRIx64
974
# else
975
#  error TARGET_PHYS_ADDR_BITS undefined
976
# endif
977

    
978
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
979
void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
980
                uint32_t value);
981
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
982
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
983
                uint32_t value);
984
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
985
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
986
                uint32_t value);
987

    
988
void omap_mpu_wakeup(void *opaque, int irq, int req);
989

    
990
# define OMAP_BAD_REG(paddr)                \
991
        fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n",        \
992
                        __FUNCTION__, paddr)
993
# define OMAP_RO_REG(paddr)                \
994
        fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n",        \
995
                        __FUNCTION__, paddr)
996

    
997
/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
998
   (Board-specifc tags are not here)  */
999
#define OMAP_TAG_CLOCK                0x4f01
1000
#define OMAP_TAG_MMC                0x4f02
1001
#define OMAP_TAG_SERIAL_CONSOLE        0x4f03
1002
#define OMAP_TAG_USB                0x4f04
1003
#define OMAP_TAG_LCD                0x4f05
1004
#define OMAP_TAG_GPIO_SWITCH        0x4f06
1005
#define OMAP_TAG_UART                0x4f07
1006
#define OMAP_TAG_FBMEM                0x4f08
1007
#define OMAP_TAG_STI_CONSOLE        0x4f09
1008
#define OMAP_TAG_CAMERA_SENSOR        0x4f0a
1009
#define OMAP_TAG_PARTITION        0x4f0b
1010
#define OMAP_TAG_TEA5761        0x4f10
1011
#define OMAP_TAG_TMP105                0x4f11
1012
#define OMAP_TAG_BOOT_REASON        0x4f80
1013
#define OMAP_TAG_FLASH_PART_STR        0x4f81
1014
#define OMAP_TAG_VERSION_STR        0x4f82
1015

    
1016
enum {
1017
    OMAP_GPIOSW_TYPE_COVER        = 0 << 4,
1018
    OMAP_GPIOSW_TYPE_CONNECTION        = 1 << 4,
1019
    OMAP_GPIOSW_TYPE_ACTIVITY        = 2 << 4,
1020
};
1021

    
1022
#define OMAP_GPIOSW_INVERTED        0x0001
1023
#define OMAP_GPIOSW_OUTPUT        0x0002
1024

    
1025
# define TCMI_VERBOSE                        1
1026
//# define MEM_VERBOSE                        1
1027

    
1028
# ifdef TCMI_VERBOSE
1029
#  define OMAP_8B_REG(paddr)                \
1030
        fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n",        \
1031
                        __FUNCTION__, paddr)
1032
#  define OMAP_16B_REG(paddr)                \
1033
        fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n",        \
1034
                        __FUNCTION__, paddr)
1035
#  define OMAP_32B_REG(paddr)                \
1036
        fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n",        \
1037
                        __FUNCTION__, paddr)
1038
# else
1039
#  define OMAP_8B_REG(paddr)
1040
#  define OMAP_16B_REG(paddr)
1041
#  define OMAP_32B_REG(paddr)
1042
# endif
1043

    
1044
# define OMAP_MPUI_REG_MASK                0x000007ff
1045

    
1046
# ifdef MEM_VERBOSE
1047
struct io_fn {
1048
    CPUReadMemoryFunc **mem_read;
1049
    CPUWriteMemoryFunc **mem_write;
1050
    void *opaque;
1051
    int in;
1052
};
1053

    
1054
static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1055
{
1056
    struct io_fn *s = opaque;
1057
    uint32_t ret;
1058

    
1059
    s->in ++;
1060
    ret = s->mem_read[0](s->opaque, addr);
1061
    s->in --;
1062
    if (!s->in)
1063
        fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1064
    return ret;
1065
}
1066
static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1067
{
1068
    struct io_fn *s = opaque;
1069
    uint32_t ret;
1070

    
1071
    s->in ++;
1072
    ret = s->mem_read[1](s->opaque, addr);
1073
    s->in --;
1074
    if (!s->in)
1075
        fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1076
    return ret;
1077
}
1078
static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1079
{
1080
    struct io_fn *s = opaque;
1081
    uint32_t ret;
1082

    
1083
    s->in ++;
1084
    ret = s->mem_read[2](s->opaque, addr);
1085
    s->in --;
1086
    if (!s->in)
1087
        fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1088
    return ret;
1089
}
1090
static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1091
{
1092
    struct io_fn *s = opaque;
1093

    
1094
    if (!s->in)
1095
        fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1096
    s->in ++;
1097
    s->mem_write[0](s->opaque, addr, value);
1098
    s->in --;
1099
}
1100
static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1101
{
1102
    struct io_fn *s = opaque;
1103

    
1104
    if (!s->in)
1105
        fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1106
    s->in ++;
1107
    s->mem_write[1](s->opaque, addr, value);
1108
    s->in --;
1109
}
1110
static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1111
{
1112
    struct io_fn *s = opaque;
1113

    
1114
    if (!s->in)
1115
        fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1116
    s->in ++;
1117
    s->mem_write[2](s->opaque, addr, value);
1118
    s->in --;
1119
}
1120

    
1121
static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
1122
static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
1123

    
1124
inline static int debug_register_io_memory(int io_index,
1125
                CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
1126
                void *opaque)
1127
{
1128
    struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1129

    
1130
    s->mem_read = mem_read;
1131
    s->mem_write = mem_write;
1132
    s->opaque = opaque;
1133
    s->in = 0;
1134
    return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
1135
}
1136
#  define cpu_register_io_memory        debug_register_io_memory
1137
# endif
1138

    
1139
/* Define when we want to reduce the number of IO regions registered.  */
1140
/*# define L4_MUX_HACK*/
1141

    
1142
# ifdef L4_MUX_HACK
1143
#  undef l4_register_io_memory
1144
int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
1145
                CPUWriteMemoryFunc **mem_write, void *opaque);
1146
# endif
1147

    
1148
#endif /* hw_omap_h */