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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
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* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* Register definitions
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
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"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
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"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
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};
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#endif
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/* Branch registers */
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enum {
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TCG_REG_B0 = 0,
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TCG_REG_B1,
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TCG_REG_B2,
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TCG_REG_B3,
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TCG_REG_B4,
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TCG_REG_B5,
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TCG_REG_B6,
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TCG_REG_B7,
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};
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/* Floating point registers */
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enum {
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TCG_REG_F0 = 0,
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TCG_REG_F1,
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TCG_REG_F2,
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TCG_REG_F3,
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TCG_REG_F4,
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TCG_REG_F5,
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TCG_REG_F6,
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TCG_REG_F7,
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TCG_REG_F8,
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TCG_REG_F9,
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TCG_REG_F10,
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TCG_REG_F11,
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TCG_REG_F12,
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TCG_REG_F13,
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TCG_REG_F14,
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TCG_REG_F15,
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};
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/* Predicate registers */
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enum {
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TCG_REG_P0 = 0,
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TCG_REG_P1,
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TCG_REG_P2,
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TCG_REG_P3,
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TCG_REG_P4,
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TCG_REG_P5,
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TCG_REG_P6,
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TCG_REG_P7,
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TCG_REG_P8,
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TCG_REG_P9,
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TCG_REG_P10,
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TCG_REG_P11,
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TCG_REG_P12,
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TCG_REG_P13,
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TCG_REG_P14,
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TCG_REG_P15,
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};
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/* Application registers */
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enum {
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TCG_REG_PFS = 64,
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};
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static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R34,
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TCG_REG_R35,
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TCG_REG_R36,
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TCG_REG_R37,
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TCG_REG_R38,
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TCG_REG_R39,
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TCG_REG_R40,
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TCG_REG_R41,
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TCG_REG_R42,
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TCG_REG_R43,
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TCG_REG_R44,
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TCG_REG_R45,
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TCG_REG_R46,
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TCG_REG_R47,
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TCG_REG_R48,
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TCG_REG_R49,
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TCG_REG_R50,
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TCG_REG_R51,
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TCG_REG_R52,
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TCG_REG_R53,
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TCG_REG_R54,
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TCG_REG_R55,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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TCG_REG_R27,
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TCG_REG_R28,
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TCG_REG_R29,
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TCG_REG_R30,
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TCG_REG_R31,
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TCG_REG_R56,
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TCG_REG_R57,
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TCG_REG_R58,
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TCG_REG_R59,
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TCG_REG_R60,
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TCG_REG_R61,
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TCG_REG_R62,
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TCG_REG_R63,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11
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};
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static const int tcg_target_call_iarg_regs[8] = {
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TCG_REG_R56,
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TCG_REG_R57,
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TCG_REG_R58,
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TCG_REG_R59,
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TCG_REG_R60,
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TCG_REG_R61,
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TCG_REG_R62,
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TCG_REG_R63,
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};
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static const int tcg_target_call_oarg_regs[2] = {
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TCG_REG_R8,
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TCG_REG_R9
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};
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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return 8;
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}
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/*
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* opcode formation
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*/
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/* bundle templates: stops (double bar in the IA64 manual) are marked with
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an uppercase letter. */
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enum {
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mii = 0x00,
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miI = 0x01,
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mIi = 0x02,
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mII = 0x03,
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mlx = 0x04,
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mLX = 0x05,
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mmi = 0x08,
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mmI = 0x09,
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Mmi = 0x0a,
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MmI = 0x0b,
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mfi = 0x0c,
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mfI = 0x0d,
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mmf = 0x0e,
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mmF = 0x0f,
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mib = 0x10,
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miB = 0x11,
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mbb = 0x12,
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mbB = 0x13,
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bbb = 0x16,
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bbB = 0x17,
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mmb = 0x18,
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mmB = 0x19,
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mfb = 0x1c,
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mfB = 0x1d,
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};
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enum {
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OPC_ADD_A1 = 0x10000000000ull,
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OPC_AND_A1 = 0x10060000000ull,
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OPC_AND_A3 = 0x10160000000ull,
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OPC_ANDCM_A1 = 0x10068000000ull,
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OPC_ANDCM_A3 = 0x10168000000ull,
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OPC_ADDS_A4 = 0x10800000000ull,
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OPC_ADDL_A5 = 0x12000000000ull,
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OPC_ALLOC_M34 = 0x02c00000000ull,
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OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
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OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
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OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
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OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
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OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
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OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
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OPC_CMP_LT_A6 = 0x18000000000ull,
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OPC_CMP_LTU_A6 = 0x1a000000000ull,
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OPC_CMP_EQ_A6 = 0x1c000000000ull,
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OPC_CMP4_LT_A6 = 0x18400000000ull,
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OPC_CMP4_LTU_A6 = 0x1a400000000ull,
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OPC_CMP4_EQ_A6 = 0x1c400000000ull,
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OPC_DEP_Z_I12 = 0x0a600000000ull,
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OPC_EXTR_I11 = 0x0a400002000ull,
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OPC_EXTR_U_I11 = 0x0a400000000ull,
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OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
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OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
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OPC_FCVT_XF_F11 = 0x000e0000000ull,
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OPC_FMA_S1_F1 = 0x10400000000ull,
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OPC_FNMA_S1_F1 = 0x18400000000ull,
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OPC_FRCPA_S1_F6 = 0x00600000000ull,
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OPC_GETF_SIG_M19 = 0x08708000000ull,
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OPC_LD1_M1 = 0x08000000000ull,
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OPC_LD1_M3 = 0x0a000000000ull,
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OPC_LD2_M1 = 0x08040000000ull,
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OPC_LD2_M3 = 0x0a040000000ull,
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OPC_LD4_M1 = 0x08080000000ull,
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OPC_LD4_M3 = 0x0a080000000ull,
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OPC_LD8_M1 = 0x080c0000000ull,
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OPC_LD8_M3 = 0x0a0c0000000ull,
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OPC_MUX1_I3 = 0x0eca0000000ull,
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OPC_NOP_B9 = 0x04008000000ull,
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OPC_NOP_F16 = 0x00008000000ull,
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OPC_NOP_I18 = 0x00008000000ull,
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OPC_NOP_M48 = 0x00008000000ull,
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OPC_MOV_I21 = 0x00e00100000ull,
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OPC_MOV_RET_I21 = 0x00e00500000ull,
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OPC_MOV_I22 = 0x00188000000ull,
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OPC_MOV_I_I26 = 0x00150000000ull,
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OPC_MOVL_X2 = 0x0c000000000ull,
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OPC_OR_A1 = 0x10070000000ull,
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OPC_SETF_EXP_M18 = 0x0c748000000ull,
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OPC_SETF_SIG_M18 = 0x0c708000000ull,
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OPC_SHL_I7 = 0x0f240000000ull,
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OPC_SHR_I5 = 0x0f220000000ull,
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OPC_SHR_U_I5 = 0x0f200000000ull,
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OPC_SHRP_I10 = 0x0ac00000000ull,
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OPC_SXT1_I29 = 0x000a0000000ull,
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OPC_SXT2_I29 = 0x000a8000000ull,
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OPC_SXT4_I29 = 0x000b0000000ull,
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OPC_ST1_M4 = 0x08c00000000ull,
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OPC_ST2_M4 = 0x08c40000000ull,
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OPC_ST4_M4 = 0x08c80000000ull,
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OPC_ST8_M4 = 0x08cc0000000ull,
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OPC_SUB_A1 = 0x10028000000ull,
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OPC_SUB_A3 = 0x10128000000ull,
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OPC_UNPACK4_L_I2 = 0x0f860000000ull,
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OPC_XMA_L_F2 = 0x1d000000000ull,
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OPC_XOR_A1 = 0x10078000000ull,
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OPC_ZXT1_I29 = 0x00080000000ull,
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OPC_ZXT2_I29 = 0x00088000000ull,
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OPC_ZXT4_I29 = 0x00090000000ull,
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};
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static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
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int r2, int r3)
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{
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return opc
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| ((r3 & 0x7f) << 20)
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| ((r2 & 0x7f) << 13)
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| ((r1 & 0x7f) << 6)
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| (qp & 0x3f);
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}
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static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
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uint64_t imm, int r3)
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{
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return opc
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| ((imm & 0x80) << 29) /* s */
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| ((imm & 0x7f) << 13) /* imm7b */
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| ((r3 & 0x7f) << 20)
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| ((r1 & 0x7f) << 6)
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| (qp & 0x3f);
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}
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static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
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uint64_t imm, int r3)
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{
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return opc
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| ((imm & 0x2000) << 23) /* s */
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| ((imm & 0x1f80) << 20) /* imm6d */
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310 |
| ((imm & 0x007f) << 13) /* imm7b */
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| ((r3 & 0x7f) << 20)
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| ((r1 & 0x7f) << 6)
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| (qp & 0x3f);
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}
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315 |
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static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
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317 |
uint64_t imm, int r3)
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318 |
{
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319 |
return opc
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320 |
| ((imm & 0x200000) << 15) /* s */
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321 |
| ((imm & 0x1f0000) << 6) /* imm5c */
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322 |
| ((imm & 0x00ff80) << 20) /* imm9d */
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323 |
| ((imm & 0x00007f) << 13) /* imm7b */
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324 |
| ((r3 & 0x03) << 20)
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325 |
| ((r1 & 0x7f) << 6)
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| (qp & 0x3f);
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327 |
}
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328 |
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329 |
static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
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330 |
int p2, int r2, int r3)
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331 |
{
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332 |
return opc
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333 |
| ((p2 & 0x3f) << 27)
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334 |
| ((r3 & 0x7f) << 20)
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| ((r2 & 0x7f) << 13)
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| ((p1 & 0x3f) << 6)
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| (qp & 0x3f);
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}
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339 |
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340 |
static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
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341 |
{
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342 |
return opc
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343 |
| ((imm & 0x100000) << 16) /* s */
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344 |
| ((imm & 0x0fffff) << 13) /* imm20b */
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| (qp & 0x3f);
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346 |
}
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347 |
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348 |
static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
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349 |
{
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350 |
return opc
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351 |
| ((b2 & 0x7) << 13)
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352 |
| (qp & 0x3f);
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353 |
}
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354 |
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355 |
static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
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356 |
{
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357 |
return opc
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358 |
| ((b2 & 0x7) << 13)
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359 |
| ((b1 & 0x7) << 6)
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360 |
| (qp & 0x3f);
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361 |
}
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362 |
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363 |
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364 |
static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
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|
365 |
{
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366 |
return opc
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367 |
| ((imm & 0x100000) << 16) /* i */
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|
368 |
| ((imm & 0x0fffff) << 6) /* imm20a */
|
|
369 |
| (qp & 0x3f);
|
|
370 |
}
|
|
371 |
|
|
372 |
static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
|
|
373 |
int f3, int f4, int f2)
|
|
374 |
{
|
|
375 |
return opc
|
|
376 |
| ((f4 & 0x7f) << 27)
|
|
377 |
| ((f3 & 0x7f) << 20)
|
|
378 |
| ((f2 & 0x7f) << 13)
|
|
379 |
| ((f1 & 0x7f) << 6)
|
|
380 |
| (qp & 0x3f);
|
|
381 |
}
|
|
382 |
|
|
383 |
static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
|
|
384 |
int f3, int f4, int f2)
|
|
385 |
{
|
|
386 |
return opc
|
|
387 |
| ((f4 & 0x7f) << 27)
|
|
388 |
| ((f3 & 0x7f) << 20)
|
|
389 |
| ((f2 & 0x7f) << 13)
|
|
390 |
| ((f1 & 0x7f) << 6)
|
|
391 |
| (qp & 0x3f);
|
|
392 |
}
|
|
393 |
|
|
394 |
static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
|
|
395 |
int p2, int f2, int f3)
|
|
396 |
{
|
|
397 |
return opc
|
|
398 |
| ((p2 & 0x3f) << 27)
|
|
399 |
| ((f3 & 0x7f) << 20)
|
|
400 |
| ((f2 & 0x7f) << 13)
|
|
401 |
| ((f1 & 0x7f) << 6)
|
|
402 |
| (qp & 0x3f);
|
|
403 |
}
|
|
404 |
|
|
405 |
static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
|
|
406 |
{
|
|
407 |
return opc
|
|
408 |
| ((f2 & 0x7f) << 13)
|
|
409 |
| ((f1 & 0x7f) << 6)
|
|
410 |
| (qp & 0x3f);
|
|
411 |
}
|
|
412 |
|
|
413 |
static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
|
|
414 |
{
|
|
415 |
return opc
|
|
416 |
| ((f2 & 0x7f) << 13)
|
|
417 |
| ((f1 & 0x7f) << 6)
|
|
418 |
| (qp & 0x3f);
|
|
419 |
}
|
|
420 |
|
|
421 |
static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
|
|
422 |
{
|
|
423 |
return opc
|
|
424 |
| ((imm & 0x100000) << 16) /* i */
|
|
425 |
| ((imm & 0x0fffff) << 6) /* imm20a */
|
|
426 |
| (qp & 0x3f);
|
|
427 |
}
|
|
428 |
|
|
429 |
static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
|
|
430 |
int r2, int r3)
|
|
431 |
{
|
|
432 |
return opc
|
|
433 |
| ((r3 & 0x7f) << 20)
|
|
434 |
| ((r2 & 0x7f) << 13)
|
|
435 |
| ((r1 & 0x7f) << 6)
|
|
436 |
| (qp & 0x3f);
|
|
437 |
}
|
|
438 |
|
|
439 |
static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
|
|
440 |
int r2, int mbtype)
|
|
441 |
{
|
|
442 |
return opc
|
|
443 |
| ((mbtype & 0x0f) << 20)
|
|
444 |
| ((r2 & 0x7f) << 13)
|
|
445 |
| ((r1 & 0x7f) << 6)
|
|
446 |
| (qp & 0x3f);
|
|
447 |
}
|
|
448 |
|
|
449 |
static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
|
|
450 |
int r3, int r2)
|
|
451 |
{
|
|
452 |
return opc
|
|
453 |
| ((r3 & 0x7f) << 20)
|
|
454 |
| ((r2 & 0x7f) << 13)
|
|
455 |
| ((r1 & 0x7f) << 6)
|
|
456 |
| (qp & 0x3f);
|
|
457 |
}
|
|
458 |
|
|
459 |
static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
|
|
460 |
int r2, int r3)
|
|
461 |
{
|
|
462 |
return opc
|
|
463 |
| ((r3 & 0x7f) << 20)
|
|
464 |
| ((r2 & 0x7f) << 13)
|
|
465 |
| ((r1 & 0x7f) << 6)
|
|
466 |
| (qp & 0x3f);
|
|
467 |
}
|
|
468 |
|
|
469 |
static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
|
|
470 |
int r2, int r3, uint64_t count)
|
|
471 |
{
|
|
472 |
return opc
|
|
473 |
| ((count & 0x3f) << 27)
|
|
474 |
| ((r3 & 0x7f) << 20)
|
|
475 |
| ((r2 & 0x7f) << 13)
|
|
476 |
| ((r1 & 0x7f) << 6)
|
|
477 |
| (qp & 0x3f);
|
|
478 |
}
|
|
479 |
|
|
480 |
static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
|
|
481 |
int r3, uint64_t pos, uint64_t len)
|
|
482 |
{
|
|
483 |
return opc
|
|
484 |
| ((len & 0x3f) << 27)
|
|
485 |
| ((r3 & 0x7f) << 20)
|
|
486 |
| ((pos & 0x3f) << 14)
|
|
487 |
| ((r1 & 0x7f) << 6)
|
|
488 |
| (qp & 0x3f);
|
|
489 |
}
|
|
490 |
|
|
491 |
static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
|
|
492 |
int r2, uint64_t pos, uint64_t len)
|
|
493 |
{
|
|
494 |
return opc
|
|
495 |
| ((len & 0x3f) << 27)
|
|
496 |
| ((pos & 0x3f) << 20)
|
|
497 |
| ((r2 & 0x7f) << 13)
|
|
498 |
| ((r1 & 0x7f) << 6)
|
|
499 |
| (qp & 0x3f);
|
|
500 |
}
|
|
501 |
|
|
502 |
static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
|
|
503 |
{
|
|
504 |
return opc
|
|
505 |
| ((imm & 0x100000) << 16) /* i */
|
|
506 |
| ((imm & 0x0fffff) << 6) /* imm20a */
|
|
507 |
| (qp & 0x3f);
|
|
508 |
}
|
|
509 |
|
|
510 |
static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
|
|
511 |
int r2, uint64_t imm)
|
|
512 |
{
|
|
513 |
return opc
|
|
514 |
| ((imm & 0x1ff) << 24)
|
|
515 |
| ((r2 & 0x7f) << 13)
|
|
516 |
| ((b1 & 0x7) << 6)
|
|
517 |
| (qp & 0x3f);
|
|
518 |
}
|
|
519 |
|
|
520 |
static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
|
|
521 |
{
|
|
522 |
return opc
|
|
523 |
| ((b2 & 0x7) << 13)
|
|
524 |
| ((r1 & 0x7f) << 6)
|
|
525 |
| (qp & 0x3f);
|
|
526 |
}
|
|
527 |
|
|
528 |
static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
|
|
529 |
{
|
|
530 |
return opc
|
|
531 |
| ((ar3 & 0x7f) << 20)
|
|
532 |
| ((r2 & 0x7f) << 13)
|
|
533 |
| (qp & 0x3f);
|
|
534 |
}
|
|
535 |
|
|
536 |
static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
|
|
537 |
{
|
|
538 |
return opc
|
|
539 |
| ((r3 & 0x7f) << 20)
|
|
540 |
| ((r1 & 0x7f) << 6)
|
|
541 |
| (qp & 0x3f);
|
|
542 |
}
|
|
543 |
|
|
544 |
static inline uint64_t tcg_opc_l2(uint64_t imm)
|
|
545 |
{
|
|
546 |
return (imm & 0x7fffffffffc00000ull) >> 22;
|
|
547 |
}
|
|
548 |
|
|
549 |
static inline uint64_t tcg_opc_l3(uint64_t imm)
|
|
550 |
{
|
|
551 |
return (imm & 0x07fffffffff00000ull) >> 18;
|
|
552 |
}
|
|
553 |
|
|
554 |
static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
|
|
555 |
{
|
|
556 |
return opc
|
|
557 |
| ((r3 & 0x7f) << 20)
|
|
558 |
| ((r1 & 0x7f) << 6)
|
|
559 |
| (qp & 0x3f);
|
|
560 |
}
|
|
561 |
|
|
562 |
static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
|
|
563 |
int r3, uint64_t imm)
|
|
564 |
{
|
|
565 |
return opc
|
|
566 |
| ((imm & 0x100) << 28) /* s */
|
|
567 |
| ((imm & 0x080) << 20) /* i */
|
|
568 |
| ((imm & 0x07f) << 13) /* imm7b */
|
|
569 |
| ((r3 & 0x7f) << 20)
|
|
570 |
| ((r1 & 0x7f) << 6)
|
|
571 |
| (qp & 0x3f);
|
|
572 |
}
|
|
573 |
|
|
574 |
static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
|
|
575 |
{
|
|
576 |
return opc
|
|
577 |
| ((r3 & 0x7f) << 20)
|
|
578 |
| ((r2 & 0x7f) << 13)
|
|
579 |
| (qp & 0x3f);
|
|
580 |
}
|
|
581 |
|
|
582 |
static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
|
|
583 |
{
|
|
584 |
return opc
|
|
585 |
| ((r2 & 0x7f) << 13)
|
|
586 |
| ((f1 & 0x7f) << 6)
|
|
587 |
| (qp & 0x3f);
|
|
588 |
}
|
|
589 |
|
|
590 |
static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
|
|
591 |
{
|
|
592 |
return opc
|
|
593 |
| ((f2 & 0x7f) << 13)
|
|
594 |
| ((r1 & 0x7f) << 6)
|
|
595 |
| (qp & 0x3f);
|
|
596 |
}
|
|
597 |
|
|
598 |
static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
|
|
599 |
int sof, int sol, int sor)
|
|
600 |
{
|
|
601 |
return opc
|
|
602 |
| ((sor & 0x0f) << 27)
|
|
603 |
| ((sol & 0x7f) << 20)
|
|
604 |
| ((sof & 0x7f) << 13)
|
|
605 |
| ((r1 & 0x7f) << 6)
|
|
606 |
| (qp & 0x3f);
|
|
607 |
}
|
|
608 |
|
|
609 |
static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
|
|
610 |
{
|
|
611 |
return opc
|
|
612 |
| ((imm & 0x100000) << 16) /* i */
|
|
613 |
| ((imm & 0x0fffff) << 6) /* imm20a */
|
|
614 |
| (qp & 0x3f);
|
|
615 |
}
|
|
616 |
|
|
617 |
static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
|
|
618 |
int r1, uint64_t imm)
|
|
619 |
{
|
|
620 |
return opc
|
|
621 |
| ((imm & 0x8000000000000000ull) >> 27) /* i */
|
|
622 |
| (imm & 0x0000000000200000ull) /* ic */
|
|
623 |
| ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
|
|
624 |
| ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
|
|
625 |
| ((imm & 0x000000000000007full) << 13) /* imm7b */
|
|
626 |
| ((r1 & 0x7f) << 6)
|
|
627 |
| (qp & 0x3f);
|
|
628 |
}
|
|
629 |
|
|
630 |
static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
|
|
631 |
{
|
|
632 |
return opc
|
|
633 |
| ((imm & 0x0800000000000000ull) >> 23) /* i */
|
|
634 |
| ((imm & 0x00000000000fffffull) << 13) /* imm20b */
|
|
635 |
| (qp & 0x3f);
|
|
636 |
}
|
|
637 |
|
|
638 |
|
|
639 |
/*
|
|
640 |
* Relocations
|
|
641 |
*/
|
|
642 |
|
|
643 |
static inline void reloc_pcrel21b (void *pc, tcg_target_long target)
|
|
644 |
{
|
|
645 |
uint64_t imm;
|
|
646 |
int64_t disp;
|
|
647 |
int slot;
|
|
648 |
|
|
649 |
slot = (tcg_target_long) pc & 3;
|
|
650 |
pc = (void *)((tcg_target_long) pc & ~3);
|
|
651 |
|
|
652 |
disp = target - (tcg_target_long) pc;
|
|
653 |
imm = (uint64_t) disp >> 4;
|
|
654 |
|
|
655 |
switch(slot) {
|
|
656 |
case 0:
|
|
657 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
|
|
658 |
| ((imm & 0x100000) << 21) /* s */
|
|
659 |
| ((imm & 0x0fffff) << 18); /* imm20b */
|
|
660 |
break;
|
|
661 |
case 1:
|
|
662 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
|
|
663 |
| ((imm & 0x100000) >> 2) /* s */
|
|
664 |
| ((imm & 0x0fffe0) >> 5); /* imm20b */
|
|
665 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
|
|
666 |
| ((imm & 0x00001f) << 59); /* imm20b */
|
|
667 |
break;
|
|
668 |
case 2:
|
|
669 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
|
|
670 |
| ((imm & 0x100000) << 39) /* s */
|
|
671 |
| ((imm & 0x0fffff) << 36); /* imm20b */
|
|
672 |
break;
|
|
673 |
}
|
|
674 |
}
|
|
675 |
|
|
676 |
static inline uint64_t get_reloc_pcrel21b (void *pc)
|
|
677 |
{
|
|
678 |
int64_t low, high;
|
|
679 |
int slot;
|
|
680 |
|
|
681 |
slot = (tcg_target_long) pc & 3;
|
|
682 |
pc = (void *)((tcg_target_long) pc & ~3);
|
|
683 |
|
|
684 |
low = (*(uint64_t *)(pc + 0));
|
|
685 |
high = (*(uint64_t *)(pc + 8));
|
|
686 |
|
|
687 |
switch(slot) {
|
|
688 |
case 0:
|
|
689 |
return ((low >> 21) & 0x100000) + /* s */
|
|
690 |
((low >> 18) & 0x0fffff); /* imm20b */
|
|
691 |
case 1:
|
|
692 |
return ((high << 2) & 0x100000) + /* s */
|
|
693 |
((high << 5) & 0x0fffe0) + /* imm20b */
|
|
694 |
((low >> 59) & 0x00001f); /* imm20b */
|
|
695 |
case 2:
|
|
696 |
return ((high >> 39) & 0x100000) + /* s */
|
|
697 |
((high >> 36) & 0x0fffff); /* imm20b */
|
|
698 |
default:
|
|
699 |
tcg_abort();
|
|
700 |
}
|
|
701 |
}
|
|
702 |
|
|
703 |
static inline void reloc_pcrel60b (void *pc, tcg_target_long target)
|
|
704 |
{
|
|
705 |
int64_t disp;
|
|
706 |
uint64_t imm;
|
|
707 |
|
|
708 |
disp = target - (tcg_target_long) pc;
|
|
709 |
imm = (uint64_t) disp >> 4;
|
|
710 |
|
|
711 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
|
|
712 |
| (imm & 0x0800000000000000ull) /* s */
|
|
713 |
| ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
|
|
714 |
| ((imm & 0x00000000000fffffull) << 36); /* imm20b */
|
|
715 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
|
|
716 |
| ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
|
|
717 |
}
|
|
718 |
|
|
719 |
static inline uint64_t get_reloc_pcrel60b (void *pc)
|
|
720 |
{
|
|
721 |
int64_t low, high;
|
|
722 |
|
|
723 |
low = (*(uint64_t *)(pc + 0));
|
|
724 |
high = (*(uint64_t *)(pc + 8));
|
|
725 |
|
|
726 |
return ((high) & 0x0800000000000000ull) + /* s */
|
|
727 |
((high >> 36) & 0x00000000000fffffull) + /* imm20b */
|
|
728 |
((high << 36) & 0x07fffff000000000ull) + /* imm39 */
|
|
729 |
((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
|
|
730 |
}
|
|
731 |
|
|
732 |
|
|
733 |
static void patch_reloc(uint8_t *code_ptr, int type,
|
|
734 |
tcg_target_long value, tcg_target_long addend)
|
|
735 |
{
|
|
736 |
value += addend;
|
|
737 |
switch (type) {
|
|
738 |
case R_IA64_PCREL21B:
|
|
739 |
reloc_pcrel21b(code_ptr, value);
|
|
740 |
break;
|
|
741 |
case R_IA64_PCREL60B:
|
|
742 |
reloc_pcrel60b(code_ptr, value);
|
|
743 |
default:
|
|
744 |
tcg_abort();
|
|
745 |
}
|
|
746 |
}
|
|
747 |
|
|
748 |
/*
|
|
749 |
* Constraints
|
|
750 |
*/
|
|
751 |
|
|
752 |
/* parse target specific constraints */
|
|
753 |
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
754 |
{
|
|
755 |
const char *ct_str;
|
|
756 |
|
|
757 |
ct_str = *pct_str;
|
|
758 |
switch(ct_str[0]) {
|
|
759 |
case 'r':
|
|
760 |
ct->ct |= TCG_CT_REG;
|
|
761 |
tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
|
762 |
break;
|
|
763 |
case 'I':
|
|
764 |
ct->ct |= TCG_CT_CONST_S22;
|
|
765 |
break;
|
|
766 |
case 'S':
|
|
767 |
ct->ct |= TCG_CT_REG;
|
|
768 |
tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
|
769 |
#if defined(CONFIG_SOFTMMU)
|
|
770 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
|
|
771 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
|
|
772 |
#endif
|
|
773 |
break;
|
|
774 |
case 'Z':
|
|
775 |
/* We are cheating a bit here, using the fact that the register
|
|
776 |
r0 is also the register number 0. Hence there is no need
|
|
777 |
to check for const_args in each instruction. */
|
|
778 |
ct->ct |= TCG_CT_CONST_ZERO;
|
|
779 |
break;
|
|
780 |
default:
|
|
781 |
return -1;
|
|
782 |
}
|
|
783 |
ct_str++;
|
|
784 |
*pct_str = ct_str;
|
|
785 |
return 0;
|
|
786 |
}
|
|
787 |
|
|
788 |
/* test if a constant matches the constraint */
|
|
789 |
static inline int tcg_target_const_match(tcg_target_long val,
|
|
790 |
const TCGArgConstraint *arg_ct)
|
|
791 |
{
|
|
792 |
int ct;
|
|
793 |
ct = arg_ct->ct;
|
|
794 |
if (ct & TCG_CT_CONST)
|
|
795 |
return 1;
|
|
796 |
else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
|
|
797 |
return 1;
|
|
798 |
else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
|
|
799 |
return 1;
|
|
800 |
else
|
|
801 |
return 0;
|
|
802 |
}
|
|
803 |
|
|
804 |
/*
|
|
805 |
* Code generation
|
|
806 |
*/
|
|
807 |
|
|
808 |
static uint8_t *tb_ret_addr;
|
|
809 |
|
|
810 |
static inline void tcg_out_bundle(TCGContext *s, int template,
|
|
811 |
uint64_t slot0, uint64_t slot1,
|
|
812 |
uint64_t slot2)
|
|
813 |
{
|
|
814 |
template &= 0x1f; /* 5 bits */
|
|
815 |
slot0 &= 0x1ffffffffffull; /* 41 bits */
|
|
816 |
slot1 &= 0x1ffffffffffull; /* 41 bits */
|
|
817 |
slot2 &= 0x1ffffffffffull; /* 41 bits */
|
|
818 |
|
|
819 |
*(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
|
|
820 |
*(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
|
|
821 |
s->code_ptr += 16;
|
|
822 |
}
|
|
823 |
|
|
824 |
static inline void tcg_out_mov(TCGContext *s, TCGArg ret, TCGArg arg)
|
|
825 |
{
|
|
826 |
tcg_out_bundle(s, mmI,
|
|
827 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
828 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
829 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
|
|
830 |
}
|
|
831 |
|
|
832 |
static inline void tcg_out_movi(TCGContext *s, TCGType type,
|
|
833 |
TCGArg reg, tcg_target_long arg)
|
|
834 |
{
|
|
835 |
tcg_out_bundle(s, mLX,
|
|
836 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
837 |
tcg_opc_l2 (arg),
|
|
838 |
tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
|
|
839 |
}
|
|
840 |
|
|
841 |
static inline void tcg_out_addi(TCGContext *s, TCGArg reg, tcg_target_long val)
|
|
842 |
{
|
|
843 |
if (val == ((int32_t)val << 10) >> 10) {
|
|
844 |
tcg_out_bundle(s, MmI,
|
|
845 |
tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
|
|
846 |
TCG_REG_R2, val, TCG_REG_R0),
|
|
847 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
848 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg,
|
|
849 |
reg, TCG_REG_R2));
|
|
850 |
} else {
|
|
851 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, val);
|
|
852 |
tcg_out_bundle(s, mmI,
|
|
853 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
854 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
855 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg,
|
|
856 |
reg, TCG_REG_R2));
|
|
857 |
}
|
|
858 |
}
|
|
859 |
|
|
860 |
static void tcg_out_br(TCGContext *s, int label_index)
|
|
861 |
{
|
|
862 |
TCGLabel *l = &s->labels[label_index];
|
|
863 |
|
|
864 |
tcg_out_bundle(s, mmB,
|
|
865 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
866 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
867 |
tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
|
|
868 |
get_reloc_pcrel21b(s->code_ptr + 2)));
|
|
869 |
|
|
870 |
if (l->has_value) {
|
|
871 |
reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
|
|
872 |
} else {
|
|
873 |
tcg_out_reloc(s, (s->code_ptr - 16) + 2,
|
|
874 |
R_IA64_PCREL21B, label_index, 0);
|
|
875 |
}
|
|
876 |
}
|
|
877 |
|
|
878 |
static inline void tcg_out_call(TCGContext *s, TCGArg addr)
|
|
879 |
{
|
|
880 |
tcg_out_bundle(s, MmI,
|
|
881 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
|
|
882 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
|
|
883 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
|
|
884 |
TCG_REG_B6, TCG_REG_R2, 0));
|
|
885 |
tcg_out_bundle(s, mmB,
|
|
886 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
|
|
887 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
888 |
tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
|
|
889 |
TCG_REG_B0, TCG_REG_B6));
|
|
890 |
}
|
|
891 |
|
|
892 |
static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
|
|
893 |
{
|
|
894 |
int64_t disp;
|
|
895 |
uint64_t imm;
|
|
896 |
|
|
897 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
|
|
898 |
|
|
899 |
disp = tb_ret_addr - s->code_ptr;
|
|
900 |
imm = (uint64_t)disp >> 4;
|
|
901 |
|
|
902 |
tcg_out_bundle(s, mLX,
|
|
903 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
904 |
tcg_opc_l3 (imm),
|
|
905 |
tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
|
|
906 |
}
|
|
907 |
|
|
908 |
static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
|
|
909 |
{
|
|
910 |
if (s->tb_jmp_offset) {
|
|
911 |
/* direct jump method */
|
|
912 |
tcg_abort();
|
|
913 |
} else {
|
|
914 |
/* indirect jump method */
|
|
915 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
|
|
916 |
(tcg_target_long)(s->tb_next + arg));
|
|
917 |
tcg_out_bundle(s, MmI,
|
|
918 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
|
|
919 |
TCG_REG_R2, TCG_REG_R2),
|
|
920 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
921 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
|
|
922 |
TCG_REG_R2, 0));
|
|
923 |
tcg_out_bundle(s, mmB,
|
|
924 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
925 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
926 |
tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
|
|
927 |
TCG_REG_B6));
|
|
928 |
}
|
|
929 |
s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
|
|
930 |
}
|
|
931 |
|
|
932 |
static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
|
|
933 |
{
|
|
934 |
tcg_out_bundle(s, mmI,
|
|
935 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
936 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
937 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
|
|
938 |
tcg_out_bundle(s, mmB,
|
|
939 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
940 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
941 |
tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
|
|
942 |
}
|
|
943 |
|
|
944 |
static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
|
|
945 |
TCGArg arg1, tcg_target_long arg2)
|
|
946 |
{
|
|
947 |
if (arg2 == ((int16_t)arg2 >> 2) << 2) {
|
|
948 |
tcg_out_bundle(s, MmI,
|
|
949 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
|
|
950 |
TCG_REG_R2, arg2, arg1),
|
|
951 |
tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
|
|
952 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
|
953 |
} else {
|
|
954 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
|
|
955 |
tcg_out_bundle(s, MmI,
|
|
956 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
|
|
957 |
TCG_REG_R2, TCG_REG_R2, arg1),
|
|
958 |
tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
|
|
959 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
|
960 |
}
|
|
961 |
}
|
|
962 |
|
|
963 |
static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
|
|
964 |
TCGArg arg1, tcg_target_long arg2)
|
|
965 |
{
|
|
966 |
if (arg2 == ((int16_t)arg2 >> 2) << 2) {
|
|
967 |
tcg_out_bundle(s, MmI,
|
|
968 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
|
|
969 |
TCG_REG_R2, arg2, arg1),
|
|
970 |
tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
|
|
971 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
|
972 |
} else {
|
|
973 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
|
|
974 |
tcg_out_bundle(s, MmI,
|
|
975 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
|
|
976 |
TCG_REG_R2, TCG_REG_R2, arg1),
|
|
977 |
tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
|
|
978 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
|
979 |
}
|
|
980 |
}
|
|
981 |
|
|
982 |
static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGArg arg,
|
|
983 |
TCGArg arg1, tcg_target_long arg2)
|
|
984 |
{
|
|
985 |
if (type == TCG_TYPE_I32) {
|
|
986 |
tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
|
|
987 |
} else {
|
|
988 |
tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
|
|
989 |
}
|
|
990 |
}
|
|
991 |
|
|
992 |
static inline void tcg_out_st(TCGContext *s, TCGType type, TCGArg arg,
|
|
993 |
TCGArg arg1, tcg_target_long arg2)
|
|
994 |
{
|
|
995 |
if (type == TCG_TYPE_I32) {
|
|
996 |
tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
|
|
997 |
} else {
|
|
998 |
tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
|
|
999 |
}
|
|
1000 |
}
|
|
1001 |
|
|
1002 |
static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
|
|
1003 |
TCGArg arg1, int const_arg1,
|
|
1004 |
TCGArg arg2, int const_arg2)
|
|
1005 |
{
|
|
1006 |
uint64_t opc1, opc2;
|
|
1007 |
|
|
1008 |
if (const_arg1 && arg1 != 0) {
|
|
1009 |
opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
|
|
1010 |
TCG_REG_R2, arg1, TCG_REG_R0);
|
|
1011 |
arg1 = TCG_REG_R2;
|
|
1012 |
} else {
|
|
1013 |
opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
|
1014 |
}
|
|
1015 |
|
|
1016 |
if (const_arg2 && arg2 != 0) {
|
|
1017 |
opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
|
|
1018 |
TCG_REG_R3, arg2, TCG_REG_R0);
|
|
1019 |
arg2 = TCG_REG_R3;
|
|
1020 |
} else {
|
|
1021 |
opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
|
|
1022 |
}
|
|
1023 |
|
|
1024 |
tcg_out_bundle(s, mII,
|
|
1025 |
opc1,
|
|
1026 |
opc2,
|
|
1027 |
tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
|
|
1028 |
}
|
|
1029 |
|
|
1030 |
static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
|
|
1031 |
TCGArg arg1, int const_arg1,
|
|
1032 |
TCGArg arg2, int const_arg2)
|
|
1033 |
{
|
|
1034 |
tcg_out_bundle(s, mII,
|
|
1035 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1036 |
tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
|
|
1037 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
|
1038 |
}
|
|
1039 |
|
|
1040 |
static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
|
|
1041 |
TCGArg arg1, int const_arg1,
|
|
1042 |
TCGArg arg2, int const_arg2)
|
|
1043 |
{
|
|
1044 |
tcg_out_bundle(s, mII,
|
|
1045 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1046 |
tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
|
|
1047 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
|
1048 |
}
|
|
1049 |
|
|
1050 |
static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
|
|
1051 |
TCGArg arg1, int const_arg1,
|
|
1052 |
TCGArg arg2, int const_arg2)
|
|
1053 |
{
|
|
1054 |
tcg_out_bundle(s, mII,
|
|
1055 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1056 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
|
|
1057 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
|
1058 |
}
|
|
1059 |
|
|
1060 |
static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
|
|
1061 |
TCGArg arg1, int const_arg1,
|
|
1062 |
TCGArg arg2, int const_arg2)
|
|
1063 |
{
|
|
1064 |
tcg_out_bundle(s, mII,
|
|
1065 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1066 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
|
|
1067 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
|
|
1068 |
}
|
|
1069 |
|
|
1070 |
static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
|
|
1071 |
TCGArg arg1, TCGArg arg2)
|
|
1072 |
{
|
|
1073 |
tcg_out_bundle(s, mmI,
|
|
1074 |
tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
|
|
1075 |
tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
|
|
1076 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
|
1077 |
tcg_out_bundle(s, mmF,
|
|
1078 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1079 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1080 |
tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
|
|
1081 |
TCG_REG_F7, TCG_REG_F0));
|
|
1082 |
tcg_out_bundle(s, miI,
|
|
1083 |
tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
|
|
1084 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1085 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
|
1086 |
}
|
|
1087 |
|
|
1088 |
static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1089 |
TCGArg arg2, int const_arg2)
|
|
1090 |
{
|
|
1091 |
if (const_arg2) {
|
|
1092 |
tcg_out_bundle(s, miI,
|
|
1093 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1094 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1095 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
|
|
1096 |
ret, arg1, arg2, 31 - arg2));
|
|
1097 |
} else {
|
|
1098 |
tcg_out_bundle(s, mII,
|
|
1099 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
|
|
1100 |
TCG_REG_R3, 0x1f, arg2),
|
|
1101 |
tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
|
|
1102 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
|
|
1103 |
TCG_REG_R2, TCG_REG_R3));
|
|
1104 |
}
|
|
1105 |
}
|
|
1106 |
|
|
1107 |
static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1108 |
TCGArg arg2, int const_arg2)
|
|
1109 |
{
|
|
1110 |
if (const_arg2) {
|
|
1111 |
tcg_out_bundle(s, miI,
|
|
1112 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1113 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1114 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
|
|
1115 |
ret, arg1, arg2, 63 - arg2));
|
|
1116 |
} else {
|
|
1117 |
tcg_out_bundle(s, miI,
|
|
1118 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1119 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1120 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
|
|
1121 |
}
|
|
1122 |
}
|
|
1123 |
|
|
1124 |
static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1125 |
TCGArg arg2, int const_arg2)
|
|
1126 |
{
|
|
1127 |
if (const_arg2) {
|
|
1128 |
tcg_out_bundle(s, miI,
|
|
1129 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1130 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1131 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
|
|
1132 |
arg1, 63 - arg2, 31 - arg2));
|
|
1133 |
} else {
|
|
1134 |
tcg_out_bundle(s, mII,
|
|
1135 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1136 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
|
|
1137 |
0x1f, arg2),
|
|
1138 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
|
|
1139 |
arg1, TCG_REG_R2));
|
|
1140 |
}
|
|
1141 |
}
|
|
1142 |
|
|
1143 |
static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1144 |
TCGArg arg2, int const_arg2)
|
|
1145 |
{
|
|
1146 |
if (const_arg2) {
|
|
1147 |
tcg_out_bundle(s, miI,
|
|
1148 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1149 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1150 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
|
|
1151 |
arg1, 63 - arg2, 63 - arg2));
|
|
1152 |
} else {
|
|
1153 |
tcg_out_bundle(s, miI,
|
|
1154 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1155 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1156 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
|
|
1157 |
arg1, arg2));
|
|
1158 |
}
|
|
1159 |
}
|
|
1160 |
|
|
1161 |
static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1162 |
TCGArg arg2, int const_arg2)
|
|
1163 |
{
|
|
1164 |
if (const_arg2) {
|
|
1165 |
tcg_out_bundle(s, miI,
|
|
1166 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1167 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1168 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
|
|
1169 |
arg1, arg2, 31 - arg2));
|
|
1170 |
} else {
|
|
1171 |
tcg_out_bundle(s, mII,
|
|
1172 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
|
|
1173 |
0x1f, arg2),
|
|
1174 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
|
|
1175 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
|
|
1176 |
TCG_REG_R2, TCG_REG_R3));
|
|
1177 |
}
|
|
1178 |
}
|
|
1179 |
|
|
1180 |
static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1181 |
TCGArg arg2, int const_arg2)
|
|
1182 |
{
|
|
1183 |
if (const_arg2) {
|
|
1184 |
tcg_out_bundle(s, miI,
|
|
1185 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1186 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1187 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
|
|
1188 |
arg1, arg2, 63 - arg2));
|
|
1189 |
} else {
|
|
1190 |
tcg_out_bundle(s, miI,
|
|
1191 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1192 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1193 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
|
|
1194 |
arg1, arg2));
|
|
1195 |
}
|
|
1196 |
}
|
|
1197 |
|
|
1198 |
static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1199 |
TCGArg arg2, int const_arg2)
|
|
1200 |
{
|
|
1201 |
if (const_arg2) {
|
|
1202 |
tcg_out_bundle(s, mII,
|
|
1203 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1204 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
|
|
1205 |
TCG_REG_R2, arg1, arg1),
|
|
1206 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
|
|
1207 |
TCG_REG_R2, 32 - arg2, 31));
|
|
1208 |
} else {
|
|
1209 |
tcg_out_bundle(s, miI,
|
|
1210 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1211 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
|
|
1212 |
TCG_REG_R2, arg1, arg1),
|
|
1213 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
|
|
1214 |
0x1f, arg2));
|
|
1215 |
tcg_out_bundle(s, mII,
|
|
1216 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1217 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
|
|
1218 |
0x20, TCG_REG_R3),
|
|
1219 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
|
|
1220 |
TCG_REG_R2, TCG_REG_R3));
|
|
1221 |
}
|
|
1222 |
}
|
|
1223 |
|
|
1224 |
static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1225 |
TCGArg arg2, int const_arg2)
|
|
1226 |
{
|
|
1227 |
if (const_arg2) {
|
|
1228 |
tcg_out_bundle(s, miI,
|
|
1229 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1230 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1231 |
tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
|
|
1232 |
arg1, 0x40 - arg2));
|
|
1233 |
} else {
|
|
1234 |
tcg_out_bundle(s, mII,
|
|
1235 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
|
|
1236 |
0x40, arg2),
|
|
1237 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
|
|
1238 |
arg1, arg2),
|
|
1239 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
|
|
1240 |
arg1, TCG_REG_R2));
|
|
1241 |
tcg_out_bundle(s, miI,
|
|
1242 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1243 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1244 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
|
|
1245 |
TCG_REG_R2, TCG_REG_R3));
|
|
1246 |
}
|
|
1247 |
}
|
|
1248 |
|
|
1249 |
static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1250 |
TCGArg arg2, int const_arg2)
|
|
1251 |
{
|
|
1252 |
if (const_arg2) {
|
|
1253 |
tcg_out_bundle(s, mII,
|
|
1254 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1255 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
|
|
1256 |
TCG_REG_R2, arg1, arg1),
|
|
1257 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
|
|
1258 |
TCG_REG_R2, arg2, 31));
|
|
1259 |
} else {
|
|
1260 |
tcg_out_bundle(s, mII,
|
|
1261 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
|
|
1262 |
0x1f, arg2),
|
|
1263 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
|
|
1264 |
TCG_REG_R2, arg1, arg1),
|
|
1265 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
|
|
1266 |
TCG_REG_R2, TCG_REG_R3));
|
|
1267 |
}
|
|
1268 |
}
|
|
1269 |
|
|
1270 |
static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
|
|
1271 |
TCGArg arg2, int const_arg2)
|
|
1272 |
{
|
|
1273 |
if (const_arg2) {
|
|
1274 |
tcg_out_bundle(s, miI,
|
|
1275 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1276 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1277 |
tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
|
|
1278 |
arg1, arg2));
|
|
1279 |
} else {
|
|
1280 |
tcg_out_bundle(s, mII,
|
|
1281 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
|
|
1282 |
0x40, arg2),
|
|
1283 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
|
|
1284 |
arg1, arg2),
|
|
1285 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
|
|
1286 |
arg1, TCG_REG_R2));
|
|
1287 |
tcg_out_bundle(s, miI,
|
|
1288 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1289 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1290 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
|
|
1291 |
TCG_REG_R2, TCG_REG_R3));
|
|
1292 |
}
|
|
1293 |
}
|
|
1294 |
|
|
1295 |
static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
|
|
1296 |
TCGArg ret, TCGArg arg)
|
|
1297 |
{
|
|
1298 |
tcg_out_bundle(s, miI,
|
|
1299 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1300 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1301 |
tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
|
|
1302 |
}
|
|
1303 |
|
|
1304 |
static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
|
|
1305 |
{
|
|
1306 |
tcg_out_bundle(s, mII,
|
|
1307 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1308 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
|
|
1309 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
|
1310 |
}
|
|
1311 |
|
|
1312 |
static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
|
|
1313 |
{
|
|
1314 |
tcg_out_bundle(s, mII,
|
|
1315 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1316 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
|
|
1317 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
|
1318 |
}
|
|
1319 |
|
|
1320 |
static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
|
|
1321 |
{
|
|
1322 |
tcg_out_bundle(s, mII,
|
|
1323 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
1324 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
|
1325 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
|
|
1326 |
}
|
|
1327 |
|
|
1328 |
static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
|
|
1329 |
TCGArg arg2, int cmp4)
|
|
1330 |
{
|
|
1331 |
uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
|
|
1332 |
|
|
1333 |
if (cmp4) {
|
|
1334 |
opc_eq_a6 = OPC_CMP4_EQ_A6;
|
|
1335 |
opc_lt_a6 = OPC_CMP4_LT_A6;
|
|
1336 |
opc_ltu_a6 = OPC_CMP4_LTU_A6;
|
|
1337 |
} else {
|
|
1338 |
opc_eq_a6 = OPC_CMP_EQ_A6;
|
|
1339 |
opc_lt_a6 = OPC_CMP_LT_A6;
|
|
1340 |
opc_ltu_a6 = OPC_CMP_LTU_A6;
|
|
1341 |
}
|
|
1342 |
|
|
1343 |
switch (cond) {
|
|
1344 |
case TCG_COND_EQ:
|
|
1345 |
return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
|
1346 |
case TCG_COND_NE:
|
|
1347 |
return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
|
1348 |
case TCG_COND_LT:
|
|
1349 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
|
1350 |
case TCG_COND_LTU:
|
|
1351 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
|
1352 |
case TCG_COND_GE:
|
|
1353 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
|
1354 |
case TCG_COND_GEU:
|
|
1355 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
|
1356 |
case TCG_COND_LE:
|
|
1357 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
|
1358 |
case TCG_COND_LEU:
|
|
1359 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
|
1360 |
case TCG_COND_GT:
|
|
1361 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
|
1362 |
case TCG_COND_GTU:
|
|
1363 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
|
1364 |
default:
|
|
1365 |
tcg_abort();
|
|
1366 |
break;
|
|
1367 |
}
|
|
1368 |
}
|
|
1369 |
|
|
1370 |
static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
|
|
1371 |
int const_arg1, TCGArg arg2, int const_arg2,
|
|
1372 |
int label_index, int cmp4)
|
|
1373 |
{
|
|
1374 |
TCGLabel *l = &s->labels[label_index];
|
|
1375 |
uint64_t opc1, opc2;
|
|
1376 |
|
|
1377 |
if (const_arg1 && arg1 != 0) {
|
|
1378 |
opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
|
|
1379 |
arg1, TCG_REG_R0);
|
|
1380 |
arg1 = TCG_REG_R2;
|