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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
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* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* Register definitions
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
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"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", |
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"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", |
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}; |
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#endif
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/* Branch registers */
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enum {
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TCG_REG_B0 = 0,
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TCG_REG_B1, |
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TCG_REG_B2, |
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TCG_REG_B3, |
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TCG_REG_B4, |
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TCG_REG_B5, |
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TCG_REG_B6, |
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TCG_REG_B7, |
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}; |
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|
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/* Floating point registers */
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enum {
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TCG_REG_F0 = 0,
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TCG_REG_F1, |
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TCG_REG_F2, |
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TCG_REG_F3, |
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TCG_REG_F4, |
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TCG_REG_F5, |
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TCG_REG_F6, |
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TCG_REG_F7, |
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TCG_REG_F8, |
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TCG_REG_F9, |
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TCG_REG_F10, |
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TCG_REG_F11, |
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TCG_REG_F12, |
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TCG_REG_F13, |
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TCG_REG_F14, |
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TCG_REG_F15, |
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}; |
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/* Predicate registers */
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enum {
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TCG_REG_P0 = 0,
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TCG_REG_P1, |
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TCG_REG_P2, |
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TCG_REG_P3, |
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TCG_REG_P4, |
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TCG_REG_P5, |
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TCG_REG_P6, |
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TCG_REG_P7, |
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TCG_REG_P8, |
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TCG_REG_P9, |
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TCG_REG_P10, |
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TCG_REG_P11, |
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TCG_REG_P12, |
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TCG_REG_P13, |
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TCG_REG_P14, |
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TCG_REG_P15, |
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}; |
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|
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/* Application registers */
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enum {
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TCG_REG_PFS = 64,
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}; |
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_R34, |
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TCG_REG_R35, |
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TCG_REG_R36, |
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TCG_REG_R37, |
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TCG_REG_R38, |
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TCG_REG_R39, |
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TCG_REG_R40, |
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TCG_REG_R41, |
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TCG_REG_R42, |
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TCG_REG_R43, |
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TCG_REG_R44, |
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TCG_REG_R45, |
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TCG_REG_R46, |
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TCG_REG_R47, |
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TCG_REG_R48, |
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TCG_REG_R49, |
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TCG_REG_R50, |
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TCG_REG_R51, |
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TCG_REG_R52, |
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TCG_REG_R53, |
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TCG_REG_R54, |
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TCG_REG_R55, |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R24, |
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TCG_REG_R25, |
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TCG_REG_R26, |
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TCG_REG_R27, |
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31, |
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TCG_REG_R56, |
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TCG_REG_R57, |
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TCG_REG_R58, |
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TCG_REG_R59, |
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TCG_REG_R60, |
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TCG_REG_R61, |
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TCG_REG_R62, |
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TCG_REG_R63, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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TCG_REG_R11 |
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}; |
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static const int tcg_target_call_iarg_regs[8] = { |
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TCG_REG_R56, |
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TCG_REG_R57, |
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TCG_REG_R58, |
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TCG_REG_R59, |
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TCG_REG_R60, |
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TCG_REG_R61, |
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TCG_REG_R62, |
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TCG_REG_R63, |
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}; |
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_R8, |
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TCG_REG_R9 |
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}; |
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags) |
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{ |
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return 8; |
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} |
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/*
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* opcode formation
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*/
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/* bundle templates: stops (double bar in the IA64 manual) are marked with
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an uppercase letter. */
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enum {
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mii = 0x00,
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miI = 0x01,
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mIi = 0x02,
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mII = 0x03,
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mlx = 0x04,
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mLX = 0x05,
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mmi = 0x08,
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mmI = 0x09,
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Mmi = 0x0a,
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MmI = 0x0b,
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mfi = 0x0c,
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mfI = 0x0d,
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mmf = 0x0e,
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mmF = 0x0f,
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mib = 0x10,
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miB = 0x11,
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mbb = 0x12,
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mbB = 0x13,
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bbb = 0x16,
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bbB = 0x17,
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mmb = 0x18,
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mmB = 0x19,
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mfb = 0x1c,
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mfB = 0x1d,
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}; |
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enum {
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OPC_ADD_A1 = 0x10000000000ull,
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OPC_AND_A1 = 0x10060000000ull,
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OPC_AND_A3 = 0x10160000000ull,
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OPC_ANDCM_A1 = 0x10068000000ull,
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OPC_ANDCM_A3 = 0x10168000000ull,
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OPC_ADDS_A4 = 0x10800000000ull,
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OPC_ADDL_A5 = 0x12000000000ull,
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OPC_ALLOC_M34 = 0x02c00000000ull,
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OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
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OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
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OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
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OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
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OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
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OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
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OPC_CMP_LT_A6 = 0x18000000000ull,
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OPC_CMP_LTU_A6 = 0x1a000000000ull,
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OPC_CMP_EQ_A6 = 0x1c000000000ull,
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OPC_CMP4_LT_A6 = 0x18400000000ull,
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OPC_CMP4_LTU_A6 = 0x1a400000000ull,
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OPC_CMP4_EQ_A6 = 0x1c400000000ull,
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OPC_DEP_Z_I12 = 0x0a600000000ull,
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OPC_EXTR_I11 = 0x0a400002000ull,
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OPC_EXTR_U_I11 = 0x0a400000000ull,
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OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
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OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
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OPC_FCVT_XF_F11 = 0x000e0000000ull,
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OPC_FMA_S1_F1 = 0x10400000000ull,
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OPC_FNMA_S1_F1 = 0x18400000000ull,
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OPC_FRCPA_S1_F6 = 0x00600000000ull,
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OPC_GETF_SIG_M19 = 0x08708000000ull,
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OPC_LD1_M1 = 0x08000000000ull,
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OPC_LD1_M3 = 0x0a000000000ull,
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OPC_LD2_M1 = 0x08040000000ull,
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OPC_LD2_M3 = 0x0a040000000ull,
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OPC_LD4_M1 = 0x08080000000ull,
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OPC_LD4_M3 = 0x0a080000000ull,
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OPC_LD8_M1 = 0x080c0000000ull,
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OPC_LD8_M3 = 0x0a0c0000000ull,
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OPC_MUX1_I3 = 0x0eca0000000ull,
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OPC_NOP_B9 = 0x04008000000ull,
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OPC_NOP_F16 = 0x00008000000ull,
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OPC_NOP_I18 = 0x00008000000ull,
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OPC_NOP_M48 = 0x00008000000ull,
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OPC_MOV_I21 = 0x00e00100000ull,
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OPC_MOV_RET_I21 = 0x00e00500000ull,
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OPC_MOV_I22 = 0x00188000000ull,
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OPC_MOV_I_I26 = 0x00150000000ull,
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OPC_MOVL_X2 = 0x0c000000000ull,
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OPC_OR_A1 = 0x10070000000ull,
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OPC_SETF_EXP_M18 = 0x0c748000000ull,
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OPC_SETF_SIG_M18 = 0x0c708000000ull,
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OPC_SHL_I7 = 0x0f240000000ull,
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OPC_SHR_I5 = 0x0f220000000ull,
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OPC_SHR_U_I5 = 0x0f200000000ull,
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OPC_SHRP_I10 = 0x0ac00000000ull,
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OPC_SXT1_I29 = 0x000a0000000ull,
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OPC_SXT2_I29 = 0x000a8000000ull,
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OPC_SXT4_I29 = 0x000b0000000ull,
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OPC_ST1_M4 = 0x08c00000000ull,
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OPC_ST2_M4 = 0x08c40000000ull,
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OPC_ST4_M4 = 0x08c80000000ull,
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OPC_ST8_M4 = 0x08cc0000000ull,
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OPC_SUB_A1 = 0x10028000000ull,
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OPC_SUB_A3 = 0x10128000000ull,
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OPC_UNPACK4_L_I2 = 0x0f860000000ull,
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OPC_XMA_L_F2 = 0x1d000000000ull,
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OPC_XOR_A1 = 0x10078000000ull,
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OPC_ZXT1_I29 = 0x00080000000ull,
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OPC_ZXT2_I29 = 0x00088000000ull,
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OPC_ZXT4_I29 = 0x00090000000ull,
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}; |
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static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1, |
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int r2, int r3) |
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{ |
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return opc
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| ((r3 & 0x7f) << 20) |
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| ((r2 & 0x7f) << 13) |
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| ((r1 & 0x7f) << 6) |
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| (qp & 0x3f);
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} |
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static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1, |
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uint64_t imm, int r3)
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{ |
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return opc
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| ((imm & 0x80) << 29) /* s */ |
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| ((imm & 0x7f) << 13) /* imm7b */ |
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| ((r3 & 0x7f) << 20) |
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| ((r1 & 0x7f) << 6) |
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| (qp & 0x3f);
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} |
303 |
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static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1, |
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uint64_t imm, int r3)
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{ |
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return opc
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| ((imm & 0x2000) << 23) /* s */ |
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| ((imm & 0x1f80) << 20) /* imm6d */ |
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| ((imm & 0x007f) << 13) /* imm7b */ |
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| ((r3 & 0x7f) << 20) |
312 |
| ((r1 & 0x7f) << 6) |
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| (qp & 0x3f);
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} |
315 |
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static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1, |
317 |
uint64_t imm, int r3)
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{ |
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return opc
|
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| ((imm & 0x200000) << 15) /* s */ |
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| ((imm & 0x1f0000) << 6) /* imm5c */ |
322 |
| ((imm & 0x00ff80) << 20) /* imm9d */ |
323 |
| ((imm & 0x00007f) << 13) /* imm7b */ |
324 |
| ((r3 & 0x03) << 20) |
325 |
| ((r1 & 0x7f) << 6) |
326 |
| (qp & 0x3f);
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} |
328 |
|
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static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1, |
330 |
int p2, int r2, int r3) |
331 |
{ |
332 |
return opc
|
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| ((p2 & 0x3f) << 27) |
334 |
| ((r3 & 0x7f) << 20) |
335 |
| ((r2 & 0x7f) << 13) |
336 |
| ((p1 & 0x3f) << 6) |
337 |
| (qp & 0x3f);
|
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} |
339 |
|
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static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm) |
341 |
{ |
342 |
return opc
|
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| ((imm & 0x100000) << 16) /* s */ |
344 |
| ((imm & 0x0fffff) << 13) /* imm20b */ |
345 |
| (qp & 0x3f);
|
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} |
347 |
|
348 |
static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2) |
349 |
{ |
350 |
return opc
|
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| ((b2 & 0x7) << 13) |
352 |
| (qp & 0x3f);
|
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} |
354 |
|
355 |
static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2) |
356 |
{ |
357 |
return opc
|
358 |
| ((b2 & 0x7) << 13) |
359 |
| ((b1 & 0x7) << 6) |
360 |
| (qp & 0x3f);
|
361 |
} |
362 |
|
363 |
|
364 |
static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm) |
365 |
{ |
366 |
return opc
|
367 |
| ((imm & 0x100000) << 16) /* i */ |
368 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
369 |
| (qp & 0x3f);
|
370 |
} |
371 |
|
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static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1, |
373 |
int f3, int f4, int f2) |
374 |
{ |
375 |
return opc
|
376 |
| ((f4 & 0x7f) << 27) |
377 |
| ((f3 & 0x7f) << 20) |
378 |
| ((f2 & 0x7f) << 13) |
379 |
| ((f1 & 0x7f) << 6) |
380 |
| (qp & 0x3f);
|
381 |
} |
382 |
|
383 |
static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1, |
384 |
int f3, int f4, int f2) |
385 |
{ |
386 |
return opc
|
387 |
| ((f4 & 0x7f) << 27) |
388 |
| ((f3 & 0x7f) << 20) |
389 |
| ((f2 & 0x7f) << 13) |
390 |
| ((f1 & 0x7f) << 6) |
391 |
| (qp & 0x3f);
|
392 |
} |
393 |
|
394 |
static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1, |
395 |
int p2, int f2, int f3) |
396 |
{ |
397 |
return opc
|
398 |
| ((p2 & 0x3f) << 27) |
399 |
| ((f3 & 0x7f) << 20) |
400 |
| ((f2 & 0x7f) << 13) |
401 |
| ((f1 & 0x7f) << 6) |
402 |
| (qp & 0x3f);
|
403 |
} |
404 |
|
405 |
static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2) |
406 |
{ |
407 |
return opc
|
408 |
| ((f2 & 0x7f) << 13) |
409 |
| ((f1 & 0x7f) << 6) |
410 |
| (qp & 0x3f);
|
411 |
} |
412 |
|
413 |
static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2) |
414 |
{ |
415 |
return opc
|
416 |
| ((f2 & 0x7f) << 13) |
417 |
| ((f1 & 0x7f) << 6) |
418 |
| (qp & 0x3f);
|
419 |
} |
420 |
|
421 |
static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm) |
422 |
{ |
423 |
return opc
|
424 |
| ((imm & 0x100000) << 16) /* i */ |
425 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
426 |
| (qp & 0x3f);
|
427 |
} |
428 |
|
429 |
static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1, |
430 |
int r2, int r3) |
431 |
{ |
432 |
return opc
|
433 |
| ((r3 & 0x7f) << 20) |
434 |
| ((r2 & 0x7f) << 13) |
435 |
| ((r1 & 0x7f) << 6) |
436 |
| (qp & 0x3f);
|
437 |
} |
438 |
|
439 |
static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1, |
440 |
int r2, int mbtype) |
441 |
{ |
442 |
return opc
|
443 |
| ((mbtype & 0x0f) << 20) |
444 |
| ((r2 & 0x7f) << 13) |
445 |
| ((r1 & 0x7f) << 6) |
446 |
| (qp & 0x3f);
|
447 |
} |
448 |
|
449 |
static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1, |
450 |
int r3, int r2) |
451 |
{ |
452 |
return opc
|
453 |
| ((r3 & 0x7f) << 20) |
454 |
| ((r2 & 0x7f) << 13) |
455 |
| ((r1 & 0x7f) << 6) |
456 |
| (qp & 0x3f);
|
457 |
} |
458 |
|
459 |
static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1, |
460 |
int r2, int r3) |
461 |
{ |
462 |
return opc
|
463 |
| ((r3 & 0x7f) << 20) |
464 |
| ((r2 & 0x7f) << 13) |
465 |
| ((r1 & 0x7f) << 6) |
466 |
| (qp & 0x3f);
|
467 |
} |
468 |
|
469 |
static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1, |
470 |
int r2, int r3, uint64_t count) |
471 |
{ |
472 |
return opc
|
473 |
| ((count & 0x3f) << 27) |
474 |
| ((r3 & 0x7f) << 20) |
475 |
| ((r2 & 0x7f) << 13) |
476 |
| ((r1 & 0x7f) << 6) |
477 |
| (qp & 0x3f);
|
478 |
} |
479 |
|
480 |
static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1, |
481 |
int r3, uint64_t pos, uint64_t len)
|
482 |
{ |
483 |
return opc
|
484 |
| ((len & 0x3f) << 27) |
485 |
| ((r3 & 0x7f) << 20) |
486 |
| ((pos & 0x3f) << 14) |
487 |
| ((r1 & 0x7f) << 6) |
488 |
| (qp & 0x3f);
|
489 |
} |
490 |
|
491 |
static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1, |
492 |
int r2, uint64_t pos, uint64_t len)
|
493 |
{ |
494 |
return opc
|
495 |
| ((len & 0x3f) << 27) |
496 |
| ((pos & 0x3f) << 20) |
497 |
| ((r2 & 0x7f) << 13) |
498 |
| ((r1 & 0x7f) << 6) |
499 |
| (qp & 0x3f);
|
500 |
} |
501 |
|
502 |
static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm) |
503 |
{ |
504 |
return opc
|
505 |
| ((imm & 0x100000) << 16) /* i */ |
506 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
507 |
| (qp & 0x3f);
|
508 |
} |
509 |
|
510 |
static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1, |
511 |
int r2, uint64_t imm)
|
512 |
{ |
513 |
return opc
|
514 |
| ((imm & 0x1ff) << 24) |
515 |
| ((r2 & 0x7f) << 13) |
516 |
| ((b1 & 0x7) << 6) |
517 |
| (qp & 0x3f);
|
518 |
} |
519 |
|
520 |
static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2) |
521 |
{ |
522 |
return opc
|
523 |
| ((b2 & 0x7) << 13) |
524 |
| ((r1 & 0x7f) << 6) |
525 |
| (qp & 0x3f);
|
526 |
} |
527 |
|
528 |
static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2) |
529 |
{ |
530 |
return opc
|
531 |
| ((ar3 & 0x7f) << 20) |
532 |
| ((r2 & 0x7f) << 13) |
533 |
| (qp & 0x3f);
|
534 |
} |
535 |
|
536 |
static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3) |
537 |
{ |
538 |
return opc
|
539 |
| ((r3 & 0x7f) << 20) |
540 |
| ((r1 & 0x7f) << 6) |
541 |
| (qp & 0x3f);
|
542 |
} |
543 |
|
544 |
static inline uint64_t tcg_opc_l2(uint64_t imm) |
545 |
{ |
546 |
return (imm & 0x7fffffffffc00000ull) >> 22; |
547 |
} |
548 |
|
549 |
static inline uint64_t tcg_opc_l3(uint64_t imm) |
550 |
{ |
551 |
return (imm & 0x07fffffffff00000ull) >> 18; |
552 |
} |
553 |
|
554 |
static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3) |
555 |
{ |
556 |
return opc
|
557 |
| ((r3 & 0x7f) << 20) |
558 |
| ((r1 & 0x7f) << 6) |
559 |
| (qp & 0x3f);
|
560 |
} |
561 |
|
562 |
static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1, |
563 |
int r3, uint64_t imm)
|
564 |
{ |
565 |
return opc
|
566 |
| ((imm & 0x100) << 28) /* s */ |
567 |
| ((imm & 0x080) << 20) /* i */ |
568 |
| ((imm & 0x07f) << 13) /* imm7b */ |
569 |
| ((r3 & 0x7f) << 20) |
570 |
| ((r1 & 0x7f) << 6) |
571 |
| (qp & 0x3f);
|
572 |
} |
573 |
|
574 |
static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3) |
575 |
{ |
576 |
return opc
|
577 |
| ((r3 & 0x7f) << 20) |
578 |
| ((r2 & 0x7f) << 13) |
579 |
| (qp & 0x3f);
|
580 |
} |
581 |
|
582 |
static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2) |
583 |
{ |
584 |
return opc
|
585 |
| ((r2 & 0x7f) << 13) |
586 |
| ((f1 & 0x7f) << 6) |
587 |
| (qp & 0x3f);
|
588 |
} |
589 |
|
590 |
static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2) |
591 |
{ |
592 |
return opc
|
593 |
| ((f2 & 0x7f) << 13) |
594 |
| ((r1 & 0x7f) << 6) |
595 |
| (qp & 0x3f);
|
596 |
} |
597 |
|
598 |
static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1, |
599 |
int sof, int sol, int sor) |
600 |
{ |
601 |
return opc
|
602 |
| ((sor & 0x0f) << 27) |
603 |
| ((sol & 0x7f) << 20) |
604 |
| ((sof & 0x7f) << 13) |
605 |
| ((r1 & 0x7f) << 6) |
606 |
| (qp & 0x3f);
|
607 |
} |
608 |
|
609 |
static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm) |
610 |
{ |
611 |
return opc
|
612 |
| ((imm & 0x100000) << 16) /* i */ |
613 |
| ((imm & 0x0fffff) << 6) /* imm20a */ |
614 |
| (qp & 0x3f);
|
615 |
} |
616 |
|
617 |
static inline uint64_t tcg_opc_x2(int qp, uint64_t opc, |
618 |
int r1, uint64_t imm)
|
619 |
{ |
620 |
return opc
|
621 |
| ((imm & 0x8000000000000000ull) >> 27) /* i */ |
622 |
| (imm & 0x0000000000200000ull) /* ic */ |
623 |
| ((imm & 0x00000000001f0000ull) << 6) /* imm5c */ |
624 |
| ((imm & 0x000000000000ff80ull) << 20) /* imm9d */ |
625 |
| ((imm & 0x000000000000007full) << 13) /* imm7b */ |
626 |
| ((r1 & 0x7f) << 6) |
627 |
| (qp & 0x3f);
|
628 |
} |
629 |
|
630 |
static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm) |
631 |
{ |
632 |
return opc
|
633 |
| ((imm & 0x0800000000000000ull) >> 23) /* i */ |
634 |
| ((imm & 0x00000000000fffffull) << 13) /* imm20b */ |
635 |
| (qp & 0x3f);
|
636 |
} |
637 |
|
638 |
|
639 |
/*
|
640 |
* Relocations
|
641 |
*/
|
642 |
|
643 |
static inline void reloc_pcrel21b (void *pc, tcg_target_long target) |
644 |
{ |
645 |
uint64_t imm; |
646 |
int64_t disp; |
647 |
int slot;
|
648 |
|
649 |
slot = (tcg_target_long) pc & 3;
|
650 |
pc = (void *)((tcg_target_long) pc & ~3); |
651 |
|
652 |
disp = target - (tcg_target_long) pc; |
653 |
imm = (uint64_t) disp >> 4;
|
654 |
|
655 |
switch(slot) {
|
656 |
case 0: |
657 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull) |
658 |
| ((imm & 0x100000) << 21) /* s */ |
659 |
| ((imm & 0x0fffff) << 18); /* imm20b */ |
660 |
break;
|
661 |
case 1: |
662 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull) |
663 |
| ((imm & 0x100000) >> 2) /* s */ |
664 |
| ((imm & 0x0fffe0) >> 5); /* imm20b */ |
665 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull) |
666 |
| ((imm & 0x00001f) << 59); /* imm20b */ |
667 |
break;
|
668 |
case 2: |
669 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull) |
670 |
| ((imm & 0x100000) << 39) /* s */ |
671 |
| ((imm & 0x0fffff) << 36); /* imm20b */ |
672 |
break;
|
673 |
} |
674 |
} |
675 |
|
676 |
static inline uint64_t get_reloc_pcrel21b (void *pc) |
677 |
{ |
678 |
int64_t low, high; |
679 |
int slot;
|
680 |
|
681 |
slot = (tcg_target_long) pc & 3;
|
682 |
pc = (void *)((tcg_target_long) pc & ~3); |
683 |
|
684 |
low = (*(uint64_t *)(pc + 0));
|
685 |
high = (*(uint64_t *)(pc + 8));
|
686 |
|
687 |
switch(slot) {
|
688 |
case 0: |
689 |
return ((low >> 21) & 0x100000) + /* s */ |
690 |
((low >> 18) & 0x0fffff); /* imm20b */ |
691 |
case 1: |
692 |
return ((high << 2) & 0x100000) + /* s */ |
693 |
((high << 5) & 0x0fffe0) + /* imm20b */ |
694 |
((low >> 59) & 0x00001f); /* imm20b */ |
695 |
case 2: |
696 |
return ((high >> 39) & 0x100000) + /* s */ |
697 |
((high >> 36) & 0x0fffff); /* imm20b */ |
698 |
default:
|
699 |
tcg_abort(); |
700 |
} |
701 |
} |
702 |
|
703 |
static inline void reloc_pcrel60b (void *pc, tcg_target_long target) |
704 |
{ |
705 |
int64_t disp; |
706 |
uint64_t imm; |
707 |
|
708 |
disp = target - (tcg_target_long) pc; |
709 |
imm = (uint64_t) disp >> 4;
|
710 |
|
711 |
*(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull) |
712 |
| (imm & 0x0800000000000000ull) /* s */ |
713 |
| ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */ |
714 |
| ((imm & 0x00000000000fffffull) << 36); /* imm20b */ |
715 |
*(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull) |
716 |
| ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */ |
717 |
} |
718 |
|
719 |
static inline uint64_t get_reloc_pcrel60b (void *pc) |
720 |
{ |
721 |
int64_t low, high; |
722 |
|
723 |
low = (*(uint64_t *)(pc + 0));
|
724 |
high = (*(uint64_t *)(pc + 8));
|
725 |
|
726 |
return ((high) & 0x0800000000000000ull) + /* s */ |
727 |
((high >> 36) & 0x00000000000fffffull) + /* imm20b */ |
728 |
((high << 36) & 0x07fffff000000000ull) + /* imm39 */ |
729 |
((low >> 28) & 0x0000000ffff00000ull); /* imm39 */ |
730 |
} |
731 |
|
732 |
|
733 |
static void patch_reloc(uint8_t *code_ptr, int type, |
734 |
tcg_target_long value, tcg_target_long addend) |
735 |
{ |
736 |
value += addend; |
737 |
switch (type) {
|
738 |
case R_IA64_PCREL21B:
|
739 |
reloc_pcrel21b(code_ptr, value); |
740 |
break;
|
741 |
case R_IA64_PCREL60B:
|
742 |
reloc_pcrel60b(code_ptr, value); |
743 |
default:
|
744 |
tcg_abort(); |
745 |
} |
746 |
} |
747 |
|
748 |
/*
|
749 |
* Constraints
|
750 |
*/
|
751 |
|
752 |
/* parse target specific constraints */
|
753 |
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
754 |
{ |
755 |
const char *ct_str; |
756 |
|
757 |
ct_str = *pct_str; |
758 |
switch(ct_str[0]) { |
759 |
case 'r': |
760 |
ct->ct |= TCG_CT_REG; |
761 |
tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
762 |
break;
|
763 |
case 'I': |
764 |
ct->ct |= TCG_CT_CONST_S22; |
765 |
break;
|
766 |
case 'S': |
767 |
ct->ct |= TCG_CT_REG; |
768 |
tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
769 |
#if defined(CONFIG_SOFTMMU)
|
770 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56); |
771 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57); |
772 |
#endif
|
773 |
break;
|
774 |
case 'Z': |
775 |
/* We are cheating a bit here, using the fact that the register
|
776 |
r0 is also the register number 0. Hence there is no need
|
777 |
to check for const_args in each instruction. */
|
778 |
ct->ct |= TCG_CT_CONST_ZERO; |
779 |
break;
|
780 |
default:
|
781 |
return -1; |
782 |
} |
783 |
ct_str++; |
784 |
*pct_str = ct_str; |
785 |
return 0; |
786 |
} |
787 |
|
788 |
/* test if a constant matches the constraint */
|
789 |
static inline int tcg_target_const_match(tcg_target_long val, |
790 |
const TCGArgConstraint *arg_ct)
|
791 |
{ |
792 |
int ct;
|
793 |
ct = arg_ct->ct; |
794 |
if (ct & TCG_CT_CONST)
|
795 |
return 1; |
796 |
else if ((ct & TCG_CT_CONST_ZERO) && val == 0) |
797 |
return 1; |
798 |
else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10) |
799 |
return 1; |
800 |
else
|
801 |
return 0; |
802 |
} |
803 |
|
804 |
/*
|
805 |
* Code generation
|
806 |
*/
|
807 |
|
808 |
static uint8_t *tb_ret_addr;
|
809 |
|
810 |
static inline void tcg_out_bundle(TCGContext *s, int template, |
811 |
uint64_t slot0, uint64_t slot1, |
812 |
uint64_t slot2) |
813 |
{ |
814 |
template &= 0x1f; /* 5 bits */ |
815 |
slot0 &= 0x1ffffffffffull; /* 41 bits */ |
816 |
slot1 &= 0x1ffffffffffull; /* 41 bits */ |
817 |
slot2 &= 0x1ffffffffffull; /* 41 bits */ |
818 |
|
819 |
*(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template; |
820 |
*(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18); |
821 |
s->code_ptr += 16;
|
822 |
} |
823 |
|
824 |
static inline void tcg_out_mov(TCGContext *s, TCGArg ret, TCGArg arg) |
825 |
{ |
826 |
tcg_out_bundle(s, mmI, |
827 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
828 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
829 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
|
830 |
} |
831 |
|
832 |
static inline void tcg_out_movi(TCGContext *s, TCGType type, |
833 |
TCGArg reg, tcg_target_long arg) |
834 |
{ |
835 |
tcg_out_bundle(s, mLX, |
836 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
837 |
tcg_opc_l2 (arg), |
838 |
tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg)); |
839 |
} |
840 |
|
841 |
static inline void tcg_out_addi(TCGContext *s, TCGArg reg, tcg_target_long val) |
842 |
{ |
843 |
if (val == ((int32_t)val << 10) >> 10) { |
844 |
tcg_out_bundle(s, MmI, |
845 |
tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
846 |
TCG_REG_R2, val, TCG_REG_R0), |
847 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
848 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg, |
849 |
reg, TCG_REG_R2)); |
850 |
} else {
|
851 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, val); |
852 |
tcg_out_bundle(s, mmI, |
853 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
854 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
855 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg, |
856 |
reg, TCG_REG_R2)); |
857 |
} |
858 |
} |
859 |
|
860 |
static void tcg_out_br(TCGContext *s, int label_index) |
861 |
{ |
862 |
TCGLabel *l = &s->labels[label_index]; |
863 |
|
864 |
tcg_out_bundle(s, mmB, |
865 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
866 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
867 |
tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1, |
868 |
get_reloc_pcrel21b(s->code_ptr + 2)));
|
869 |
|
870 |
if (l->has_value) {
|
871 |
reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); |
872 |
} else {
|
873 |
tcg_out_reloc(s, (s->code_ptr - 16) + 2, |
874 |
R_IA64_PCREL21B, label_index, 0);
|
875 |
} |
876 |
} |
877 |
|
878 |
static inline void tcg_out_call(TCGContext *s, TCGArg addr) |
879 |
{ |
880 |
tcg_out_bundle(s, MmI, |
881 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr), |
882 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
|
883 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
884 |
TCG_REG_B6, TCG_REG_R2, 0));
|
885 |
tcg_out_bundle(s, mmB, |
886 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3), |
887 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
888 |
tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5, |
889 |
TCG_REG_B0, TCG_REG_B6)); |
890 |
} |
891 |
|
892 |
static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg) |
893 |
{ |
894 |
int64_t disp; |
895 |
uint64_t imm; |
896 |
|
897 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg); |
898 |
|
899 |
disp = tb_ret_addr - s->code_ptr; |
900 |
imm = (uint64_t)disp >> 4;
|
901 |
|
902 |
tcg_out_bundle(s, mLX, |
903 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
904 |
tcg_opc_l3 (imm), |
905 |
tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm)); |
906 |
} |
907 |
|
908 |
static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg) |
909 |
{ |
910 |
if (s->tb_jmp_offset) {
|
911 |
/* direct jump method */
|
912 |
tcg_abort(); |
913 |
} else {
|
914 |
/* indirect jump method */
|
915 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, |
916 |
(tcg_target_long)(s->tb_next + arg)); |
917 |
tcg_out_bundle(s, MmI, |
918 |
tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, |
919 |
TCG_REG_R2, TCG_REG_R2), |
920 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
921 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, |
922 |
TCG_REG_R2, 0));
|
923 |
tcg_out_bundle(s, mmB, |
924 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
925 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
926 |
tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, |
927 |
TCG_REG_B6)); |
928 |
} |
929 |
s->tb_next_offset[arg] = s->code_ptr - s->code_buf; |
930 |
} |
931 |
|
932 |
static inline void tcg_out_jmp(TCGContext *s, TCGArg addr) |
933 |
{ |
934 |
tcg_out_bundle(s, mmI, |
935 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
936 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
937 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
|
938 |
tcg_out_bundle(s, mmB, |
939 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
940 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
941 |
tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
942 |
} |
943 |
|
944 |
static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, |
945 |
TCGArg arg1, tcg_target_long arg2) |
946 |
{ |
947 |
if (arg2 == ((int16_t)arg2 >> 2) << 2) { |
948 |
tcg_out_bundle(s, MmI, |
949 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, |
950 |
TCG_REG_R2, arg2, arg1), |
951 |
tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
952 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
953 |
} else {
|
954 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); |
955 |
tcg_out_bundle(s, MmI, |
956 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, |
957 |
TCG_REG_R2, TCG_REG_R2, arg1), |
958 |
tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
959 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
960 |
} |
961 |
} |
962 |
|
963 |
static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, |
964 |
TCGArg arg1, tcg_target_long arg2) |
965 |
{ |
966 |
if (arg2 == ((int16_t)arg2 >> 2) << 2) { |
967 |
tcg_out_bundle(s, MmI, |
968 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, |
969 |
TCG_REG_R2, arg2, arg1), |
970 |
tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
971 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
972 |
} else {
|
973 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); |
974 |
tcg_out_bundle(s, MmI, |
975 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, |
976 |
TCG_REG_R2, TCG_REG_R2, arg1), |
977 |
tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
978 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
979 |
} |
980 |
} |
981 |
|
982 |
static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGArg arg, |
983 |
TCGArg arg1, tcg_target_long arg2) |
984 |
{ |
985 |
if (type == TCG_TYPE_I32) {
|
986 |
tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2); |
987 |
} else {
|
988 |
tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2); |
989 |
} |
990 |
} |
991 |
|
992 |
static inline void tcg_out_st(TCGContext *s, TCGType type, TCGArg arg, |
993 |
TCGArg arg1, tcg_target_long arg2) |
994 |
{ |
995 |
if (type == TCG_TYPE_I32) {
|
996 |
tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2); |
997 |
} else {
|
998 |
tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2); |
999 |
} |
1000 |
} |
1001 |
|
1002 |
static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret, |
1003 |
TCGArg arg1, int const_arg1,
|
1004 |
TCGArg arg2, int const_arg2)
|
1005 |
{ |
1006 |
uint64_t opc1, opc2; |
1007 |
|
1008 |
if (const_arg1 && arg1 != 0) { |
1009 |
opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
1010 |
TCG_REG_R2, arg1, TCG_REG_R0); |
1011 |
arg1 = TCG_REG_R2; |
1012 |
} else {
|
1013 |
opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
1014 |
} |
1015 |
|
1016 |
if (const_arg2 && arg2 != 0) { |
1017 |
opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
1018 |
TCG_REG_R3, arg2, TCG_REG_R0); |
1019 |
arg2 = TCG_REG_R3; |
1020 |
} else {
|
1021 |
opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
|
1022 |
} |
1023 |
|
1024 |
tcg_out_bundle(s, mII, |
1025 |
opc1, |
1026 |
opc2, |
1027 |
tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2)); |
1028 |
} |
1029 |
|
1030 |
static inline void tcg_out_eqv(TCGContext *s, TCGArg ret, |
1031 |
TCGArg arg1, int const_arg1,
|
1032 |
TCGArg arg2, int const_arg2)
|
1033 |
{ |
1034 |
tcg_out_bundle(s, mII, |
1035 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1036 |
tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2), |
1037 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
1038 |
} |
1039 |
|
1040 |
static inline void tcg_out_nand(TCGContext *s, TCGArg ret, |
1041 |
TCGArg arg1, int const_arg1,
|
1042 |
TCGArg arg2, int const_arg2)
|
1043 |
{ |
1044 |
tcg_out_bundle(s, mII, |
1045 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1046 |
tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2), |
1047 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
1048 |
} |
1049 |
|
1050 |
static inline void tcg_out_nor(TCGContext *s, TCGArg ret, |
1051 |
TCGArg arg1, int const_arg1,
|
1052 |
TCGArg arg2, int const_arg2)
|
1053 |
{ |
1054 |
tcg_out_bundle(s, mII, |
1055 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1056 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2), |
1057 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
1058 |
} |
1059 |
|
1060 |
static inline void tcg_out_orc(TCGContext *s, TCGArg ret, |
1061 |
TCGArg arg1, int const_arg1,
|
1062 |
TCGArg arg2, int const_arg2)
|
1063 |
{ |
1064 |
tcg_out_bundle(s, mII, |
1065 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1066 |
tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
|
1067 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2)); |
1068 |
} |
1069 |
|
1070 |
static inline void tcg_out_mul(TCGContext *s, TCGArg ret, |
1071 |
TCGArg arg1, TCGArg arg2) |
1072 |
{ |
1073 |
tcg_out_bundle(s, mmI, |
1074 |
tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1), |
1075 |
tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2), |
1076 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1077 |
tcg_out_bundle(s, mmF, |
1078 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1079 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1080 |
tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6, |
1081 |
TCG_REG_F7, TCG_REG_F0)); |
1082 |
tcg_out_bundle(s, miI, |
1083 |
tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6), |
1084 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1085 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1086 |
} |
1087 |
|
1088 |
static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1089 |
TCGArg arg2, int const_arg2)
|
1090 |
{ |
1091 |
if (const_arg2) {
|
1092 |
tcg_out_bundle(s, miI, |
1093 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1094 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1095 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
1096 |
ret, arg1, arg2, 31 - arg2));
|
1097 |
} else {
|
1098 |
tcg_out_bundle(s, mII, |
1099 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, |
1100 |
TCG_REG_R3, 0x1f, arg2),
|
1101 |
tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1), |
1102 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, |
1103 |
TCG_REG_R2, TCG_REG_R3)); |
1104 |
} |
1105 |
} |
1106 |
|
1107 |
static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1108 |
TCGArg arg2, int const_arg2)
|
1109 |
{ |
1110 |
if (const_arg2) {
|
1111 |
tcg_out_bundle(s, miI, |
1112 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1113 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1114 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
1115 |
ret, arg1, arg2, 63 - arg2));
|
1116 |
} else {
|
1117 |
tcg_out_bundle(s, miI, |
1118 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1119 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1120 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2)); |
1121 |
} |
1122 |
} |
1123 |
|
1124 |
static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1125 |
TCGArg arg2, int const_arg2)
|
1126 |
{ |
1127 |
if (const_arg2) {
|
1128 |
tcg_out_bundle(s, miI, |
1129 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1130 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1131 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
1132 |
arg1, 63 - arg2, 31 - arg2)); |
1133 |
} else {
|
1134 |
tcg_out_bundle(s, mII, |
1135 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1136 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2, |
1137 |
0x1f, arg2),
|
1138 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, |
1139 |
arg1, TCG_REG_R2)); |
1140 |
} |
1141 |
} |
1142 |
|
1143 |
static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1144 |
TCGArg arg2, int const_arg2)
|
1145 |
{ |
1146 |
if (const_arg2) {
|
1147 |
tcg_out_bundle(s, miI, |
1148 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1149 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1150 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
1151 |
arg1, 63 - arg2, 63 - arg2)); |
1152 |
} else {
|
1153 |
tcg_out_bundle(s, miI, |
1154 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1155 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1156 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, |
1157 |
arg1, arg2)); |
1158 |
} |
1159 |
} |
1160 |
|
1161 |
static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1162 |
TCGArg arg2, int const_arg2)
|
1163 |
{ |
1164 |
if (const_arg2) {
|
1165 |
tcg_out_bundle(s, miI, |
1166 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1167 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1168 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1169 |
arg1, arg2, 31 - arg2));
|
1170 |
} else {
|
1171 |
tcg_out_bundle(s, mII, |
1172 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
1173 |
0x1f, arg2),
|
1174 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1), |
1175 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1176 |
TCG_REG_R2, TCG_REG_R3)); |
1177 |
} |
1178 |
} |
1179 |
|
1180 |
static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1181 |
TCGArg arg2, int const_arg2)
|
1182 |
{ |
1183 |
if (const_arg2) {
|
1184 |
tcg_out_bundle(s, miI, |
1185 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1186 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1187 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1188 |
arg1, arg2, 63 - arg2));
|
1189 |
} else {
|
1190 |
tcg_out_bundle(s, miI, |
1191 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1192 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1193 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1194 |
arg1, arg2)); |
1195 |
} |
1196 |
} |
1197 |
|
1198 |
static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1199 |
TCGArg arg2, int const_arg2)
|
1200 |
{ |
1201 |
if (const_arg2) {
|
1202 |
tcg_out_bundle(s, mII, |
1203 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1204 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1205 |
TCG_REG_R2, arg1, arg1), |
1206 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1207 |
TCG_REG_R2, 32 - arg2, 31)); |
1208 |
} else {
|
1209 |
tcg_out_bundle(s, miI, |
1210 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1211 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1212 |
TCG_REG_R2, arg1, arg1), |
1213 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
1214 |
0x1f, arg2));
|
1215 |
tcg_out_bundle(s, mII, |
1216 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1217 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3, |
1218 |
0x20, TCG_REG_R3),
|
1219 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1220 |
TCG_REG_R2, TCG_REG_R3)); |
1221 |
} |
1222 |
} |
1223 |
|
1224 |
static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1225 |
TCGArg arg2, int const_arg2)
|
1226 |
{ |
1227 |
if (const_arg2) {
|
1228 |
tcg_out_bundle(s, miI, |
1229 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1230 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1231 |
tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
1232 |
arg1, 0x40 - arg2));
|
1233 |
} else {
|
1234 |
tcg_out_bundle(s, mII, |
1235 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, |
1236 |
0x40, arg2),
|
1237 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3, |
1238 |
arg1, arg2), |
1239 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2, |
1240 |
arg1, TCG_REG_R2)); |
1241 |
tcg_out_bundle(s, miI, |
1242 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1243 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1244 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
1245 |
TCG_REG_R2, TCG_REG_R3)); |
1246 |
} |
1247 |
} |
1248 |
|
1249 |
static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1250 |
TCGArg arg2, int const_arg2)
|
1251 |
{ |
1252 |
if (const_arg2) {
|
1253 |
tcg_out_bundle(s, mII, |
1254 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1255 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1256 |
TCG_REG_R2, arg1, arg1), |
1257 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1258 |
TCG_REG_R2, arg2, 31));
|
1259 |
} else {
|
1260 |
tcg_out_bundle(s, mII, |
1261 |
tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
1262 |
0x1f, arg2),
|
1263 |
tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1264 |
TCG_REG_R2, arg1, arg1), |
1265 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1266 |
TCG_REG_R2, TCG_REG_R3)); |
1267 |
} |
1268 |
} |
1269 |
|
1270 |
static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1271 |
TCGArg arg2, int const_arg2)
|
1272 |
{ |
1273 |
if (const_arg2) {
|
1274 |
tcg_out_bundle(s, miI, |
1275 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1276 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1277 |
tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
1278 |
arg1, arg2)); |
1279 |
} else {
|
1280 |
tcg_out_bundle(s, mII, |
1281 |
tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, |
1282 |
0x40, arg2),
|
1283 |
tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3, |
1284 |
arg1, arg2), |
1285 |
tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2, |
1286 |
arg1, TCG_REG_R2)); |
1287 |
tcg_out_bundle(s, miI, |
1288 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1289 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1290 |
tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
1291 |
TCG_REG_R2, TCG_REG_R3)); |
1292 |
} |
1293 |
} |
1294 |
|
1295 |
static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29, |
1296 |
TCGArg ret, TCGArg arg) |
1297 |
{ |
1298 |
tcg_out_bundle(s, miI, |
1299 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1300 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1301 |
tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg)); |
1302 |
} |
1303 |
|
1304 |
static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg) |
1305 |
{ |
1306 |
tcg_out_bundle(s, mII, |
1307 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1308 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15), |
1309 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
1310 |
} |
1311 |
|
1312 |
static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg) |
1313 |
{ |
1314 |
tcg_out_bundle(s, mII, |
1315 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1316 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31), |
1317 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
1318 |
} |
1319 |
|
1320 |
static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg) |
1321 |
{ |
1322 |
tcg_out_bundle(s, mII, |
1323 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1324 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1325 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
|
1326 |
} |
1327 |
|
1328 |
static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1, |
1329 |
TCGArg arg2, int cmp4)
|
1330 |
{ |
1331 |
uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6; |
1332 |
|
1333 |
if (cmp4) {
|
1334 |
opc_eq_a6 = OPC_CMP4_EQ_A6; |
1335 |
opc_lt_a6 = OPC_CMP4_LT_A6; |
1336 |
opc_ltu_a6 = OPC_CMP4_LTU_A6; |
1337 |
} else {
|
1338 |
opc_eq_a6 = OPC_CMP_EQ_A6; |
1339 |
opc_lt_a6 = OPC_CMP_LT_A6; |
1340 |
opc_ltu_a6 = OPC_CMP_LTU_A6; |
1341 |
} |
1342 |
|
1343 |
switch (cond) {
|
1344 |
case TCG_COND_EQ:
|
1345 |
return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
1346 |
case TCG_COND_NE:
|
1347 |
return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
1348 |
case TCG_COND_LT:
|
1349 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
1350 |
case TCG_COND_LTU:
|
1351 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
1352 |
case TCG_COND_GE:
|
1353 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
1354 |
case TCG_COND_GEU:
|
1355 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
1356 |
case TCG_COND_LE:
|
1357 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
1358 |
case TCG_COND_LEU:
|
1359 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
1360 |
case TCG_COND_GT:
|
1361 |
return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
1362 |
case TCG_COND_GTU:
|
1363 |
return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
1364 |
default:
|
1365 |
tcg_abort(); |
1366 |
break;
|
1367 |
} |
1368 |
} |
1369 |
|
1370 |
static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1, |
1371 |
int const_arg1, TCGArg arg2, int const_arg2, |
1372 |
int label_index, int cmp4) |
1373 |
{ |
1374 |
TCGLabel *l = &s->labels[label_index]; |
1375 |
uint64_t opc1, opc2; |
1376 |
|
1377 |
if (const_arg1 && arg1 != 0) { |
1378 |
opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, |
1379 |
arg1, TCG_REG_R0); |
1380 |
arg1 = TCG_REG_R2; |
1381 |
} else {
|
1382 |
opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
1383 |
} |
1384 |
|
1385 |
if (const_arg2 && arg2 != 0) { |
1386 |
opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3, |
1387 |
arg2, TCG_REG_R0); |
1388 |
arg2 = TCG_REG_R3; |
1389 |
} else {
|
1390 |
opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
|
1391 |
} |
1392 |
|
1393 |
tcg_out_bundle(s, mII, |
1394 |
opc1, |
1395 |
opc2, |
1396 |
tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4)); |
1397 |
tcg_out_bundle(s, mmB, |
1398 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1399 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1400 |
tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1, |
1401 |
get_reloc_pcrel21b(s->code_ptr + 2)));
|
1402 |
|
1403 |
if (l->has_value) {
|
1404 |
reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); |
1405 |
} else {
|
1406 |
tcg_out_reloc(s, (s->code_ptr - 16) + 2, |
1407 |
R_IA64_PCREL21B, label_index, 0);
|
1408 |
} |
1409 |
} |
1410 |
|
1411 |
static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret, |
1412 |
TCGArg arg1, TCGArg arg2, int cmp4)
|
1413 |
{ |
1414 |
tcg_out_bundle(s, MmI, |
1415 |
tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), |
1416 |
tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
|
1417 |
tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
|
1418 |
} |
1419 |
|
1420 |
#if defined(CONFIG_SOFTMMU)
|
1421 |
|
1422 |
#include "../../softmmu_defs.h" |
1423 |
|
1424 |
/* Load and compare a TLB entry, and return the result in (p6, p7).
|
1425 |
R2 is loaded with the address of the addend TLB entry.
|
1426 |
R56 is loaded with the address, zero extented on 32-bit targets. */
|
1427 |
static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg, |
1428 |
int s_bits, uint64_t offset_rw,
|
1429 |
uint64_t offset_addend) |
1430 |
{ |
1431 |
tcg_out_bundle(s, mII, |
1432 |
tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3, |
1433 |
TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
1434 |
TCG_REG_R0), |
1435 |
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2, |
1436 |
addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
|
1437 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2, |
1438 |
TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
|
1439 |
63 - CPU_TLB_ENTRY_BITS));
|
1440 |
tcg_out_bundle(s, mII, |
1441 |
tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, |
1442 |
offset_rw, TCG_REG_R2), |
1443 |
#if TARGET_LONG_BITS == 32 |
1444 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R56, addr_reg), |
1445 |
#else
|
1446 |
tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R56, |
1447 |
0, addr_reg),
|
1448 |
#endif
|
1449 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1450 |
TCG_REG_R2, TCG_AREG0)); |
1451 |
tcg_out_bundle(s, mII, |
1452 |
#if TARGET_LONG_BITS == 32 |
1453 |
tcg_opc_m3 (TCG_REG_P0, OPC_LD4_M3, TCG_REG_R57, |
1454 |
TCG_REG_R2, offset_addend - offset_rw), |
1455 |
#else
|
1456 |
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R57, |
1457 |
TCG_REG_R2, offset_addend - offset_rw), |
1458 |
#endif
|
1459 |
tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3, |
1460 |
TCG_REG_R3, TCG_REG_R56), |
1461 |
tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6, |
1462 |
TCG_REG_P7, TCG_REG_R3, TCG_REG_R57)); |
1463 |
} |
1464 |
|
1465 |
static void *qemu_ld_helpers[4] = { |
1466 |
__ldb_mmu, |
1467 |
__ldw_mmu, |
1468 |
__ldl_mmu, |
1469 |
__ldq_mmu, |
1470 |
}; |
1471 |
|
1472 |
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
1473 |
{ |
1474 |
int addr_reg, data_reg, mem_index, s_bits, bswap;
|
1475 |
uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
|
1476 |
uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, |
1477 |
OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
|
1478 |
|
1479 |
data_reg = *args++; |
1480 |
addr_reg = *args++; |
1481 |
mem_index = *args; |
1482 |
s_bits = opc & 3;
|
1483 |
|
1484 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1485 |
bswap = 1;
|
1486 |
#else
|
1487 |
bswap = 0;
|
1488 |
#endif
|
1489 |
|
1490 |
/* Read the TLB entry */
|
1491 |
tcg_out_qemu_tlb(s, addr_reg, s_bits, |
1492 |
offsetof(CPUState, tlb_table[mem_index][0].addr_read),
|
1493 |
offsetof(CPUState, tlb_table[mem_index][0].addend));
|
1494 |
|
1495 |
/* P6 is the fast path, and P7 the slow path */
|
1496 |
tcg_out_bundle(s, mLX, |
1497 |
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R57, |
1498 |
mem_index, TCG_REG_R0), |
1499 |
tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]), |
1500 |
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, |
1501 |
(tcg_target_long) qemu_ld_helpers[s_bits])); |
1502 |
tcg_out_bundle(s, MmI, |
1503 |
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, |
1504 |
TCG_REG_R2, 8),
|
1505 |
tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, |
1506 |
TCG_REG_R3, TCG_REG_R56), |
1507 |
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
1508 |
TCG_REG_R3, 0));
|
1509 |
if (bswap && s_bits == 1) { |
1510 |
tcg_out_bundle(s, MmI, |
1511 |
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
1512 |
TCG_REG_R8, TCG_REG_R3), |
1513 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
1514 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1515 |
TCG_REG_R8, TCG_REG_R8, 15, 15)); |
1516 |
} else if (bswap && s_bits == 2) { |
1517 |
tcg_out_bundle(s, MmI, |
1518 |
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
1519 |
TCG_REG_R8, TCG_REG_R3), |
1520 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
1521 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1522 |
TCG_REG_R8, TCG_REG_R8, 31, 31)); |
1523 |
} else {
|
1524 |
tcg_out_bundle(s, mmI, |
1525 |
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
1526 |
TCG_REG_R8, TCG_REG_R3), |
1527 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
1528 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1529 |
} |
1530 |
if (!bswap || s_bits == 0) { |
1531 |
tcg_out_bundle(s, miB, |
1532 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1533 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1534 |
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1535 |
TCG_REG_B0, TCG_REG_B6)); |
1536 |
} else {
|
1537 |
tcg_out_bundle(s, miB, |
1538 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1539 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1540 |
TCG_REG_R8, TCG_REG_R8, 0xb),
|
1541 |
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1542 |
TCG_REG_B0, TCG_REG_B6)); |
1543 |
} |
1544 |
|
1545 |
if (opc == 3) { |
1546 |
tcg_out_bundle(s, miI, |
1547 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1548 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1549 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
1550 |
data_reg, 0, TCG_REG_R8));
|
1551 |
} else {
|
1552 |
tcg_out_bundle(s, miI, |
1553 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1554 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1555 |
tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc], |
1556 |
data_reg, TCG_REG_R8)); |
1557 |
} |
1558 |
} |
1559 |
|
1560 |
static void *qemu_st_helpers[4] = { |
1561 |
__stb_mmu, |
1562 |
__stw_mmu, |
1563 |
__stl_mmu, |
1564 |
__stq_mmu, |
1565 |
}; |
1566 |
|
1567 |
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
1568 |
{ |
1569 |
int addr_reg, data_reg, mem_index, bswap;
|
1570 |
uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
|
1571 |
|
1572 |
data_reg = *args++; |
1573 |
addr_reg = *args++; |
1574 |
mem_index = *args; |
1575 |
|
1576 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1577 |
bswap = 1;
|
1578 |
#else
|
1579 |
bswap = 0;
|
1580 |
#endif
|
1581 |
|
1582 |
tcg_out_qemu_tlb(s, addr_reg, opc, |
1583 |
offsetof(CPUState, tlb_table[mem_index][0].addr_write),
|
1584 |
offsetof(CPUState, tlb_table[mem_index][0].addend));
|
1585 |
|
1586 |
/* P6 is the fast path, and P7 the slow path */
|
1587 |
tcg_out_bundle(s, mLX, |
1588 |
tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R57, |
1589 |
0, data_reg),
|
1590 |
tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]), |
1591 |
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, |
1592 |
(tcg_target_long) qemu_st_helpers[opc])); |
1593 |
tcg_out_bundle(s, MmI, |
1594 |
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, |
1595 |
TCG_REG_R2, 8),
|
1596 |
tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, |
1597 |
TCG_REG_R3, TCG_REG_R56), |
1598 |
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
1599 |
TCG_REG_R3, 0));
|
1600 |
|
1601 |
if (!bswap || opc == 0) { |
1602 |
tcg_out_bundle(s, mII, |
1603 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1604 |
TCG_REG_R1, TCG_REG_R2), |
1605 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1606 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1607 |
} else if (opc == 1) { |
1608 |
tcg_out_bundle(s, mII, |
1609 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1610 |
TCG_REG_R1, TCG_REG_R2), |
1611 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1612 |
TCG_REG_R2, data_reg, 15, 15), |
1613 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1614 |
TCG_REG_R2, TCG_REG_R2, 0xb));
|
1615 |
data_reg = TCG_REG_R2; |
1616 |
} else if (opc == 2) { |
1617 |
tcg_out_bundle(s, mII, |
1618 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1619 |
TCG_REG_R1, TCG_REG_R2), |
1620 |
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1621 |
TCG_REG_R2, data_reg, 31, 31), |
1622 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1623 |
TCG_REG_R2, TCG_REG_R2, 0xb));
|
1624 |
data_reg = TCG_REG_R2; |
1625 |
} else if (opc == 3) { |
1626 |
tcg_out_bundle(s, miI, |
1627 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1628 |
TCG_REG_R1, TCG_REG_R2), |
1629 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1630 |
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1631 |
TCG_REG_R2, data_reg, 0xb));
|
1632 |
data_reg = TCG_REG_R2; |
1633 |
} |
1634 |
|
1635 |
tcg_out_bundle(s, miB, |
1636 |
tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc], |
1637 |
data_reg, TCG_REG_R3), |
1638 |
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, |
1639 |
mem_index, TCG_REG_R0), |
1640 |
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1641 |
TCG_REG_B0, TCG_REG_B6)); |
1642 |
} |
1643 |
|
1644 |
#else /* !CONFIG_SOFTMMU */ |
1645 |
|
1646 |
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
1647 |
{ |
1648 |
int addr_reg, data_reg, mem_index, s_bits, bswap;
|
1649 |
uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
|
1650 |
uint64_t opc_sxt_i29[8] = { OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 }; |
1651 |
|
1652 |
data_reg = *args++; |
1653 |
addr_reg = *args++; |
1654 |
mem_index = *args; |
1655 |
s_bits = opc & 3;
|
1656 |
|
1657 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1658 |
bswap = 1;
|
1659 |
#else
|
1660 |
bswap = 0;
|
1661 |
#endif
|
1662 |
|
1663 |
tcg_out_bundle(s, mLX, |
1664 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1665 |
tcg_opc_l2 ((tcg_target_long) GUEST_BASE), |
1666 |
tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R2, |
1667 |
GUEST_BASE)); |
1668 |
|
1669 |
#if TARGET_LONG_BITS == 32 |
1670 |
tcg_out_bundle(s, mII, |
1671 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1672 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1673 |
TCG_REG_R3, addr_reg), |
1674 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1675 |
TCG_REG_R2, TCG_REG_R3)); |
1676 |
|
1677 |
if (!bswap || s_bits == 0) { |
1678 |
if (s_bits == opc) {
|
1679 |
tcg_out_bundle(s, miI, |
1680 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1681 |
data_reg, TCG_REG_R2), |
1682 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1683 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1684 |
} else {
|
1685 |
tcg_out_bundle(s, mII, |
1686 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1687 |
data_reg, TCG_REG_R2), |
1688 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1689 |
tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1690 |
data_reg, data_reg)); |
1691 |
} |
1692 |
} else if (s_bits == 3) { |
1693 |
tcg_out_bundle(s, mII, |
1694 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1695 |
data_reg, TCG_REG_R2), |
1696 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1697 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1698 |
data_reg, data_reg, 0xb));
|
1699 |
} else {
|
1700 |
if (s_bits == 1) { |
1701 |
tcg_out_bundle(s, mII, |
1702 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1703 |
data_reg, TCG_REG_R2), |
1704 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1705 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1706 |
data_reg, data_reg, 15, 15)); |
1707 |
} else {
|
1708 |
tcg_out_bundle(s, mII, |
1709 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1710 |
data_reg, TCG_REG_R2), |
1711 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1712 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1713 |
data_reg, data_reg, 31, 31)); |
1714 |
} |
1715 |
if (opc == s_bits) {
|
1716 |
tcg_out_bundle(s, miI, |
1717 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1718 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1719 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1720 |
data_reg, data_reg, 0xb));
|
1721 |
} else {
|
1722 |
tcg_out_bundle(s, mII, |
1723 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1724 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1725 |
data_reg, data_reg, 0xb),
|
1726 |
tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1727 |
data_reg, data_reg)); |
1728 |
} |
1729 |
} |
1730 |
#else
|
1731 |
tcg_out_bundle(s, MmI, |
1732 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1733 |
TCG_REG_R2, addr_reg), |
1734 |
tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1735 |
data_reg, TCG_REG_R2), |
1736 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1737 |
|
1738 |
if (bswap && s_bits == 1) { |
1739 |
tcg_out_bundle(s, mII, |
1740 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1741 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1742 |
data_reg, data_reg, 15, 15), |
1743 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1744 |
data_reg, data_reg, 0xb));
|
1745 |
} else if (bswap && s_bits == 2) { |
1746 |
tcg_out_bundle(s, mII, |
1747 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1748 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1749 |
data_reg, data_reg, 31, 31), |
1750 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1751 |
data_reg, data_reg, 0xb));
|
1752 |
} else if (bswap && s_bits == 3) { |
1753 |
tcg_out_bundle(s, miI, |
1754 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1755 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1756 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1757 |
data_reg, data_reg, 0xb));
|
1758 |
} |
1759 |
if (s_bits != opc) {
|
1760 |
tcg_out_bundle(s, miI, |
1761 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1762 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1763 |
tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1764 |
data_reg, data_reg)); |
1765 |
} |
1766 |
#endif
|
1767 |
} |
1768 |
|
1769 |
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
1770 |
{ |
1771 |
int addr_reg, data_reg, bswap;
|
1772 |
uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
|
1773 |
|
1774 |
data_reg = *args++; |
1775 |
addr_reg = *args++; |
1776 |
|
1777 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1778 |
bswap = 1;
|
1779 |
#else
|
1780 |
bswap = 0;
|
1781 |
#endif
|
1782 |
|
1783 |
tcg_out_bundle(s, mLX, |
1784 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1785 |
tcg_opc_l2 ((tcg_target_long) GUEST_BASE), |
1786 |
tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R2, |
1787 |
GUEST_BASE)); |
1788 |
|
1789 |
#if TARGET_LONG_BITS == 32 |
1790 |
tcg_out_bundle(s, mII, |
1791 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1792 |
tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1793 |
TCG_REG_R3, addr_reg), |
1794 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1795 |
TCG_REG_R2, TCG_REG_R3)); |
1796 |
if (bswap) {
|
1797 |
if (opc == 1) { |
1798 |
tcg_out_bundle(s, mII, |
1799 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1800 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1801 |
TCG_REG_R3, data_reg, 15, 15), |
1802 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1803 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
1804 |
data_reg = TCG_REG_R3; |
1805 |
} else if (opc == 2) { |
1806 |
tcg_out_bundle(s, mII, |
1807 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1808 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1809 |
TCG_REG_R3, data_reg, 31, 31), |
1810 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1811 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
1812 |
data_reg = TCG_REG_R3; |
1813 |
} else if (opc == 3) { |
1814 |
tcg_out_bundle(s, miI, |
1815 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1816 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1817 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1818 |
TCG_REG_R3, data_reg, 0xb));
|
1819 |
data_reg = TCG_REG_R3; |
1820 |
} |
1821 |
} |
1822 |
tcg_out_bundle(s, mmI, |
1823 |
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
1824 |
data_reg, TCG_REG_R2), |
1825 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1826 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1827 |
#else
|
1828 |
if (!bswap || opc == 0) { |
1829 |
tcg_out_bundle(s, MmI, |
1830 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1831 |
TCG_REG_R2, addr_reg), |
1832 |
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
1833 |
data_reg, TCG_REG_R2), |
1834 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1835 |
} else {
|
1836 |
if (opc == 1) { |
1837 |
tcg_out_bundle(s, mII, |
1838 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1839 |
TCG_REG_R2, addr_reg), |
1840 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1841 |
TCG_REG_R3, data_reg, 15, 15), |
1842 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1843 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
1844 |
data_reg = TCG_REG_R3; |
1845 |
} else if (opc == 2) { |
1846 |
tcg_out_bundle(s, mII, |
1847 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1848 |
TCG_REG_R2, addr_reg), |
1849 |
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1850 |
TCG_REG_R3, data_reg, 31, 31), |
1851 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1852 |
TCG_REG_R3, TCG_REG_R3, 0xb));
|
1853 |
data_reg = TCG_REG_R3; |
1854 |
} else if (opc == 3) { |
1855 |
tcg_out_bundle(s, miI, |
1856 |
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1857 |
TCG_REG_R2, addr_reg), |
1858 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1859 |
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1860 |
TCG_REG_R3, data_reg, 0xb));
|
1861 |
data_reg = TCG_REG_R3; |
1862 |
} |
1863 |
tcg_out_bundle(s, miI, |
1864 |
tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
1865 |
data_reg, TCG_REG_R2), |
1866 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1867 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1868 |
} |
1869 |
#endif
|
1870 |
} |
1871 |
|
1872 |
#endif
|
1873 |
|
1874 |
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, |
1875 |
const TCGArg *args, const int *const_args) |
1876 |
{ |
1877 |
switch(opc) {
|
1878 |
case INDEX_op_exit_tb:
|
1879 |
tcg_out_exit_tb(s, args[0]);
|
1880 |
break;
|
1881 |
case INDEX_op_br:
|
1882 |
tcg_out_br(s, args[0]);
|
1883 |
break;
|
1884 |
case INDEX_op_call:
|
1885 |
tcg_out_call(s, args[0]);
|
1886 |
break;
|
1887 |
case INDEX_op_goto_tb:
|
1888 |
tcg_out_goto_tb(s, args[0]);
|
1889 |
break;
|
1890 |
case INDEX_op_jmp:
|
1891 |
tcg_out_jmp(s, args[0]);
|
1892 |
break;
|
1893 |
|
1894 |
case INDEX_op_movi_i32:
|
1895 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); |
1896 |
break;
|
1897 |
case INDEX_op_movi_i64:
|
1898 |
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
1899 |
break;
|
1900 |
|
1901 |
case INDEX_op_ld8u_i32:
|
1902 |
case INDEX_op_ld8u_i64:
|
1903 |
tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); |
1904 |
break;
|
1905 |
case INDEX_op_ld8s_i32:
|
1906 |
case INDEX_op_ld8s_i64:
|
1907 |
tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); |
1908 |
tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]); |
1909 |
break;
|
1910 |
case INDEX_op_ld16u_i32:
|
1911 |
case INDEX_op_ld16u_i64:
|
1912 |
tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); |
1913 |
break;
|
1914 |
case INDEX_op_ld16s_i32:
|
1915 |
case INDEX_op_ld16s_i64:
|
1916 |
tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); |
1917 |
tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]); |
1918 |
break;
|
1919 |
case INDEX_op_ld_i32:
|
1920 |
case INDEX_op_ld32u_i64:
|
1921 |
tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); |
1922 |
break;
|
1923 |
case INDEX_op_ld32s_i64:
|
1924 |
tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); |
1925 |
tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]); |
1926 |
break;
|
1927 |
case INDEX_op_ld_i64:
|
1928 |
tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]); |
1929 |
break;
|
1930 |
case INDEX_op_st8_i32:
|
1931 |
case INDEX_op_st8_i64:
|
1932 |
tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]); |
1933 |
break;
|
1934 |
case INDEX_op_st16_i32:
|
1935 |
case INDEX_op_st16_i64:
|
1936 |
tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]); |
1937 |
break;
|
1938 |
case INDEX_op_st_i32:
|
1939 |
case INDEX_op_st32_i64:
|
1940 |
tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]); |
1941 |
break;
|
1942 |
case INDEX_op_st_i64:
|
1943 |
tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]); |
1944 |
break;
|
1945 |
|
1946 |
case INDEX_op_add_i32:
|
1947 |
case INDEX_op_add_i64:
|
1948 |
tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1], |
1949 |
args[2], const_args[2]); |
1950 |
break;
|
1951 |
case INDEX_op_sub_i32:
|
1952 |
case INDEX_op_sub_i64:
|
1953 |
tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1], |
1954 |
args[2], const_args[2]); |
1955 |
break;
|
1956 |
|
1957 |
case INDEX_op_and_i32:
|
1958 |
case INDEX_op_and_i64:
|
1959 |
tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1], |
1960 |
args[2], const_args[2]); |
1961 |
break;
|
1962 |
case INDEX_op_andc_i32:
|
1963 |
case INDEX_op_andc_i64:
|
1964 |
tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1], |
1965 |
args[2], const_args[2]); |
1966 |
break;
|
1967 |
case INDEX_op_eqv_i32:
|
1968 |
case INDEX_op_eqv_i64:
|
1969 |
tcg_out_eqv(s, args[0], args[1], const_args[1], |
1970 |
args[2], const_args[2]); |
1971 |
break;
|
1972 |
case INDEX_op_nand_i32:
|
1973 |
case INDEX_op_nand_i64:
|
1974 |
tcg_out_nand(s, args[0], args[1], const_args[1], |
1975 |
args[2], const_args[2]); |
1976 |
break;
|
1977 |
case INDEX_op_nor_i32:
|
1978 |
case INDEX_op_nor_i64:
|
1979 |
tcg_out_nor(s, args[0], args[1], const_args[1], |
1980 |
args[2], const_args[2]); |
1981 |
break;
|
1982 |
case INDEX_op_or_i32:
|
1983 |
case INDEX_op_or_i64:
|
1984 |
tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1], |
1985 |
args[2], const_args[2]); |
1986 |
break;
|
1987 |
case INDEX_op_orc_i32:
|
1988 |
case INDEX_op_orc_i64:
|
1989 |
tcg_out_orc(s, args[0], args[1], const_args[1], |
1990 |
args[2], const_args[2]); |
1991 |
break;
|
1992 |
case INDEX_op_xor_i32:
|
1993 |
case INDEX_op_xor_i64:
|
1994 |
tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1], |
1995 |
args[2], const_args[2]); |
1996 |
break;
|
1997 |
|
1998 |
case INDEX_op_mul_i32:
|
1999 |
case INDEX_op_mul_i64:
|
2000 |
tcg_out_mul(s, args[0], args[1], args[2]); |
2001 |
break;
|
2002 |
|
2003 |
case INDEX_op_sar_i32:
|
2004 |
tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]); |
2005 |
break;
|
2006 |
case INDEX_op_sar_i64:
|
2007 |
tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]); |
2008 |
break;
|
2009 |
case INDEX_op_shl_i32:
|
2010 |
tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]); |
2011 |
break;
|
2012 |
case INDEX_op_shl_i64:
|
2013 |
tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]); |
2014 |
break;
|
2015 |
case INDEX_op_shr_i32:
|
2016 |
tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]); |
2017 |
break;
|
2018 |
case INDEX_op_shr_i64:
|
2019 |
tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]); |
2020 |
break;
|
2021 |
case INDEX_op_rotl_i32:
|
2022 |
tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]); |
2023 |
break;
|
2024 |
case INDEX_op_rotl_i64:
|
2025 |
tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]); |
2026 |
break;
|
2027 |
case INDEX_op_rotr_i32:
|
2028 |
tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]); |
2029 |
break;
|
2030 |
case INDEX_op_rotr_i64:
|
2031 |
tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]); |
2032 |
break;
|
2033 |
|
2034 |
case INDEX_op_ext8s_i32:
|
2035 |
case INDEX_op_ext8s_i64:
|
2036 |
tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]); |
2037 |
break;
|
2038 |
case INDEX_op_ext8u_i32:
|
2039 |
case INDEX_op_ext8u_i64:
|
2040 |
tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]); |
2041 |
break;
|
2042 |
case INDEX_op_ext16s_i32:
|
2043 |
case INDEX_op_ext16s_i64:
|
2044 |
tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]); |
2045 |
break;
|
2046 |
case INDEX_op_ext16u_i32:
|
2047 |
case INDEX_op_ext16u_i64:
|
2048 |
tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]); |
2049 |
break;
|
2050 |
case INDEX_op_ext32s_i64:
|
2051 |
tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]); |
2052 |
break;
|
2053 |
case INDEX_op_ext32u_i64:
|
2054 |
tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]); |
2055 |
break;
|
2056 |
|
2057 |
case INDEX_op_bswap16_i32:
|
2058 |
case INDEX_op_bswap16_i64:
|
2059 |
tcg_out_bswap16(s, args[0], args[1]); |
2060 |
break;
|
2061 |
case INDEX_op_bswap32_i32:
|
2062 |
case INDEX_op_bswap32_i64:
|
2063 |
tcg_out_bswap32(s, args[0], args[1]); |
2064 |
break;
|
2065 |
case INDEX_op_bswap64_i64:
|
2066 |
tcg_out_bswap64(s, args[0], args[1]); |
2067 |
break;
|
2068 |
|
2069 |
case INDEX_op_brcond_i32:
|
2070 |
tcg_out_brcond(s, args[2], args[0], const_args[0], |
2071 |
args[1], const_args[1], args[3], 1); |
2072 |
break;
|
2073 |
case INDEX_op_brcond_i64:
|
2074 |
tcg_out_brcond(s, args[2], args[0], const_args[0], |
2075 |
args[1], const_args[1], args[3], 0); |
2076 |
break;
|
2077 |
case INDEX_op_setcond_i32:
|
2078 |
tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1); |
2079 |
break;
|
2080 |
case INDEX_op_setcond_i64:
|
2081 |
tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0); |
2082 |
break;
|
2083 |
|
2084 |
case INDEX_op_qemu_ld8u:
|
2085 |
tcg_out_qemu_ld(s, args, 0);
|
2086 |
break;
|
2087 |
case INDEX_op_qemu_ld8s:
|
2088 |
tcg_out_qemu_ld(s, args, 0 | 4); |
2089 |
break;
|
2090 |
case INDEX_op_qemu_ld16u:
|
2091 |
tcg_out_qemu_ld(s, args, 1);
|
2092 |
break;
|
2093 |
case INDEX_op_qemu_ld16s:
|
2094 |
tcg_out_qemu_ld(s, args, 1 | 4); |
2095 |
break;
|
2096 |
case INDEX_op_qemu_ld32u:
|
2097 |
tcg_out_qemu_ld(s, args, 2);
|
2098 |
break;
|
2099 |
case INDEX_op_qemu_ld32s:
|
2100 |
tcg_out_qemu_ld(s, args, 2 | 4); |
2101 |
break;
|
2102 |
case INDEX_op_qemu_ld64:
|
2103 |
tcg_out_qemu_ld(s, args, 3);
|
2104 |
break;
|
2105 |
|
2106 |
case INDEX_op_qemu_st8:
|
2107 |
tcg_out_qemu_st(s, args, 0);
|
2108 |
break;
|
2109 |
case INDEX_op_qemu_st16:
|
2110 |
tcg_out_qemu_st(s, args, 1);
|
2111 |
break;
|
2112 |
case INDEX_op_qemu_st32:
|
2113 |
tcg_out_qemu_st(s, args, 2);
|
2114 |
break;
|
2115 |
case INDEX_op_qemu_st64:
|
2116 |
tcg_out_qemu_st(s, args, 3);
|
2117 |
break;
|
2118 |
|
2119 |
default:
|
2120 |
tcg_abort(); |
2121 |
} |
2122 |
} |
2123 |
|
2124 |
static const TCGTargetOpDef ia64_op_defs[] = { |
2125 |
{ INDEX_op_br, { } }, |
2126 |
{ INDEX_op_call, { "r" } },
|
2127 |
{ INDEX_op_exit_tb, { } }, |
2128 |
{ INDEX_op_goto_tb, { } }, |
2129 |
{ INDEX_op_jmp, { "r" } },
|
2130 |
|
2131 |
{ INDEX_op_mov_i32, { "r", "r" } }, |
2132 |
{ INDEX_op_movi_i32, { "r" } },
|
2133 |
|
2134 |
{ INDEX_op_ld8u_i32, { "r", "r" } }, |
2135 |
{ INDEX_op_ld8s_i32, { "r", "r" } }, |
2136 |
{ INDEX_op_ld16u_i32, { "r", "r" } }, |
2137 |
{ INDEX_op_ld16s_i32, { "r", "r" } }, |
2138 |
{ INDEX_op_ld_i32, { "r", "r" } }, |
2139 |
{ INDEX_op_st8_i32, { "rZ", "r" } }, |
2140 |
{ INDEX_op_st16_i32, { "rZ", "r" } }, |
2141 |
{ INDEX_op_st_i32, { "rZ", "r" } }, |
2142 |
|
2143 |
{ INDEX_op_add_i32, { "r", "rI", "rI" } }, |
2144 |
{ INDEX_op_sub_i32, { "r", "rI", "rI" } }, |
2145 |
|
2146 |
{ INDEX_op_and_i32, { "r", "rI", "rI" } }, |
2147 |
{ INDEX_op_andc_i32, { "r", "rI", "rI" } }, |
2148 |
{ INDEX_op_eqv_i32, { "r", "rZ", "rZ" } }, |
2149 |
{ INDEX_op_nand_i32, { "r", "rZ", "rZ" } }, |
2150 |
{ INDEX_op_nor_i32, { "r", "rZ", "rZ" } }, |
2151 |
{ INDEX_op_or_i32, { "r", "rI", "rI" } }, |
2152 |
{ INDEX_op_orc_i32, { "r", "rZ", "rZ" } }, |
2153 |
{ INDEX_op_xor_i32, { "r", "rI", "rI" } }, |
2154 |
|
2155 |
{ INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, |
2156 |
|
2157 |
{ INDEX_op_sar_i32, { "r", "rZ", "ri" } }, |
2158 |
{ INDEX_op_shl_i32, { "r", "rZ", "ri" } }, |
2159 |
{ INDEX_op_shr_i32, { "r", "rZ", "ri" } }, |
2160 |
{ INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, |
2161 |
{ INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, |
2162 |
|
2163 |
{ INDEX_op_ext8s_i32, { "r", "rZ"} }, |
2164 |
{ INDEX_op_ext8u_i32, { "r", "rZ"} }, |
2165 |
{ INDEX_op_ext16s_i32, { "r", "rZ"} }, |
2166 |
{ INDEX_op_ext16u_i32, { "r", "rZ"} }, |
2167 |
|
2168 |
{ INDEX_op_bswap16_i32, { "r", "rZ" } }, |
2169 |
{ INDEX_op_bswap32_i32, { "r", "rZ" } }, |
2170 |
|
2171 |
{ INDEX_op_brcond_i32, { "rI", "rI" } }, |
2172 |
{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, |
2173 |
|
2174 |
{ INDEX_op_mov_i64, { "r", "r" } }, |
2175 |
{ INDEX_op_movi_i64, { "r" } },
|
2176 |
|
2177 |
{ INDEX_op_ld8u_i64, { "r", "r" } }, |
2178 |
{ INDEX_op_ld8s_i64, { "r", "r" } }, |
2179 |
{ INDEX_op_ld16u_i64, { "r", "r" } }, |
2180 |
{ INDEX_op_ld16s_i64, { "r", "r" } }, |
2181 |
{ INDEX_op_ld32u_i64, { "r", "r" } }, |
2182 |
{ INDEX_op_ld32s_i64, { "r", "r" } }, |
2183 |
{ INDEX_op_ld_i64, { "r", "r" } }, |
2184 |
{ INDEX_op_st8_i64, { "rZ", "r" } }, |
2185 |
{ INDEX_op_st16_i64, { "rZ", "r" } }, |
2186 |
{ INDEX_op_st32_i64, { "rZ", "r" } }, |
2187 |
{ INDEX_op_st_i64, { "rZ", "r" } }, |
2188 |
|
2189 |
{ INDEX_op_add_i64, { "r", "rI", "rI" } }, |
2190 |
{ INDEX_op_sub_i64, { "r", "rI", "rI" } }, |
2191 |
|
2192 |
{ INDEX_op_and_i64, { "r", "rI", "rI" } }, |
2193 |
{ INDEX_op_andc_i64, { "r", "rI", "rI" } }, |
2194 |
{ INDEX_op_eqv_i64, { "r", "rZ", "rZ" } }, |
2195 |
{ INDEX_op_nand_i64, { "r", "rZ", "rZ" } }, |
2196 |
{ INDEX_op_nor_i64, { "r", "rZ", "rZ" } }, |
2197 |
{ INDEX_op_or_i64, { "r", "rI", "rI" } }, |
2198 |
{ INDEX_op_orc_i64, { "r", "rZ", "rZ" } }, |
2199 |
{ INDEX_op_xor_i64, { "r", "rI", "rI" } }, |
2200 |
|
2201 |
{ INDEX_op_mul_i64, { "r", "rZ", "rZ" } }, |
2202 |
|
2203 |
{ INDEX_op_sar_i64, { "r", "rZ", "ri" } }, |
2204 |
{ INDEX_op_shl_i64, { "r", "rZ", "ri" } }, |
2205 |
{ INDEX_op_shr_i64, { "r", "rZ", "ri" } }, |
2206 |
{ INDEX_op_rotl_i64, { "r", "rZ", "ri" } }, |
2207 |
{ INDEX_op_rotr_i64, { "r", "rZ", "ri" } }, |
2208 |
|
2209 |
{ INDEX_op_ext8s_i64, { "r", "rZ"} }, |
2210 |
{ INDEX_op_ext8u_i64, { "r", "rZ"} }, |
2211 |
{ INDEX_op_ext16s_i64, { "r", "rZ"} }, |
2212 |
{ INDEX_op_ext16u_i64, { "r", "rZ"} }, |
2213 |
{ INDEX_op_ext32s_i64, { "r", "rZ"} }, |
2214 |
{ INDEX_op_ext32u_i64, { "r", "rZ"} }, |
2215 |
|
2216 |
{ INDEX_op_bswap16_i64, { "r", "rZ" } }, |
2217 |
{ INDEX_op_bswap32_i64, { "r", "rZ" } }, |
2218 |
{ INDEX_op_bswap64_i64, { "r", "rZ" } }, |
2219 |
|
2220 |
{ INDEX_op_brcond_i64, { "rI", "rI" } }, |
2221 |
{ INDEX_op_setcond_i64, { "r", "rZ", "rZ" } }, |
2222 |
|
2223 |
{ INDEX_op_qemu_ld8u, { "r", "r" } }, |
2224 |
{ INDEX_op_qemu_ld8s, { "r", "r" } }, |
2225 |
{ INDEX_op_qemu_ld16u, { "r", "r" } }, |
2226 |
{ INDEX_op_qemu_ld16s, { "r", "r" } }, |
2227 |
{ INDEX_op_qemu_ld32, { "r", "r" } }, |
2228 |
{ INDEX_op_qemu_ld32u, { "r", "r" } }, |
2229 |
{ INDEX_op_qemu_ld32s, { "r", "r" } }, |
2230 |
{ INDEX_op_qemu_ld64, { "r", "r" } }, |
2231 |
|
2232 |
{ INDEX_op_qemu_st8, { "SZ", "r" } }, |
2233 |
{ INDEX_op_qemu_st16, { "SZ", "r" } }, |
2234 |
{ INDEX_op_qemu_st32, { "SZ", "r" } }, |
2235 |
{ INDEX_op_qemu_st64, { "SZ", "r" } }, |
2236 |
|
2237 |
{ -1 },
|
2238 |
}; |
2239 |
|
2240 |
/* Generate global QEMU prologue and epilogue code */
|
2241 |
void tcg_target_qemu_prologue(TCGContext *s)
|
2242 |
{ |
2243 |
int frame_size;
|
2244 |
|
2245 |
/* reserve some stack space */
|
2246 |
frame_size = TCG_STATIC_CALL_ARGS_SIZE; |
2247 |
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
2248 |
~(TCG_TARGET_STACK_ALIGN - 1);
|
2249 |
|
2250 |
/* First emit adhoc function descriptor */
|
2251 |
*(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */ |
2252 |
s->code_ptr += 16; /* skip GP */ |
2253 |
|
2254 |
/* prologue */
|
2255 |
tcg_out_bundle(s, mII, |
2256 |
tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34, |
2257 |
TCG_REG_R33, 32, 24, 0), |
2258 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
2259 |
TCG_REG_B6, TCG_REG_R32, 0),
|
2260 |
tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, |
2261 |
TCG_REG_R32, TCG_REG_B0)); |
2262 |
tcg_out_bundle(s, miB, |
2263 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
2264 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
2265 |
TCG_REG_R12, -frame_size, TCG_REG_R12), |
2266 |
tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
2267 |
|
2268 |
/* epilogue */
|
2269 |
tb_ret_addr = s->code_ptr; |
2270 |
tcg_out_bundle(s, miI, |
2271 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
2272 |
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
2273 |
TCG_REG_B0, TCG_REG_R32, 0),
|
2274 |
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
2275 |
TCG_REG_R12, frame_size, TCG_REG_R12)); |
2276 |
tcg_out_bundle(s, miB, |
2277 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
2278 |
tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26, |
2279 |
TCG_REG_PFS, TCG_REG_R33), |
2280 |
tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4, |
2281 |
TCG_REG_B0)); |
2282 |
} |
2283 |
|
2284 |
void tcg_target_init(TCGContext *s)
|
2285 |
{ |
2286 |
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], |
2287 |
0xffffffffffffffffull);
|
2288 |
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], |
2289 |
0xffffffffffffffffull);
|
2290 |
tcg_regset_set(tcg_target_call_clobber_regs, |
2291 |
(1 << TCG_REG_R8) |
|
2292 |
(1 << TCG_REG_R9) |
|
2293 |
(1 << TCG_REG_R10) |
|
2294 |
(1 << TCG_REG_R11) |
|
2295 |
(1 << TCG_REG_R13) |
|
2296 |
(1 << TCG_REG_R14) |
|
2297 |
(1 << TCG_REG_R15) |
|
2298 |
(1 << TCG_REG_R16) |
|
2299 |
(1 << TCG_REG_R17) |
|
2300 |
(1 << TCG_REG_R18) |
|
2301 |
(1 << TCG_REG_R19) |
|
2302 |
(1 << TCG_REG_R20) |
|
2303 |
(1 << TCG_REG_R21) |
|
2304 |
(1 << TCG_REG_R22) |
|
2305 |
(1 << TCG_REG_R23) |
|
2306 |
(1 << TCG_REG_R24) |
|
2307 |
(1 << TCG_REG_R25) |
|
2308 |
(1 << TCG_REG_R26) |
|
2309 |
(1 << TCG_REG_R27) |
|
2310 |
(1 << TCG_REG_R28) |
|
2311 |
(1 << TCG_REG_R29) |
|
2312 |
(1 << TCG_REG_R30) |
|
2313 |
(1 << TCG_REG_R31));
|
2314 |
tcg_regset_clear(s->reserved_regs); |
2315 |
|
2316 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
|
2317 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
|
2318 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
|
2319 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
|
2320 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
|
2321 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
|
2322 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* PFS */
|
2323 |
|
2324 |
tcg_add_target_add_op_defs(ia64_op_defs); |
2325 |
} |