root / hw / char / ipoctal232.c @ 47b43a1f
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/*
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* QEMU GE IP-Octal 232 IndustryPack emulation
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*
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* Copyright (C) 2012 Igalia, S.L.
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* Author: Alberto Garcia <agarcia@igalia.com>
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*
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* This code is licensed under the GNU GPL v2 or (at your option) any
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* later version.
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*/
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#include "ipack.h" |
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#include "qemu/bitops.h" |
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#include "char/char.h" |
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/* #define DEBUG_IPOCTAL */
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#ifdef DEBUG_IPOCTAL
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#define DPRINTF2(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF2(fmt, ...) do { } while (0) |
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#endif
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#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__) |
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#define RX_FIFO_SIZE 3 |
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/* The IP-Octal has 8 channels (a-h)
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divided into 4 blocks (A-D) */
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#define N_CHANNELS 8 |
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#define N_BLOCKS 4 |
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#define REG_MRa 0x01 |
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#define REG_MRb 0x11 |
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#define REG_SRa 0x03 |
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#define REG_SRb 0x13 |
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#define REG_CSRa 0x03 |
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#define REG_CSRb 0x13 |
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#define REG_CRa 0x05 |
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#define REG_CRb 0x15 |
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#define REG_RHRa 0x07 |
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#define REG_RHRb 0x17 |
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#define REG_THRa 0x07 |
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#define REG_THRb 0x17 |
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#define REG_ACR 0x09 |
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#define REG_ISR 0x0B |
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#define REG_IMR 0x0B |
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#define REG_OPCR 0x1B |
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|
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#define CR_ENABLE_RX BIT(0) |
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#define CR_DISABLE_RX BIT(1) |
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#define CR_ENABLE_TX BIT(2) |
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#define CR_DISABLE_TX BIT(3) |
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#define CR_CMD(cr) ((cr) >> 4) |
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#define CR_NO_OP 0 |
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#define CR_RESET_MR 1 |
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#define CR_RESET_RX 2 |
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#define CR_RESET_TX 3 |
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#define CR_RESET_ERR 4 |
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#define CR_RESET_BRKINT 5 |
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#define CR_START_BRK 6 |
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#define CR_STOP_BRK 7 |
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#define CR_ASSERT_RTSN 8 |
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#define CR_NEGATE_RTSN 9 |
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#define CR_TIMEOUT_ON 10 |
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#define CR_TIMEOUT_OFF 12 |
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|
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#define SR_RXRDY BIT(0) |
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#define SR_FFULL BIT(1) |
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#define SR_TXRDY BIT(2) |
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#define SR_TXEMT BIT(3) |
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#define SR_OVERRUN BIT(4) |
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#define SR_PARITY BIT(5) |
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#define SR_FRAMING BIT(6) |
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#define SR_BREAK BIT(7) |
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#define ISR_TXRDYA BIT(0) |
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#define ISR_RXRDYA BIT(1) |
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#define ISR_BREAKA BIT(2) |
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#define ISR_CNTRDY BIT(3) |
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#define ISR_TXRDYB BIT(4) |
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#define ISR_RXRDYB BIT(5) |
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#define ISR_BREAKB BIT(6) |
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#define ISR_MPICHG BIT(7) |
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#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0)) |
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#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1)) |
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#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2)) |
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typedef struct IPOctalState IPOctalState; |
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typedef struct SCC2698Channel SCC2698Channel; |
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typedef struct SCC2698Block SCC2698Block; |
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struct SCC2698Channel {
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IPOctalState *ipoctal; |
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CharDriverState *dev; |
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bool rx_enabled;
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uint8_t mr[2];
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uint8_t mr_idx; |
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uint8_t sr; |
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uint8_t rhr[RX_FIFO_SIZE]; |
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uint8_t rhr_idx; |
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uint8_t rx_pending; |
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}; |
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struct SCC2698Block {
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uint8_t imr; |
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uint8_t isr; |
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}; |
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struct IPOctalState {
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IPackDevice dev; |
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SCC2698Channel ch[N_CHANNELS]; |
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SCC2698Block blk[N_BLOCKS]; |
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uint8_t irq_vector; |
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}; |
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#define TYPE_IPOCTAL "ipoctal232" |
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#define IPOCTAL(obj) \
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OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL) |
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static const VMStateDescription vmstate_scc2698_channel = { |
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.name = "scc2698_channel",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_BOOL(rx_enabled, SCC2698Channel), |
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VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
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VMSTATE_UINT8(mr_idx, SCC2698Channel), |
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VMSTATE_UINT8(sr, SCC2698Channel), |
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VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE), |
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VMSTATE_UINT8(rhr_idx, SCC2698Channel), |
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VMSTATE_UINT8(rx_pending, SCC2698Channel), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_scc2698_block = { |
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.name = "scc2698_block",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT8(imr, SCC2698Block), |
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VMSTATE_UINT8(isr, SCC2698Block), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_ipoctal = { |
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.name = "ipoctal232",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_IPACK_DEVICE(dev, IPOctalState), |
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VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
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vmstate_scc2698_channel, SCC2698Channel), |
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VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
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vmstate_scc2698_block, SCC2698Block), |
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VMSTATE_UINT8(irq_vector, IPOctalState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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/* data[10] is 0x0C, not 0x0B as the doc says */
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static const uint8_t id_prom_data[] = { |
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0x49, 0x50, 0x41, 0x43, 0xF0, 0x22, |
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0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC |
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}; |
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static void update_irq(IPOctalState *dev, unsigned block) |
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{ |
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/* Blocks A and B interrupt on INT0#, C and D on INT1#.
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Thus, to get the status we have to check two blocks. */
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SCC2698Block *blk0 = &dev->blk[block]; |
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SCC2698Block *blk1 = &dev->blk[block^1];
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unsigned intno = block / 2; |
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if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
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qemu_irq_raise(dev->dev.irq[intno]); |
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} else {
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qemu_irq_lower(dev->dev.irq[intno]); |
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} |
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} |
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static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val) |
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{ |
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SCC2698Channel *ch = &dev->ch[channel]; |
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SCC2698Block *blk = &dev->blk[channel / 2];
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DPRINTF("Write CR%c %u: ", channel + 'a', val); |
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/* The lower 4 bits are used to enable and disable Tx and Rx */
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if (val & CR_ENABLE_RX) {
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DPRINTF2("Rx on, ");
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ch->rx_enabled = true;
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} |
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if (val & CR_DISABLE_RX) {
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DPRINTF2("Rx off, ");
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ch->rx_enabled = false;
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} |
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if (val & CR_ENABLE_TX) {
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DPRINTF2("Tx on, ");
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ch->sr |= SR_TXRDY | SR_TXEMT; |
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blk->isr |= ISR_TXRDY(channel); |
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} |
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if (val & CR_DISABLE_TX) {
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DPRINTF2("Tx off, ");
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ch->sr &= ~(SR_TXRDY | SR_TXEMT); |
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blk->isr &= ~ISR_TXRDY(channel); |
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} |
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DPRINTF2("cmd: ");
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/* The rest of the bits implement different commands */
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switch (CR_CMD(val)) {
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case CR_NO_OP:
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DPRINTF2("none");
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break;
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case CR_RESET_MR:
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DPRINTF2("reset MR");
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ch->mr_idx = 0;
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break;
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case CR_RESET_RX:
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DPRINTF2("reset Rx");
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ch->rx_enabled = false;
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ch->rx_pending = 0;
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ch->sr &= ~SR_RXRDY; |
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blk->isr &= ~ISR_RXRDY(channel); |
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break;
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case CR_RESET_TX:
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DPRINTF2("reset Tx");
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ch->sr &= ~(SR_TXRDY | SR_TXEMT); |
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blk->isr &= ~ISR_TXRDY(channel); |
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break;
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case CR_RESET_ERR:
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DPRINTF2("reset err");
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ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK); |
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break;
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case CR_RESET_BRKINT:
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DPRINTF2("reset brk ch int");
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blk->isr &= ~(ISR_BREAKA | ISR_BREAKB); |
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break;
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default:
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DPRINTF2("unsupported 0x%x", CR_CMD(val));
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} |
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DPRINTF2("\n");
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} |
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static uint16_t io_read(IPackDevice *ip, uint8_t addr)
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{ |
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IPOctalState *dev = IPOCTAL(ip); |
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uint16_t ret = 0;
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/* addr[7:6]: block (A-D)
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addr[7:5]: channel (a-h)
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addr[5:0]: register */
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unsigned block = addr >> 5; |
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unsigned channel = addr >> 4; |
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/* Big endian, accessed using 8-bit bytes at odd locations */
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unsigned offset = (addr & 0x1F) ^ 1; |
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SCC2698Channel *ch = &dev->ch[channel]; |
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SCC2698Block *blk = &dev->blk[block]; |
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uint8_t old_isr = blk->isr; |
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switch (offset) {
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case REG_MRa:
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case REG_MRb:
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ret = ch->mr[ch->mr_idx]; |
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DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret); |
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ch->mr_idx = 1;
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break;
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case REG_SRa:
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case REG_SRb:
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ret = ch->sr; |
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DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret); |
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break;
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case REG_RHRa:
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case REG_RHRb:
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ret = ch->rhr[ch->rhr_idx]; |
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if (ch->rx_pending > 0) { |
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ch->rx_pending--; |
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if (ch->rx_pending == 0) { |
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ch->sr &= ~SR_RXRDY; |
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blk->isr &= ~ISR_RXRDY(channel); |
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if (ch->dev) {
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qemu_chr_accept_input(ch->dev); |
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} |
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} else {
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ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
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} |
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if (ch->sr & SR_BREAK) {
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ch->sr &= ~SR_BREAK; |
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blk->isr |= ISR_BREAK(channel); |
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} |
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} |
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DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret); |
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break;
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case REG_ISR:
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ret = blk->isr; |
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DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret); |
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break;
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default:
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DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
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} |
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if (old_isr != blk->isr) {
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update_irq(dev, block); |
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} |
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return ret;
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} |
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static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val) |
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{ |
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IPOctalState *dev = IPOCTAL(ip); |
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unsigned reg = val & 0xFF; |
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/* addr[7:6]: block (A-D)
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addr[7:5]: channel (a-h)
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addr[5:0]: register */
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unsigned block = addr >> 5; |
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unsigned channel = addr >> 4; |
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/* Big endian, accessed using 8-bit bytes at odd locations */
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unsigned offset = (addr & 0x1F) ^ 1; |
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SCC2698Channel *ch = &dev->ch[channel]; |
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SCC2698Block *blk = &dev->blk[block]; |
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uint8_t old_isr = blk->isr; |
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uint8_t old_imr = blk->imr; |
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switch (offset) {
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case REG_MRa:
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case REG_MRb:
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ch->mr[ch->mr_idx] = reg; |
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DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg); |
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ch->mr_idx = 1;
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break;
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/* Not implemented */
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case REG_CSRa:
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case REG_CSRb:
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DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg); |
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break;
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case REG_CRa:
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case REG_CRb:
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write_cr(dev, channel, reg); |
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break;
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case REG_THRa:
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case REG_THRb:
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if (ch->sr & SR_TXRDY) {
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DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg); |
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if (ch->dev) {
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uint8_t thr = reg; |
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qemu_chr_fe_write(ch->dev, &thr, 1);
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} |
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} else {
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DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg); |
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} |
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break;
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/* Not implemented */
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case REG_ACR:
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DPRINTF("Write ACR%c 0x%x\n", block + 'A', val); |
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break;
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case REG_IMR:
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DPRINTF("Write IMR%c 0x%x\n", block + 'A', val); |
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blk->imr = reg; |
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break;
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|
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/* Not implemented */
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case REG_OPCR:
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DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val); |
383 |
break;
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|
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default:
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DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
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} |
388 |
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if (old_isr != blk->isr || old_imr != blk->imr) {
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update_irq(dev, block); |
391 |
} |
392 |
} |
393 |
|
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static uint16_t id_read(IPackDevice *ip, uint8_t addr)
|
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{ |
396 |
uint16_t ret = 0;
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unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */ |
398 |
|
399 |
if (pos < ARRAY_SIZE(id_prom_data)) {
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ret = id_prom_data[pos]; |
401 |
} else {
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402 |
DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr);
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} |
404 |
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return ret;
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} |
407 |
|
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static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val) |
409 |
{ |
410 |
IPOctalState *dev = IPOCTAL(ip); |
411 |
if (addr == 1) { |
412 |
DPRINTF("Write IRQ vector: %u\n", (unsigned) val); |
413 |
dev->irq_vector = val; /* Undocumented, but the hw works like that */
|
414 |
} else {
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415 |
DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
|
416 |
} |
417 |
} |
418 |
|
419 |
static uint16_t int_read(IPackDevice *ip, uint8_t addr)
|
420 |
{ |
421 |
IPOctalState *dev = IPOCTAL(ip); |
422 |
/* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
|
423 |
if (addr != 0 && addr != 2) { |
424 |
DPRINTF("Attempt to read from 0x%x\n", addr);
|
425 |
return 0; |
426 |
} else {
|
427 |
/* Update interrupts if necessary */
|
428 |
update_irq(dev, addr); |
429 |
return dev->irq_vector;
|
430 |
} |
431 |
} |
432 |
|
433 |
static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val) |
434 |
{ |
435 |
DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
|
436 |
} |
437 |
|
438 |
static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
|
439 |
{ |
440 |
DPRINTF("Attempt to read from 0x%x\n", addr);
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441 |
return 0; |
442 |
} |
443 |
|
444 |
static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val) |
445 |
{ |
446 |
DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
|
447 |
} |
448 |
|
449 |
static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
|
450 |
{ |
451 |
DPRINTF("Attempt to read from 0x%x\n", addr);
|
452 |
return 0; |
453 |
} |
454 |
|
455 |
static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val) |
456 |
{ |
457 |
IPOctalState *dev = IPOCTAL(ip); |
458 |
if (addr == 1) { |
459 |
DPRINTF("Write IRQ vector: %u\n", (unsigned) val); |
460 |
dev->irq_vector = val; |
461 |
} else {
|
462 |
DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
|
463 |
} |
464 |
} |
465 |
|
466 |
static int hostdev_can_receive(void *opaque) |
467 |
{ |
468 |
SCC2698Channel *ch = opaque; |
469 |
int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
|
470 |
return ch->rx_enabled ? available_bytes : 0; |
471 |
} |
472 |
|
473 |
static void hostdev_receive(void *opaque, const uint8_t *buf, int size) |
474 |
{ |
475 |
SCC2698Channel *ch = opaque; |
476 |
IPOctalState *dev = ch->ipoctal; |
477 |
unsigned pos = ch->rhr_idx + ch->rx_pending;
|
478 |
int i;
|
479 |
|
480 |
assert(size + ch->rx_pending <= RX_FIFO_SIZE); |
481 |
|
482 |
/* Copy data to the RxFIFO */
|
483 |
for (i = 0; i < size; i++) { |
484 |
pos %= RX_FIFO_SIZE; |
485 |
ch->rhr[pos++] = buf[i]; |
486 |
} |
487 |
|
488 |
ch->rx_pending += size; |
489 |
|
490 |
/* If the RxFIFO was empty raise an interrupt */
|
491 |
if (!(ch->sr & SR_RXRDY)) {
|
492 |
unsigned block, channel = 0; |
493 |
/* Find channel number to update the ISR register */
|
494 |
while (&dev->ch[channel] != ch) {
|
495 |
channel++; |
496 |
} |
497 |
block = channel / 2;
|
498 |
dev->blk[block].isr |= ISR_RXRDY(channel); |
499 |
ch->sr |= SR_RXRDY; |
500 |
update_irq(dev, block); |
501 |
} |
502 |
} |
503 |
|
504 |
static void hostdev_event(void *opaque, int event) |
505 |
{ |
506 |
SCC2698Channel *ch = opaque; |
507 |
switch (event) {
|
508 |
case CHR_EVENT_OPENED:
|
509 |
DPRINTF("Device %s opened\n", ch->dev->label);
|
510 |
break;
|
511 |
case CHR_EVENT_BREAK: {
|
512 |
uint8_t zero = 0;
|
513 |
DPRINTF("Device %s received break\n", ch->dev->label);
|
514 |
|
515 |
if (!(ch->sr & SR_BREAK)) {
|
516 |
IPOctalState *dev = ch->ipoctal; |
517 |
unsigned block, channel = 0; |
518 |
|
519 |
while (&dev->ch[channel] != ch) {
|
520 |
channel++; |
521 |
} |
522 |
block = channel / 2;
|
523 |
|
524 |
ch->sr |= SR_BREAK; |
525 |
dev->blk[block].isr |= ISR_BREAK(channel); |
526 |
} |
527 |
|
528 |
/* Put a zero character in the buffer */
|
529 |
hostdev_receive(ch, &zero, 1);
|
530 |
} |
531 |
break;
|
532 |
default:
|
533 |
DPRINTF("Device %s received event %d\n", ch->dev->label, event);
|
534 |
} |
535 |
} |
536 |
|
537 |
static int ipoctal_init(IPackDevice *ip) |
538 |
{ |
539 |
IPOctalState *s = IPOCTAL(ip); |
540 |
unsigned i;
|
541 |
|
542 |
for (i = 0; i < N_CHANNELS; i++) { |
543 |
SCC2698Channel *ch = &s->ch[i]; |
544 |
ch->ipoctal = s; |
545 |
|
546 |
/* Redirect IP-Octal channels to host character devices */
|
547 |
if (ch->dev) {
|
548 |
qemu_chr_add_handlers(ch->dev, hostdev_can_receive, |
549 |
hostdev_receive, hostdev_event, ch); |
550 |
DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
|
551 |
} else {
|
552 |
DPRINTF("Could not redirect channel %u, no chardev set\n", i);
|
553 |
} |
554 |
} |
555 |
|
556 |
return 0; |
557 |
} |
558 |
|
559 |
static Property ipoctal_properties[] = {
|
560 |
DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev), |
561 |
DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev), |
562 |
DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev), |
563 |
DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev), |
564 |
DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev), |
565 |
DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev), |
566 |
DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev), |
567 |
DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev), |
568 |
DEFINE_PROP_END_OF_LIST(), |
569 |
}; |
570 |
|
571 |
static void ipoctal_class_init(ObjectClass *klass, void *data) |
572 |
{ |
573 |
DeviceClass *dc = DEVICE_CLASS(klass); |
574 |
IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass); |
575 |
|
576 |
ic->init = ipoctal_init; |
577 |
ic->io_read = io_read; |
578 |
ic->io_write = io_write; |
579 |
ic->id_read = id_read; |
580 |
ic->id_write = id_write; |
581 |
ic->int_read = int_read; |
582 |
ic->int_write = int_write; |
583 |
ic->mem_read16 = mem_read16; |
584 |
ic->mem_write16 = mem_write16; |
585 |
ic->mem_read8 = mem_read8; |
586 |
ic->mem_write8 = mem_write8; |
587 |
|
588 |
dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
|
589 |
dc->props = ipoctal_properties; |
590 |
dc->vmsd = &vmstate_ipoctal; |
591 |
} |
592 |
|
593 |
static const TypeInfo ipoctal_info = { |
594 |
.name = TYPE_IPOCTAL, |
595 |
.parent = TYPE_IPACK_DEVICE, |
596 |
.instance_size = sizeof(IPOctalState),
|
597 |
.class_init = ipoctal_class_init, |
598 |
}; |
599 |
|
600 |
static void ipoctal_register_types(void) |
601 |
{ |
602 |
type_register_static(&ipoctal_info); |
603 |
} |
604 |
|
605 |
type_init(ipoctal_register_types) |