root / hw / net / ne2000.c @ 47b43a1f
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/*
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* QEMU NE2000 emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/pci/pci.h" |
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#include "net/net.h" |
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#include "ne2000.h" |
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#include "hw/loader.h" |
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#include "sysemu/sysemu.h" |
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|
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/* debug NE2000 card */
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//#define DEBUG_NE2000
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#define MAX_ETH_FRAME_SIZE 1514 |
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|
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#define E8390_CMD 0x00 /* The command register (for all pages) */ |
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
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#define EN0_TSR 0x04 /* Transmit status reg RD */ |
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#define EN0_TPSR 0x04 /* Transmit starting page WR */ |
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#define EN0_NCR 0x05 /* Number of collision reg RD */ |
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
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#define EN0_FIFO 0x06 /* FIFO RD */ |
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
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#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
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#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
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#define EN0_RSR 0x0c /* rx status reg RD */ |
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#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
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#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
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#define EN0_DCFG 0x0e /* Data configuration reg WR */ |
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
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|
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#define EN1_PHYS 0x11 |
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#define EN1_CURPAG 0x17 |
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#define EN1_MULT 0x18 |
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|
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#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
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#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
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|
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#define EN3_CONFIG0 0x33 |
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#define EN3_CONFIG1 0x34 |
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#define EN3_CONFIG2 0x35 |
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#define EN3_CONFIG3 0x36 |
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|
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */ |
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#define E8390_START 0x02 /* Start the chip, clear reset */ |
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#define E8390_TRANS 0x04 /* Transmit a frame */ |
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#define E8390_RREAD 0x08 /* Remote read */ |
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#define E8390_RWRITE 0x10 /* Remote write */ |
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#define E8390_NODMA 0x20 /* Remote DMA */ |
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#define E8390_PAGE0 0x00 /* Select page chip registers */ |
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#define E8390_PAGE1 0x40 /* using the two high-order bits */ |
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
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|
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */ |
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#define ENISR_TX 0x02 /* Transmitter, no error */ |
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
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#define ENISR_RDC 0x40 /* remote dma complete */ |
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#define ENISR_RESET 0x80 /* Reset completed */ |
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#define ENISR_ALL 0x3f /* Interrupts we will enable */ |
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|
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */ |
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#define ENRSR_CRC 0x02 /* CRC error */ |
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#define ENRSR_FAE 0x04 /* frame alignment error */ |
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#define ENRSR_FO 0x08 /* FIFO overrun */ |
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#define ENRSR_MPA 0x10 /* missed pkt */ |
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#define ENRSR_PHY 0x20 /* physical/multicast address */ |
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
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#define ENRSR_DEF 0x80 /* deferring */ |
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|
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
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typedef struct PCINE2000State { |
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PCIDevice dev; |
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NE2000State ne2000; |
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} PCINE2000State; |
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void ne2000_reset(NE2000State *s)
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{
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int i;
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s->isr = ENISR_RESET; |
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memcpy(s->mem, &s->c.macaddr, 6);
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s->mem[14] = 0x57; |
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s->mem[15] = 0x57; |
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|
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/* duplicate prom data */
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for(i = 15;i >= 0; i--) { |
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s->mem[2 * i] = s->mem[i];
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s->mem[2 * i + 1] = s->mem[i]; |
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} |
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} |
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|
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static void ne2000_update_irq(NE2000State *s) |
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{
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int isr;
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isr = (s->isr & s->imr) & 0x7f;
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#if defined(DEBUG_NE2000)
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printf("NE2000: Set IRQ to %d (%02x %02x)\n",
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isr ? 1 : 0, s->isr, s->imr); |
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#endif
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qemu_set_irq(s->irq, (isr != 0));
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} |
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static int ne2000_buffer_full(NE2000State *s) |
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{
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int avail, index, boundary;
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index = s->curpag << 8;
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boundary = s->boundary << 8;
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if (index < boundary)
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avail = boundary - index; |
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else
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avail = (s->stop - s->start) - (index - boundary); |
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if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
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return 1; |
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return 0; |
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} |
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int ne2000_can_receive(NetClientState *nc)
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{
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NE2000State *s = qemu_get_nic_opaque(nc); |
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if (s->cmd & E8390_STOP)
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return 1; |
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return !ne2000_buffer_full(s);
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} |
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#define MIN_BUF_SIZE 60 |
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ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
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{
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NE2000State *s = qemu_get_nic_opaque(nc); |
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int size = size_;
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uint8_t *p; |
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unsigned int total_len, next, avail, len, index, mcast_idx; |
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uint8_t buf1[60];
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static const uint8_t broadcast_macaddr[6] = |
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{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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#if defined(DEBUG_NE2000)
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printf("NE2000: received len=%d\n", size);
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#endif
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if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
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return -1; |
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|
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/* XXX: check this */
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if (s->rxcr & 0x10) { |
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/* promiscuous: receive all */
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} else {
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if (!memcmp(buf, broadcast_macaddr, 6)) { |
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/* broadcast address */
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if (!(s->rxcr & 0x04)) |
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return size;
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} else if (buf[0] & 0x01) { |
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/* multicast */
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if (!(s->rxcr & 0x08)) |
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return size;
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mcast_idx = compute_mcast_idx(buf); |
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if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
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return size;
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} else if (s->mem[0] == buf[0] && |
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s->mem[2] == buf[1] && |
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s->mem[4] == buf[2] && |
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s->mem[6] == buf[3] && |
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s->mem[8] == buf[4] && |
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s->mem[10] == buf[5]) { |
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/* match */
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} else {
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return size;
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} |
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} |
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|
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|
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/* if too small buffer, then expand it */
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if (size < MIN_BUF_SIZE) {
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memcpy(buf1, buf, size); |
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memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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buf = buf1; |
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size = MIN_BUF_SIZE; |
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} |
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|
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index = s->curpag << 8;
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/* 4 bytes for header */
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total_len = size + 4;
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/* address for next packet (4 bytes for CRC) */
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next = index + ((total_len + 4 + 255) & ~0xff); |
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if (next >= s->stop)
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next -= (s->stop - s->start); |
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/* prepare packet header */
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p = s->mem + index; |
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s->rsr = ENRSR_RXOK; /* receive status */
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/* XXX: check this */
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if (buf[0] & 0x01) |
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s->rsr |= ENRSR_PHY; |
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p[0] = s->rsr;
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p[1] = next >> 8; |
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p[2] = total_len;
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p[3] = total_len >> 8; |
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index += 4;
|
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|
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/* write packet data */
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while (size > 0) { |
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if (index <= s->stop)
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avail = s->stop - index; |
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else
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avail = 0;
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len = size; |
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if (len > avail)
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len = avail; |
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memcpy(s->mem + index, buf, len); |
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buf += len; |
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index += len; |
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if (index == s->stop)
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index = s->start; |
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size -= len; |
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} |
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s->curpag = next >> 8;
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|
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/* now we can signal we have received something */
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s->isr |= ENISR_RX; |
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ne2000_update_irq(s); |
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|
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return size_;
|
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} |
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|
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static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{
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NE2000State *s = opaque; |
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int offset, page, index;
|
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|
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addr &= 0xf;
|
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#ifdef DEBUG_NE2000
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printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
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#endif
|
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if (addr == E8390_CMD) {
|
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/* control register */
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s->cmd = val; |
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if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
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s->isr &= ~ENISR_RESET; |
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/* test specific case: zero length transfer */
|
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if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
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s->rcnt == 0) {
|
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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} |
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if (val & E8390_TRANS) {
|
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index = (s->tpsr << 8);
|
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/* XXX: next 2 lines are a hack to make netware 3.11 work */
|
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if (index >= NE2000_PMEM_END)
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index -= NE2000_PMEM_SIZE; |
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/* fail safe: check range on the transmitted length */
|
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if (index + s->tcnt <= NE2000_PMEM_END) {
|
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qemu_send_packet(qemu_get_queue(s->nic), s->mem + index, |
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s->tcnt); |
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} |
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/* signal end of transfer */
|
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s->tsr = ENTSR_PTX; |
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s->isr |= ENISR_TX; |
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s->cmd &= ~E8390_TRANS; |
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ne2000_update_irq(s); |
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} |
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} |
| 313 |
} else {
|
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page = s->cmd >> 6;
|
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offset = addr | (page << 4);
|
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switch(offset) {
|
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case EN0_STARTPG:
|
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s->start = val << 8;
|
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break;
|
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case EN0_STOPPG:
|
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s->stop = val << 8;
|
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break;
|
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case EN0_BOUNDARY:
|
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s->boundary = val; |
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break;
|
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case EN0_IMR:
|
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s->imr = val; |
| 328 |
ne2000_update_irq(s); |
| 329 |
break;
|
| 330 |
case EN0_TPSR:
|
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s->tpsr = val; |
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break;
|
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case EN0_TCNTLO:
|
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s->tcnt = (s->tcnt & 0xff00) | val;
|
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break;
|
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case EN0_TCNTHI:
|
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s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
| 338 |
break;
|
| 339 |
case EN0_RSARLO:
|
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s->rsar = (s->rsar & 0xff00) | val;
|
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break;
|
| 342 |
case EN0_RSARHI:
|
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s->rsar = (s->rsar & 0x00ff) | (val << 8); |
| 344 |
break;
|
| 345 |
case EN0_RCNTLO:
|
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s->rcnt = (s->rcnt & 0xff00) | val;
|
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break;
|
| 348 |
case EN0_RCNTHI:
|
| 349 |
s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
| 350 |
break;
|
| 351 |
case EN0_RXCR:
|
| 352 |
s->rxcr = val; |
| 353 |
break;
|
| 354 |
case EN0_DCFG:
|
| 355 |
s->dcfg = val; |
| 356 |
break;
|
| 357 |
case EN0_ISR:
|
| 358 |
s->isr &= ~(val & 0x7f);
|
| 359 |
ne2000_update_irq(s); |
| 360 |
break;
|
| 361 |
case EN1_PHYS ... EN1_PHYS + 5: |
| 362 |
s->phys[offset - EN1_PHYS] = val; |
| 363 |
break;
|
| 364 |
case EN1_CURPAG:
|
| 365 |
s->curpag = val; |
| 366 |
break;
|
| 367 |
case EN1_MULT ... EN1_MULT + 7: |
| 368 |
s->mult[offset - EN1_MULT] = val; |
| 369 |
break;
|
| 370 |
} |
| 371 |
} |
| 372 |
} |
| 373 |
|
| 374 |
static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
| 375 |
{
|
| 376 |
NE2000State *s = opaque; |
| 377 |
int offset, page, ret;
|
| 378 |
|
| 379 |
addr &= 0xf;
|
| 380 |
if (addr == E8390_CMD) {
|
| 381 |
ret = s->cmd; |
| 382 |
} else {
|
| 383 |
page = s->cmd >> 6;
|
| 384 |
offset = addr | (page << 4);
|
| 385 |
switch(offset) {
|
| 386 |
case EN0_TSR:
|
| 387 |
ret = s->tsr; |
| 388 |
break;
|
| 389 |
case EN0_BOUNDARY:
|
| 390 |
ret = s->boundary; |
| 391 |
break;
|
| 392 |
case EN0_ISR:
|
| 393 |
ret = s->isr; |
| 394 |
break;
|
| 395 |
case EN0_RSARLO:
|
| 396 |
ret = s->rsar & 0x00ff;
|
| 397 |
break;
|
| 398 |
case EN0_RSARHI:
|
| 399 |
ret = s->rsar >> 8;
|
| 400 |
break;
|
| 401 |
case EN1_PHYS ... EN1_PHYS + 5: |
| 402 |
ret = s->phys[offset - EN1_PHYS]; |
| 403 |
break;
|
| 404 |
case EN1_CURPAG:
|
| 405 |
ret = s->curpag; |
| 406 |
break;
|
| 407 |
case EN1_MULT ... EN1_MULT + 7: |
| 408 |
ret = s->mult[offset - EN1_MULT]; |
| 409 |
break;
|
| 410 |
case EN0_RSR:
|
| 411 |
ret = s->rsr; |
| 412 |
break;
|
| 413 |
case EN2_STARTPG:
|
| 414 |
ret = s->start >> 8;
|
| 415 |
break;
|
| 416 |
case EN2_STOPPG:
|
| 417 |
ret = s->stop >> 8;
|
| 418 |
break;
|
| 419 |
case EN0_RTL8029ID0:
|
| 420 |
ret = 0x50;
|
| 421 |
break;
|
| 422 |
case EN0_RTL8029ID1:
|
| 423 |
ret = 0x43;
|
| 424 |
break;
|
| 425 |
case EN3_CONFIG0:
|
| 426 |
ret = 0; /* 10baseT media */ |
| 427 |
break;
|
| 428 |
case EN3_CONFIG2:
|
| 429 |
ret = 0x40; /* 10baseT active */ |
| 430 |
break;
|
| 431 |
case EN3_CONFIG3:
|
| 432 |
ret = 0x40; /* Full duplex */ |
| 433 |
break;
|
| 434 |
default:
|
| 435 |
ret = 0x00;
|
| 436 |
break;
|
| 437 |
} |
| 438 |
} |
| 439 |
#ifdef DEBUG_NE2000
|
| 440 |
printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
| 441 |
#endif
|
| 442 |
return ret;
|
| 443 |
} |
| 444 |
|
| 445 |
static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
| 446 |
uint32_t val) |
| 447 |
{
|
| 448 |
if (addr < 32 || |
| 449 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 450 |
s->mem[addr] = val; |
| 451 |
} |
| 452 |
} |
| 453 |
|
| 454 |
static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
| 455 |
uint32_t val) |
| 456 |
{
|
| 457 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 458 |
if (addr < 32 || |
| 459 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 460 |
*(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
| 461 |
} |
| 462 |
} |
| 463 |
|
| 464 |
static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
| 465 |
uint32_t val) |
| 466 |
{
|
| 467 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 468 |
if (addr < 32 || |
| 469 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 470 |
cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
| 471 |
} |
| 472 |
} |
| 473 |
|
| 474 |
static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
| 475 |
{
|
| 476 |
if (addr < 32 || |
| 477 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 478 |
return s->mem[addr];
|
| 479 |
} else {
|
| 480 |
return 0xff; |
| 481 |
} |
| 482 |
} |
| 483 |
|
| 484 |
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
| 485 |
{
|
| 486 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 487 |
if (addr < 32 || |
| 488 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 489 |
return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
| 490 |
} else {
|
| 491 |
return 0xffff; |
| 492 |
} |
| 493 |
} |
| 494 |
|
| 495 |
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
| 496 |
{
|
| 497 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 498 |
if (addr < 32 || |
| 499 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 500 |
return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
| 501 |
} else {
|
| 502 |
return 0xffffffff; |
| 503 |
} |
| 504 |
} |
| 505 |
|
| 506 |
static inline void ne2000_dma_update(NE2000State *s, int len) |
| 507 |
{
|
| 508 |
s->rsar += len; |
| 509 |
/* wrap */
|
| 510 |
/* XXX: check what to do if rsar > stop */
|
| 511 |
if (s->rsar == s->stop)
|
| 512 |
s->rsar = s->start; |
| 513 |
|
| 514 |
if (s->rcnt <= len) {
|
| 515 |
s->rcnt = 0;
|
| 516 |
/* signal end of transfer */
|
| 517 |
s->isr |= ENISR_RDC; |
| 518 |
ne2000_update_irq(s); |
| 519 |
} else {
|
| 520 |
s->rcnt -= len; |
| 521 |
} |
| 522 |
} |
| 523 |
|
| 524 |
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 525 |
{
|
| 526 |
NE2000State *s = opaque; |
| 527 |
|
| 528 |
#ifdef DEBUG_NE2000
|
| 529 |
printf("NE2000: asic write val=0x%04x\n", val);
|
| 530 |
#endif
|
| 531 |
if (s->rcnt == 0) |
| 532 |
return;
|
| 533 |
if (s->dcfg & 0x01) { |
| 534 |
/* 16 bit access */
|
| 535 |
ne2000_mem_writew(s, s->rsar, val); |
| 536 |
ne2000_dma_update(s, 2);
|
| 537 |
} else {
|
| 538 |
/* 8 bit access */
|
| 539 |
ne2000_mem_writeb(s, s->rsar, val); |
| 540 |
ne2000_dma_update(s, 1);
|
| 541 |
} |
| 542 |
} |
| 543 |
|
| 544 |
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
| 545 |
{
|
| 546 |
NE2000State *s = opaque; |
| 547 |
int ret;
|
| 548 |
|
| 549 |
if (s->dcfg & 0x01) { |
| 550 |
/* 16 bit access */
|
| 551 |
ret = ne2000_mem_readw(s, s->rsar); |
| 552 |
ne2000_dma_update(s, 2);
|
| 553 |
} else {
|
| 554 |
/* 8 bit access */
|
| 555 |
ret = ne2000_mem_readb(s, s->rsar); |
| 556 |
ne2000_dma_update(s, 1);
|
| 557 |
} |
| 558 |
#ifdef DEBUG_NE2000
|
| 559 |
printf("NE2000: asic read val=0x%04x\n", ret);
|
| 560 |
#endif
|
| 561 |
return ret;
|
| 562 |
} |
| 563 |
|
| 564 |
static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
| 565 |
{
|
| 566 |
NE2000State *s = opaque; |
| 567 |
|
| 568 |
#ifdef DEBUG_NE2000
|
| 569 |
printf("NE2000: asic writel val=0x%04x\n", val);
|
| 570 |
#endif
|
| 571 |
if (s->rcnt == 0) |
| 572 |
return;
|
| 573 |
/* 32 bit access */
|
| 574 |
ne2000_mem_writel(s, s->rsar, val); |
| 575 |
ne2000_dma_update(s, 4);
|
| 576 |
} |
| 577 |
|
| 578 |
static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
| 579 |
{
|
| 580 |
NE2000State *s = opaque; |
| 581 |
int ret;
|
| 582 |
|
| 583 |
/* 32 bit access */
|
| 584 |
ret = ne2000_mem_readl(s, s->rsar); |
| 585 |
ne2000_dma_update(s, 4);
|
| 586 |
#ifdef DEBUG_NE2000
|
| 587 |
printf("NE2000: asic readl val=0x%04x\n", ret);
|
| 588 |
#endif
|
| 589 |
return ret;
|
| 590 |
} |
| 591 |
|
| 592 |
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 593 |
{
|
| 594 |
/* nothing to do (end of reset pulse) */
|
| 595 |
} |
| 596 |
|
| 597 |
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
| 598 |
{
|
| 599 |
NE2000State *s = opaque; |
| 600 |
ne2000_reset(s); |
| 601 |
return 0; |
| 602 |
} |
| 603 |
|
| 604 |
static int ne2000_post_load(void* opaque, int version_id) |
| 605 |
{
|
| 606 |
NE2000State* s = opaque; |
| 607 |
|
| 608 |
if (version_id < 2) { |
| 609 |
s->rxcr = 0x0c;
|
| 610 |
} |
| 611 |
return 0; |
| 612 |
} |
| 613 |
|
| 614 |
const VMStateDescription vmstate_ne2000 = {
|
| 615 |
.name = "ne2000",
|
| 616 |
.version_id = 2,
|
| 617 |
.minimum_version_id = 0,
|
| 618 |
.minimum_version_id_old = 0,
|
| 619 |
.post_load = ne2000_post_load, |
| 620 |
.fields = (VMStateField []) {
|
| 621 |
VMSTATE_UINT8_V(rxcr, NE2000State, 2),
|
| 622 |
VMSTATE_UINT8(cmd, NE2000State), |
| 623 |
VMSTATE_UINT32(start, NE2000State), |
| 624 |
VMSTATE_UINT32(stop, NE2000State), |
| 625 |
VMSTATE_UINT8(boundary, NE2000State), |
| 626 |
VMSTATE_UINT8(tsr, NE2000State), |
| 627 |
VMSTATE_UINT8(tpsr, NE2000State), |
| 628 |
VMSTATE_UINT16(tcnt, NE2000State), |
| 629 |
VMSTATE_UINT16(rcnt, NE2000State), |
| 630 |
VMSTATE_UINT32(rsar, NE2000State), |
| 631 |
VMSTATE_UINT8(rsr, NE2000State), |
| 632 |
VMSTATE_UINT8(isr, NE2000State), |
| 633 |
VMSTATE_UINT8(dcfg, NE2000State), |
| 634 |
VMSTATE_UINT8(imr, NE2000State), |
| 635 |
VMSTATE_BUFFER(phys, NE2000State), |
| 636 |
VMSTATE_UINT8(curpag, NE2000State), |
| 637 |
VMSTATE_BUFFER(mult, NE2000State), |
| 638 |
VMSTATE_UNUSED(4), /* was irq */ |
| 639 |
VMSTATE_BUFFER(mem, NE2000State), |
| 640 |
VMSTATE_END_OF_LIST() |
| 641 |
} |
| 642 |
}; |
| 643 |
|
| 644 |
static const VMStateDescription vmstate_pci_ne2000 = { |
| 645 |
.name = "ne2000",
|
| 646 |
.version_id = 3,
|
| 647 |
.minimum_version_id = 3,
|
| 648 |
.minimum_version_id_old = 3,
|
| 649 |
.fields = (VMStateField []) {
|
| 650 |
VMSTATE_PCI_DEVICE(dev, PCINE2000State), |
| 651 |
VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
|
| 652 |
VMSTATE_END_OF_LIST() |
| 653 |
} |
| 654 |
}; |
| 655 |
|
| 656 |
static uint64_t ne2000_read(void *opaque, hwaddr addr, |
| 657 |
unsigned size)
|
| 658 |
{
|
| 659 |
NE2000State *s = opaque; |
| 660 |
|
| 661 |
if (addr < 0x10 && size == 1) { |
| 662 |
return ne2000_ioport_read(s, addr);
|
| 663 |
} else if (addr == 0x10) { |
| 664 |
if (size <= 2) { |
| 665 |
return ne2000_asic_ioport_read(s, addr);
|
| 666 |
} else {
|
| 667 |
return ne2000_asic_ioport_readl(s, addr);
|
| 668 |
} |
| 669 |
} else if (addr == 0x1f && size == 1) { |
| 670 |
return ne2000_reset_ioport_read(s, addr);
|
| 671 |
} |
| 672 |
return ((uint64_t)1 << (size * 8)) - 1; |
| 673 |
} |
| 674 |
|
| 675 |
static void ne2000_write(void *opaque, hwaddr addr, |
| 676 |
uint64_t data, unsigned size)
|
| 677 |
{
|
| 678 |
NE2000State *s = opaque; |
| 679 |
|
| 680 |
if (addr < 0x10 && size == 1) { |
| 681 |
ne2000_ioport_write(s, addr, data); |
| 682 |
} else if (addr == 0x10) { |
| 683 |
if (size <= 2) { |
| 684 |
ne2000_asic_ioport_write(s, addr, data); |
| 685 |
} else {
|
| 686 |
ne2000_asic_ioport_writel(s, addr, data); |
| 687 |
} |
| 688 |
} else if (addr == 0x1f && size == 1) { |
| 689 |
ne2000_reset_ioport_write(s, addr, data); |
| 690 |
} |
| 691 |
} |
| 692 |
|
| 693 |
static const MemoryRegionOps ne2000_ops = { |
| 694 |
.read = ne2000_read, |
| 695 |
.write = ne2000_write, |
| 696 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 697 |
}; |
| 698 |
|
| 699 |
/***********************************************************/
|
| 700 |
/* PCI NE2000 definitions */
|
| 701 |
|
| 702 |
void ne2000_setup_io(NE2000State *s, unsigned size) |
| 703 |
{
|
| 704 |
memory_region_init_io(&s->io, &ne2000_ops, s, "ne2000", size);
|
| 705 |
} |
| 706 |
|
| 707 |
static void ne2000_cleanup(NetClientState *nc) |
| 708 |
{
|
| 709 |
NE2000State *s = qemu_get_nic_opaque(nc); |
| 710 |
|
| 711 |
s->nic = NULL;
|
| 712 |
} |
| 713 |
|
| 714 |
static NetClientInfo net_ne2000_info = {
|
| 715 |
.type = NET_CLIENT_OPTIONS_KIND_NIC, |
| 716 |
.size = sizeof(NICState),
|
| 717 |
.can_receive = ne2000_can_receive, |
| 718 |
.receive = ne2000_receive, |
| 719 |
.cleanup = ne2000_cleanup, |
| 720 |
}; |
| 721 |
|
| 722 |
static int pci_ne2000_init(PCIDevice *pci_dev) |
| 723 |
{
|
| 724 |
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
| 725 |
NE2000State *s; |
| 726 |
uint8_t *pci_conf; |
| 727 |
|
| 728 |
pci_conf = d->dev.config; |
| 729 |
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
| 730 |
|
| 731 |
s = &d->ne2000; |
| 732 |
ne2000_setup_io(s, 0x100);
|
| 733 |
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
|
| 734 |
s->irq = d->dev.irq[0];
|
| 735 |
|
| 736 |
qemu_macaddr_default_if_unset(&s->c.macaddr); |
| 737 |
ne2000_reset(s); |
| 738 |
|
| 739 |
s->nic = qemu_new_nic(&net_ne2000_info, &s->c, |
| 740 |
object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s); |
| 741 |
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a); |
| 742 |
|
| 743 |
add_boot_device_path(s->c.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
|
| 744 |
|
| 745 |
return 0; |
| 746 |
} |
| 747 |
|
| 748 |
static void pci_ne2000_exit(PCIDevice *pci_dev) |
| 749 |
{
|
| 750 |
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
| 751 |
NE2000State *s = &d->ne2000; |
| 752 |
|
| 753 |
memory_region_destroy(&s->io); |
| 754 |
qemu_del_nic(s->nic); |
| 755 |
} |
| 756 |
|
| 757 |
static Property ne2000_properties[] = {
|
| 758 |
DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c), |
| 759 |
DEFINE_PROP_END_OF_LIST(), |
| 760 |
}; |
| 761 |
|
| 762 |
static void ne2000_class_init(ObjectClass *klass, void *data) |
| 763 |
{
|
| 764 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 765 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 766 |
|
| 767 |
k->init = pci_ne2000_init; |
| 768 |
k->exit = pci_ne2000_exit; |
| 769 |
k->romfile = "efi-ne2k_pci.rom",
|
| 770 |
k->vendor_id = PCI_VENDOR_ID_REALTEK; |
| 771 |
k->device_id = PCI_DEVICE_ID_REALTEK_8029; |
| 772 |
k->class_id = PCI_CLASS_NETWORK_ETHERNET; |
| 773 |
dc->vmsd = &vmstate_pci_ne2000; |
| 774 |
dc->props = ne2000_properties; |
| 775 |
} |
| 776 |
|
| 777 |
static const TypeInfo ne2000_info = { |
| 778 |
.name = "ne2k_pci",
|
| 779 |
.parent = TYPE_PCI_DEVICE, |
| 780 |
.instance_size = sizeof(PCINE2000State),
|
| 781 |
.class_init = ne2000_class_init, |
| 782 |
}; |
| 783 |
|
| 784 |
static void ne2000_register_types(void) |
| 785 |
{
|
| 786 |
type_register_static(&ne2000_info); |
| 787 |
} |
| 788 |
|
| 789 |
type_init(ne2000_register_types) |