root / hw / sd / sdhci.c @ 47b43a1f
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/*
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* SD Association Host Standard Specification v2.0 controller emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Mitsyanko Igor <i.mitsyanko@samsung.com>
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* Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
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*
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* Based on MMC controller for Samsung S5PC1xx-based board emulation
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* by Alexey Merkulov and Vladimir Monakhov.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h" |
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#include "sysemu/blockdev.h" |
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#include "sysemu/dma.h" |
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#include "qemu/timer.h" |
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#include "block/block_int.h" |
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#include "qemu/bitops.h" |
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#include "sdhci.h" |
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/* host controller debug messages */
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#ifndef SDHC_DEBUG
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#define SDHC_DEBUG 0 |
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#endif
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#if SDHC_DEBUG == 0 |
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#define DPRINT_L1(fmt, args...) do { } while (0) |
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#define DPRINT_L2(fmt, args...) do { } while (0) |
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#define ERRPRINT(fmt, args...) do { } while (0) |
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#elif SDHC_DEBUG == 1 |
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#define DPRINT_L1(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) |
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#define DPRINT_L2(fmt, args...) do { } while (0) |
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#define ERRPRINT(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0) |
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#else
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#define DPRINT_L1(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) |
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#define DPRINT_L2(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) |
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#define ERRPRINT(fmt, args...) \
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do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0) |
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#endif
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/* Default SD/MMC host controller features information, which will be
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* presented in CAPABILITIES register of generic SD host controller at reset.
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* If not stated otherwise:
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* 0 - not supported, 1 - supported, other - prohibited.
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*/
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#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ |
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#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ |
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#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ |
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#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ |
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#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ |
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#define SDHC_CAPAB_SDMA 1ul /* SDMA support */ |
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#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ |
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#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ |
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#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ |
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/* Maximum host controller R/W buffers size
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* Possible values: 512, 1024, 2048 bytes */
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#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul |
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/* Maximum clock frequency for SDclock in MHz
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* value in range 10-63 MHz, 0 - not defined */
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#define SDHC_CAPAB_BASECLKFREQ 0ul |
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#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ |
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/* Timeout clock frequency 1-63, 0 - not defined */
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#define SDHC_CAPAB_TOCLKFREQ 0ul |
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/* Now check all parameters and calculate CAPABILITIES REGISTER value */
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#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ |
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SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ |
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SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ |
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SDHC_CAPAB_TOUNIT > 1
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#error Capabilities features can have value 0 or 1 only! |
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#endif
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#if SDHC_CAPAB_MAXBLOCKLENGTH == 512 |
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#define MAX_BLOCK_LENGTH 0ul |
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#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 |
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#define MAX_BLOCK_LENGTH 1ul |
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#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 |
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#define MAX_BLOCK_LENGTH 2ul |
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#else
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#error Max host controller block size can have value 512, 1024 or 2048 only! |
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#endif
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#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ |
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SDHC_CAPAB_BASECLKFREQ > 63
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#error SDclock frequency can have value in range 0, 10-63 only! |
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#endif
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#if SDHC_CAPAB_TOCLKFREQ > 63 |
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#error Timeout clock frequency can have value in range 0-63 only! |
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#endif
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#define SDHC_CAPAB_REG_DEFAULT \
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((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ |
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(SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ |
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(SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ |
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(SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ |
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(SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ |
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(SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ |
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(SDHC_CAPAB_TOCLKFREQ)) |
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#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
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static uint8_t sdhci_slotint(SDHCIState *s)
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{
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return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
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((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || |
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((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); |
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} |
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static inline void sdhci_update_irq(SDHCIState *s) |
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{
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qemu_set_irq(s->irq, sdhci_slotint(s)); |
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} |
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static void sdhci_raise_insertion_irq(void *opaque) |
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{
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SDHCIState *s = (SDHCIState *)opaque; |
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if (s->norintsts & SDHC_NIS_REMOVE) {
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qemu_mod_timer(s->insert_timer, |
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qemu_get_clock_ns(vm_clock) + SDHC_INSERTION_DELAY); |
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} else {
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s->prnsts = 0x1ff0000;
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if (s->norintstsen & SDHC_NISEN_INSERT) {
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s->norintsts |= SDHC_NIS_INSERT; |
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} |
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sdhci_update_irq(s); |
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} |
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} |
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static void sdhci_insert_eject_cb(void *opaque, int irq, int level) |
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{
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SDHCIState *s = (SDHCIState *)opaque; |
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DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); |
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if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
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/* Give target some time to notice card ejection */
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qemu_mod_timer(s->insert_timer, |
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qemu_get_clock_ns(vm_clock) + SDHC_INSERTION_DELAY); |
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} else {
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if (level) {
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s->prnsts = 0x1ff0000;
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if (s->norintstsen & SDHC_NISEN_INSERT) {
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s->norintsts |= SDHC_NIS_INSERT; |
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} |
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} else {
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s->prnsts = 0x1fa0000;
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s->pwrcon &= ~SDHC_POWER_ON; |
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s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; |
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if (s->norintstsen & SDHC_NISEN_REMOVE) {
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s->norintsts |= SDHC_NIS_REMOVE; |
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} |
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} |
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sdhci_update_irq(s); |
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} |
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} |
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static void sdhci_card_readonly_cb(void *opaque, int irq, int level) |
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{
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SDHCIState *s = (SDHCIState *)opaque; |
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if (level) {
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s->prnsts &= ~SDHC_WRITE_PROTECT; |
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} else {
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/* Write enabled */
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s->prnsts |= SDHC_WRITE_PROTECT; |
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} |
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} |
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static void sdhci_reset(SDHCIState *s) |
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{
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qemu_del_timer(s->insert_timer); |
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qemu_del_timer(s->transfer_timer); |
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/* Set all registers to 0. Capabilities registers are not cleared
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* and assumed to always preserve their value, given to them during
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* initialization */
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memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
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sd_set_cb(s->card, s->ro_cb, s->eject_cb); |
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s->data_count = 0;
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s->stopped_state = sdhc_not_stopped; |
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} |
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static void sdhci_do_data_transfer(void *opaque) |
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{
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SDHCIState *s = (SDHCIState *)opaque; |
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SDHCI_GET_CLASS(s)->data_transfer(s); |
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} |
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static void sdhci_send_command(SDHCIState *s) |
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{
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SDRequest request; |
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uint8_t response[16];
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int rlen;
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s->errintsts = 0;
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s->acmd12errsts = 0;
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request.cmd = s->cmdreg >> 8;
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request.arg = s->argument; |
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DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg);
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rlen = sd_do_command(s->card, &request, response); |
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if (s->cmdreg & SDHC_CMD_RESPONSE) {
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if (rlen == 4) { |
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s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | |
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(response[2] << 8) | response[3]; |
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s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; |
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DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); |
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} else if (rlen == 16) { |
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s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | |
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(response[13] << 8) | response[14]; |
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s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | |
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(response[9] << 8) | response[10]; |
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s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | |
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(response[5] << 8) | response[6]; |
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s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | |
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response[2];
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DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
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"64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
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s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); |
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} else {
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ERRPRINT("Timeout waiting for command response\n");
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if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
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s->errintsts |= SDHC_EIS_CMDTIMEOUT; |
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s->norintsts |= SDHC_NIS_ERR; |
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} |
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} |
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if ((s->norintstsen & SDHC_NISEN_TRSCMP) &&
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(s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
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s->norintsts |= SDHC_NIS_TRSCMP; |
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} |
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} else if (rlen != 0 && (s->errintstsen & SDHC_EISEN_CMDIDX)) { |
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s->errintsts |= SDHC_EIS_CMDIDX; |
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s->norintsts |= SDHC_NIS_ERR; |
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} |
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if (s->norintstsen & SDHC_NISEN_CMDCMP) {
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s->norintsts |= SDHC_NIS_CMDCMP; |
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} |
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sdhci_update_irq(s); |
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if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
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sdhci_do_data_transfer(s); |
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} |
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} |
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static void sdhci_end_transfer(SDHCIState *s) |
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{
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/* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
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if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { |
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SDRequest request; |
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uint8_t response[16];
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request.cmd = 0x0C;
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request.arg = 0;
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DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg);
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sd_do_command(s->card, &request, response); |
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/* Auto CMD12 response goes to the upper Response register */
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s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | |
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(response[2] << 8) | response[3]; |
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} |
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|
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s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | |
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SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | |
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SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); |
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if (s->norintstsen & SDHC_NISEN_TRSCMP) {
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s->norintsts |= SDHC_NIS_TRSCMP; |
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} |
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sdhci_update_irq(s); |
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} |
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|
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/*
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* Programmed i/o data transfer
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*/
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|
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/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
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static void sdhci_read_block_from_card(SDHCIState *s) |
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{
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int index = 0; |
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|
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if ((s->trnmod & SDHC_TRNS_MULTI) &&
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(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
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return;
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} |
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|
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for (index = 0; index < (s->blksize & 0x0fff); index++) { |
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s->fifo_buffer[index] = sd_read_data(s->card); |
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} |
| 311 |
|
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/* New data now available for READ through Buffer Port Register */
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s->prnsts |= SDHC_DATA_AVAILABLE; |
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if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
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s->norintsts |= SDHC_NIS_RBUFRDY; |
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} |
| 317 |
|
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/* Clear DAT line active status if that was the last block */
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if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || |
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((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
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s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; |
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} |
| 323 |
|
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/* If stop at block gap request was set and it's not the last block of
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* data - generate Block Event interrupt */
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if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
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s->blkcnt != 1) {
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s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; |
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if (s->norintstsen & SDHC_EISEN_BLKGAP) {
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s->norintsts |= SDHC_EIS_BLKGAP; |
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} |
| 332 |
} |
| 333 |
|
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sdhci_update_irq(s); |
| 335 |
} |
| 336 |
|
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/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
|
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static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) |
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{
|
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uint32_t value = 0;
|
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int i;
|
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|
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/* first check that a valid data exists in host controller input buffer */
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if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { |
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ERRPRINT("Trying to read from empty buffer\n");
|
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return 0; |
| 347 |
} |
| 348 |
|
| 349 |
for (i = 0; i < size; i++) { |
| 350 |
value |= s->fifo_buffer[s->data_count] << i * 8;
|
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s->data_count++; |
| 352 |
/* check if we've read all valid data (blksize bytes) from buffer */
|
| 353 |
if ((s->data_count) >= (s->blksize & 0x0fff)) { |
| 354 |
DPRINT_L2("All %u bytes of data have been read from input buffer\n",
|
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s->data_count); |
| 356 |
s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
|
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s->data_count = 0; /* next buff read must start at position [0] */ |
| 358 |
|
| 359 |
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
|
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s->blkcnt--; |
| 361 |
} |
| 362 |
|
| 363 |
/* if that was the last block of data */
|
| 364 |
if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || |
| 365 |
((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
|
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/* stop at gap request */
|
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(s->stopped_state == sdhc_gap_read && |
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!(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
|
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SDHCI_GET_CLASS(s)->end_data_transfer(s); |
| 370 |
} else { /* if there are more data, read next block from card */ |
| 371 |
SDHCI_GET_CLASS(s)->read_block_from_card(s); |
| 372 |
} |
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break;
|
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} |
| 375 |
} |
| 376 |
|
| 377 |
return value;
|
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} |
| 379 |
|
| 380 |
/* Write data from host controller FIFO to card */
|
| 381 |
static void sdhci_write_block_to_card(SDHCIState *s) |
| 382 |
{
|
| 383 |
int index = 0; |
| 384 |
|
| 385 |
if (s->prnsts & SDHC_SPACE_AVAILABLE) {
|
| 386 |
if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
|
| 387 |
s->norintsts |= SDHC_NIS_WBUFRDY; |
| 388 |
} |
| 389 |
sdhci_update_irq(s); |
| 390 |
return;
|
| 391 |
} |
| 392 |
|
| 393 |
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
|
| 394 |
if (s->blkcnt == 0) { |
| 395 |
return;
|
| 396 |
} else {
|
| 397 |
s->blkcnt--; |
| 398 |
} |
| 399 |
} |
| 400 |
|
| 401 |
for (index = 0; index < (s->blksize & 0x0fff); index++) { |
| 402 |
sd_write_data(s->card, s->fifo_buffer[index]); |
| 403 |
} |
| 404 |
|
| 405 |
/* Next data can be written through BUFFER DATORT register */
|
| 406 |
s->prnsts |= SDHC_SPACE_AVAILABLE; |
| 407 |
if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
|
| 408 |
s->norintsts |= SDHC_NIS_WBUFRDY; |
| 409 |
} |
| 410 |
|
| 411 |
/* Finish transfer if that was the last block of data */
|
| 412 |
if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || |
| 413 |
((s->trnmod & SDHC_TRNS_MULTI) && |
| 414 |
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
|
| 415 |
SDHCI_GET_CLASS(s)->end_data_transfer(s); |
| 416 |
} |
| 417 |
|
| 418 |
/* Generate Block Gap Event if requested and if not the last block */
|
| 419 |
if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
|
| 420 |
s->blkcnt > 0) {
|
| 421 |
s->prnsts &= ~SDHC_DOING_WRITE; |
| 422 |
if (s->norintstsen & SDHC_EISEN_BLKGAP) {
|
| 423 |
s->norintsts |= SDHC_EIS_BLKGAP; |
| 424 |
} |
| 425 |
SDHCI_GET_CLASS(s)->end_data_transfer(s); |
| 426 |
} |
| 427 |
|
| 428 |
sdhci_update_irq(s); |
| 429 |
} |
| 430 |
|
| 431 |
/* Write @size bytes of @value data to host controller @s Buffer Data Port
|
| 432 |
* register */
|
| 433 |
static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) |
| 434 |
{
|
| 435 |
unsigned i;
|
| 436 |
|
| 437 |
/* Check that there is free space left in a buffer */
|
| 438 |
if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
|
| 439 |
ERRPRINT("Can't write to data buffer: buffer full\n");
|
| 440 |
return;
|
| 441 |
} |
| 442 |
|
| 443 |
for (i = 0; i < size; i++) { |
| 444 |
s->fifo_buffer[s->data_count] = value & 0xFF;
|
| 445 |
s->data_count++; |
| 446 |
value >>= 8;
|
| 447 |
if (s->data_count >= (s->blksize & 0x0fff)) { |
| 448 |
DPRINT_L2("write buffer filled with %u bytes of data\n",
|
| 449 |
s->data_count); |
| 450 |
s->data_count = 0;
|
| 451 |
s->prnsts &= ~SDHC_SPACE_AVAILABLE; |
| 452 |
if (s->prnsts & SDHC_DOING_WRITE) {
|
| 453 |
SDHCI_GET_CLASS(s)->write_block_to_card(s); |
| 454 |
} |
| 455 |
} |
| 456 |
} |
| 457 |
} |
| 458 |
|
| 459 |
/*
|
| 460 |
* Single DMA data transfer
|
| 461 |
*/
|
| 462 |
|
| 463 |
/* Multi block SDMA transfer */
|
| 464 |
static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) |
| 465 |
{
|
| 466 |
bool page_aligned = false; |
| 467 |
unsigned int n, begin; |
| 468 |
const uint16_t block_size = s->blksize & 0x0fff; |
| 469 |
uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); |
| 470 |
uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); |
| 471 |
|
| 472 |
/* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
|
| 473 |
* possible stop at page boundary if initial address is not page aligned,
|
| 474 |
* allow them to work properly */
|
| 475 |
if ((s->sdmasysad % boundary_chk) == 0) { |
| 476 |
page_aligned = true;
|
| 477 |
} |
| 478 |
|
| 479 |
if (s->trnmod & SDHC_TRNS_READ) {
|
| 480 |
s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | |
| 481 |
SDHC_DAT_LINE_ACTIVE; |
| 482 |
while (s->blkcnt) {
|
| 483 |
if (s->data_count == 0) { |
| 484 |
for (n = 0; n < block_size; n++) { |
| 485 |
s->fifo_buffer[n] = sd_read_data(s->card); |
| 486 |
} |
| 487 |
} |
| 488 |
begin = s->data_count; |
| 489 |
if (((boundary_count + begin) < block_size) && page_aligned) {
|
| 490 |
s->data_count = boundary_count + begin; |
| 491 |
boundary_count = 0;
|
| 492 |
} else {
|
| 493 |
s->data_count = block_size; |
| 494 |
boundary_count -= block_size - begin; |
| 495 |
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
|
| 496 |
s->blkcnt--; |
| 497 |
} |
| 498 |
} |
| 499 |
dma_memory_write(&dma_context_memory, s->sdmasysad, |
| 500 |
&s->fifo_buffer[begin], s->data_count - begin); |
| 501 |
s->sdmasysad += s->data_count - begin; |
| 502 |
if (s->data_count == block_size) {
|
| 503 |
s->data_count = 0;
|
| 504 |
} |
| 505 |
if (page_aligned && boundary_count == 0) { |
| 506 |
break;
|
| 507 |
} |
| 508 |
} |
| 509 |
} else {
|
| 510 |
s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | |
| 511 |
SDHC_DAT_LINE_ACTIVE; |
| 512 |
while (s->blkcnt) {
|
| 513 |
begin = s->data_count; |
| 514 |
if (((boundary_count + begin) < block_size) && page_aligned) {
|
| 515 |
s->data_count = boundary_count + begin; |
| 516 |
boundary_count = 0;
|
| 517 |
} else {
|
| 518 |
s->data_count = block_size; |
| 519 |
boundary_count -= block_size - begin; |
| 520 |
} |
| 521 |
dma_memory_read(&dma_context_memory, s->sdmasysad, |
| 522 |
&s->fifo_buffer[begin], s->data_count); |
| 523 |
s->sdmasysad += s->data_count - begin; |
| 524 |
if (s->data_count == block_size) {
|
| 525 |
for (n = 0; n < block_size; n++) { |
| 526 |
sd_write_data(s->card, s->fifo_buffer[n]); |
| 527 |
} |
| 528 |
s->data_count = 0;
|
| 529 |
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
|
| 530 |
s->blkcnt--; |
| 531 |
} |
| 532 |
} |
| 533 |
if (page_aligned && boundary_count == 0) { |
| 534 |
break;
|
| 535 |
} |
| 536 |
} |
| 537 |
} |
| 538 |
|
| 539 |
if (s->blkcnt == 0) { |
| 540 |
SDHCI_GET_CLASS(s)->end_data_transfer(s); |
| 541 |
} else {
|
| 542 |
if (s->norintstsen & SDHC_NISEN_DMA) {
|
| 543 |
s->norintsts |= SDHC_NIS_DMA; |
| 544 |
} |
| 545 |
sdhci_update_irq(s); |
| 546 |
} |
| 547 |
} |
| 548 |
|
| 549 |
/* single block SDMA transfer */
|
| 550 |
|
| 551 |
static void sdhci_sdma_transfer_single_block(SDHCIState *s) |
| 552 |
{
|
| 553 |
int n;
|
| 554 |
uint32_t datacnt = s->blksize & 0x0fff;
|
| 555 |
|
| 556 |
if (s->trnmod & SDHC_TRNS_READ) {
|
| 557 |
for (n = 0; n < datacnt; n++) { |
| 558 |
s->fifo_buffer[n] = sd_read_data(s->card); |
| 559 |
} |
| 560 |
dma_memory_write(&dma_context_memory, s->sdmasysad, s->fifo_buffer, |
| 561 |
datacnt); |
| 562 |
} else {
|
| 563 |
dma_memory_read(&dma_context_memory, s->sdmasysad, s->fifo_buffer, |
| 564 |
datacnt); |
| 565 |
for (n = 0; n < datacnt; n++) { |
| 566 |
sd_write_data(s->card, s->fifo_buffer[n]); |
| 567 |
} |
| 568 |
} |
| 569 |
|
| 570 |
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
|
| 571 |
s->blkcnt--; |
| 572 |
} |
| 573 |
|
| 574 |
SDHCI_GET_CLASS(s)->end_data_transfer(s); |
| 575 |
} |
| 576 |
|
| 577 |
typedef struct ADMADescr { |
| 578 |
hwaddr addr; |
| 579 |
uint16_t length; |
| 580 |
uint8_t attr; |
| 581 |
uint8_t incr; |
| 582 |
} ADMADescr; |
| 583 |
|
| 584 |
static void get_adma_description(SDHCIState *s, ADMADescr *dscr) |
| 585 |
{
|
| 586 |
uint32_t adma1 = 0;
|
| 587 |
uint64_t adma2 = 0;
|
| 588 |
hwaddr entry_addr = (hwaddr)s->admasysaddr; |
| 589 |
switch (SDHC_DMA_TYPE(s->hostctl)) {
|
| 590 |
case SDHC_CTRL_ADMA2_32:
|
| 591 |
dma_memory_read(&dma_context_memory, entry_addr, (uint8_t *)&adma2, |
| 592 |
sizeof(adma2));
|
| 593 |
adma2 = le64_to_cpu(adma2); |
| 594 |
/* The spec does not specify endianness of descriptor table.
|
| 595 |
* We currently assume that it is LE.
|
| 596 |
*/
|
| 597 |
dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; |
| 598 |
dscr->length = (uint16_t)extract64(adma2, 16, 16); |
| 599 |
dscr->attr = (uint8_t)extract64(adma2, 0, 7); |
| 600 |
dscr->incr = 8;
|
| 601 |
break;
|
| 602 |
case SDHC_CTRL_ADMA1_32:
|
| 603 |
dma_memory_read(&dma_context_memory, entry_addr, (uint8_t *)&adma1, |
| 604 |
sizeof(adma1));
|
| 605 |
adma1 = le32_to_cpu(adma1); |
| 606 |
dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
|
| 607 |
dscr->attr = (uint8_t)extract32(adma1, 0, 7); |
| 608 |
dscr->incr = 4;
|
| 609 |
if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
|
| 610 |
dscr->length = (uint16_t)extract32(adma1, 12, 16); |
| 611 |
} else {
|
| 612 |
dscr->length = 4096;
|
| 613 |
} |
| 614 |
break;
|
| 615 |
case SDHC_CTRL_ADMA2_64:
|
| 616 |
dma_memory_read(&dma_context_memory, entry_addr, |
| 617 |
(uint8_t *)(&dscr->attr), 1);
|
| 618 |
dma_memory_read(&dma_context_memory, entry_addr + 2,
|
| 619 |
(uint8_t *)(&dscr->length), 2);
|
| 620 |
dscr->length = le16_to_cpu(dscr->length); |
| 621 |
dma_memory_read(&dma_context_memory, entry_addr + 4,
|
| 622 |
(uint8_t *)(&dscr->addr), 8);
|
| 623 |
dscr->attr = le64_to_cpu(dscr->attr); |
| 624 |
dscr->attr &= 0xfffffff8;
|
| 625 |
dscr->incr = 12;
|
| 626 |
break;
|
| 627 |
} |
| 628 |
} |
| 629 |
|
| 630 |
/* Advanced DMA data transfer */
|
| 631 |
|
| 632 |
static void sdhci_do_adma(SDHCIState *s) |
| 633 |
{
|
| 634 |
unsigned int n, begin, length; |
| 635 |
const uint16_t block_size = s->blksize & 0x0fff; |
| 636 |
ADMADescr dscr; |
| 637 |
int i;
|
| 638 |
|
| 639 |
for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { |
| 640 |
s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; |
| 641 |
|
| 642 |
get_adma_description(s, &dscr); |
| 643 |
DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", |
| 644 |
dscr.addr, dscr.length, dscr.attr); |
| 645 |
|
| 646 |
if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { |
| 647 |
/* Indicate that error occurred in ST_FDS state */
|
| 648 |
s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; |
| 649 |
s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; |
| 650 |
|
| 651 |
/* Generate ADMA error interrupt */
|
| 652 |
if (s->errintstsen & SDHC_EISEN_ADMAERR) {
|
| 653 |
s->errintsts |= SDHC_EIS_ADMAERR; |
| 654 |
s->norintsts |= SDHC_NIS_ERR; |
| 655 |
} |
| 656 |
|
| 657 |
sdhci_update_irq(s); |
| 658 |
return;
|
| 659 |
} |
| 660 |
|
| 661 |
length = dscr.length ? dscr.length : 65536;
|
| 662 |
|
| 663 |
switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
|
| 664 |
case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ |
| 665 |
|
| 666 |
if (s->trnmod & SDHC_TRNS_READ) {
|
| 667 |
while (length) {
|
| 668 |
if (s->data_count == 0) { |
| 669 |
for (n = 0; n < block_size; n++) { |
| 670 |
s->fifo_buffer[n] = sd_read_data(s->card); |
| 671 |
} |
| 672 |
} |
| 673 |
begin = s->data_count; |
| 674 |
if ((length + begin) < block_size) {
|
| 675 |
s->data_count = length + begin; |
| 676 |
length = 0;
|
| 677 |
} else {
|
| 678 |
s->data_count = block_size; |
| 679 |
length -= block_size - begin; |
| 680 |
} |
| 681 |
dma_memory_write(&dma_context_memory, dscr.addr, |
| 682 |
&s->fifo_buffer[begin], |
| 683 |
s->data_count - begin); |
| 684 |
dscr.addr += s->data_count - begin; |
| 685 |
if (s->data_count == block_size) {
|
| 686 |
s->data_count = 0;
|
| 687 |
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
|
| 688 |
s->blkcnt--; |
| 689 |
if (s->blkcnt == 0) { |
| 690 |
break;
|
| 691 |
} |
| 692 |
} |
| 693 |
} |
| 694 |
} |
| 695 |
} else {
|
| 696 |
while (length) {
|
| 697 |
begin = s->data_count; |
| 698 |
if ((length + begin) < block_size) {
|
| 699 |
s->data_count = length + begin; |
| 700 |
length = 0;
|
| 701 |
} else {
|
| 702 |
s->data_count = block_size; |
| 703 |
length -= block_size - begin; |
| 704 |
} |
| 705 |
dma_memory_read(&dma_context_memory, dscr.addr, |
| 706 |
&s->fifo_buffer[begin], s->data_count); |
| 707 |
dscr.addr += s->data_count - begin; |
| 708 |
if (s->data_count == block_size) {
|
| 709 |
for (n = 0; n < block_size; n++) { |
| 710 |
sd_write_data(s->card, s->fifo_buffer[n]); |
| 711 |
} |
| 712 |
s->data_count = 0;
|
| 713 |
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
|
| 714 |
s->blkcnt--; |
| 715 |
if (s->blkcnt == 0) { |
| 716 |
break;
|
| 717 |
} |
| 718 |
} |
| 719 |
} |
| 720 |
} |
| 721 |
} |
| 722 |
s->admasysaddr += dscr.incr; |
| 723 |
break;
|
| 724 |
case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ |
| 725 |
s->admasysaddr = dscr.addr; |
| 726 |
DPRINT_L1("ADMA link: admasysaddr=0x%lx\n", s->admasysaddr);
|
| 727 |
break;
|
| 728 |
default:
|
| 729 |
s->admasysaddr += dscr.incr; |
| 730 |
break;
|
| 731 |
} |
| 732 |
|
| 733 |
/* ADMA transfer terminates if blkcnt == 0 or by END attribute */
|
| 734 |
if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
|
| 735 |
(s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
|
| 736 |
DPRINT_L2("ADMA transfer completed\n");
|
| 737 |
if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
|
| 738 |
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && |
| 739 |
s->blkcnt != 0)) {
|
| 740 |
ERRPRINT("SD/MMC host ADMA length mismatch\n");
|
| 741 |
s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | |
| 742 |
SDHC_ADMAERR_STATE_ST_TFR; |
| 743 |
if (s->errintstsen & SDHC_EISEN_ADMAERR) {
|
| 744 |
ERRPRINT("Set ADMA error flag\n");
|
| 745 |
s->errintsts |= SDHC_EIS_ADMAERR; |
| 746 |
s->norintsts |= SDHC_NIS_ERR; |
| 747 |
} |
| 748 |
|
| 749 |
sdhci_update_irq(s); |
| 750 |
} |
| 751 |
SDHCI_GET_CLASS(s)->end_data_transfer(s); |
| 752 |
return;
|
| 753 |
} |
| 754 |
|
| 755 |
if (dscr.attr & SDHC_ADMA_ATTR_INT) {
|
| 756 |
DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr);
|
| 757 |
if (s->norintstsen & SDHC_NISEN_DMA) {
|
| 758 |
s->norintsts |= SDHC_NIS_DMA; |
| 759 |
} |
| 760 |
|
| 761 |
sdhci_update_irq(s); |
| 762 |
return;
|
| 763 |
} |
| 764 |
} |
| 765 |
|
| 766 |
/* we have unfinished business - reschedule to continue ADMA */
|
| 767 |
qemu_mod_timer(s->transfer_timer, |
| 768 |
qemu_get_clock_ns(vm_clock) + SDHC_TRANSFER_DELAY); |
| 769 |
} |
| 770 |
|
| 771 |
/* Perform data transfer according to controller configuration */
|
| 772 |
|
| 773 |
static void sdhci_data_transfer(SDHCIState *s) |
| 774 |
{
|
| 775 |
SDHCIClass *k = SDHCI_GET_CLASS(s); |
| 776 |
s->data_count = 0;
|
| 777 |
|
| 778 |
if (s->trnmod & SDHC_TRNS_DMA) {
|
| 779 |
switch (SDHC_DMA_TYPE(s->hostctl)) {
|
| 780 |
case SDHC_CTRL_SDMA:
|
| 781 |
if ((s->trnmod & SDHC_TRNS_MULTI) &&
|
| 782 |
(!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) {
|
| 783 |
break;
|
| 784 |
} |
| 785 |
|
| 786 |
if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { |
| 787 |
k->do_sdma_single(s); |
| 788 |
} else {
|
| 789 |
k->do_sdma_multi(s); |
| 790 |
} |
| 791 |
|
| 792 |
break;
|
| 793 |
case SDHC_CTRL_ADMA1_32:
|
| 794 |
if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
|
| 795 |
ERRPRINT("ADMA1 not supported\n");
|
| 796 |
break;
|
| 797 |
} |
| 798 |
|
| 799 |
k->do_adma(s); |
| 800 |
break;
|
| 801 |
case SDHC_CTRL_ADMA2_32:
|
| 802 |
if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
|
| 803 |
ERRPRINT("ADMA2 not supported\n");
|
| 804 |
break;
|
| 805 |
} |
| 806 |
|
| 807 |
k->do_adma(s); |
| 808 |
break;
|
| 809 |
case SDHC_CTRL_ADMA2_64:
|
| 810 |
if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
|
| 811 |
!(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
|
| 812 |
ERRPRINT("64 bit ADMA not supported\n");
|
| 813 |
break;
|
| 814 |
} |
| 815 |
|
| 816 |
k->do_adma(s); |
| 817 |
break;
|
| 818 |
default:
|
| 819 |
ERRPRINT("Unsupported DMA type\n");
|
| 820 |
break;
|
| 821 |
} |
| 822 |
} else {
|
| 823 |
if ((s->trnmod & SDHC_TRNS_READ) && sd_data_ready(s->card)) {
|
| 824 |
s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | |
| 825 |
SDHC_DAT_LINE_ACTIVE; |
| 826 |
SDHCI_GET_CLASS(s)->read_block_from_card(s); |
| 827 |
} else {
|
| 828 |
s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | |
| 829 |
SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; |
| 830 |
SDHCI_GET_CLASS(s)->write_block_to_card(s); |
| 831 |
} |
| 832 |
} |
| 833 |
} |
| 834 |
|
| 835 |
static bool sdhci_can_issue_command(SDHCIState *s) |
| 836 |
{
|
| 837 |
if (!SDHC_CLOCK_IS_ON(s->clkcon) || !(s->pwrcon & SDHC_POWER_ON) ||
|
| 838 |
(((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && |
| 839 |
((s->cmdreg & SDHC_CMD_DATA_PRESENT) || |
| 840 |
((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && |
| 841 |
!(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
|
| 842 |
return false; |
| 843 |
} |
| 844 |
|
| 845 |
return true; |
| 846 |
} |
| 847 |
|
| 848 |
/* The Buffer Data Port register must be accessed in sequential and
|
| 849 |
* continuous manner */
|
| 850 |
static inline bool |
| 851 |
sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
|
| 852 |
{
|
| 853 |
if ((s->data_count & 0x3) != byte_num) { |
| 854 |
ERRPRINT("Non-sequential access to Buffer Data Port register"
|
| 855 |
"is prohibited\n");
|
| 856 |
return false; |
| 857 |
} |
| 858 |
return true; |
| 859 |
} |
| 860 |
|
| 861 |
static uint32_t sdhci_read(SDHCIState *s, unsigned int offset, unsigned size) |
| 862 |
{
|
| 863 |
uint32_t ret = 0;
|
| 864 |
|
| 865 |
switch (offset & ~0x3) { |
| 866 |
case SDHC_SYSAD:
|
| 867 |
ret = s->sdmasysad; |
| 868 |
break;
|
| 869 |
case SDHC_BLKSIZE:
|
| 870 |
ret = s->blksize | (s->blkcnt << 16);
|
| 871 |
break;
|
| 872 |
case SDHC_ARGUMENT:
|
| 873 |
ret = s->argument; |
| 874 |
break;
|
| 875 |
case SDHC_TRNMOD:
|
| 876 |
ret = s->trnmod | (s->cmdreg << 16);
|
| 877 |
break;
|
| 878 |
case SDHC_RSPREG0 ... SDHC_RSPREG3:
|
| 879 |
ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; |
| 880 |
break;
|
| 881 |
case SDHC_BDATA:
|
| 882 |
if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
|
| 883 |
ret = SDHCI_GET_CLASS(s)->bdata_read(s, size); |
| 884 |
DPRINT_L2("read %ub: addr[0x%04x] -> %u\n", size, offset, ret);
|
| 885 |
return ret;
|
| 886 |
} |
| 887 |
break;
|
| 888 |
case SDHC_PRNSTS:
|
| 889 |
ret = s->prnsts; |
| 890 |
break;
|
| 891 |
case SDHC_HOSTCTL:
|
| 892 |
ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | |
| 893 |
(s->wakcon << 24);
|
| 894 |
break;
|
| 895 |
case SDHC_CLKCON:
|
| 896 |
ret = s->clkcon | (s->timeoutcon << 16);
|
| 897 |
break;
|
| 898 |
case SDHC_NORINTSTS:
|
| 899 |
ret = s->norintsts | (s->errintsts << 16);
|
| 900 |
break;
|
| 901 |
case SDHC_NORINTSTSEN:
|
| 902 |
ret = s->norintstsen | (s->errintstsen << 16);
|
| 903 |
break;
|
| 904 |
case SDHC_NORINTSIGEN:
|
| 905 |
ret = s->norintsigen | (s->errintsigen << 16);
|
| 906 |
break;
|
| 907 |
case SDHC_ACMD12ERRSTS:
|
| 908 |
ret = s->acmd12errsts; |
| 909 |
break;
|
| 910 |
case SDHC_CAPAREG:
|
| 911 |
ret = s->capareg; |
| 912 |
break;
|
| 913 |
case SDHC_MAXCURR:
|
| 914 |
ret = s->maxcurr; |
| 915 |
break;
|
| 916 |
case SDHC_ADMAERR:
|
| 917 |
ret = s->admaerr; |
| 918 |
break;
|
| 919 |
case SDHC_ADMASYSADDR:
|
| 920 |
ret = (uint32_t)s->admasysaddr; |
| 921 |
break;
|
| 922 |
case SDHC_ADMASYSADDR + 4: |
| 923 |
ret = (uint32_t)(s->admasysaddr >> 32);
|
| 924 |
break;
|
| 925 |
case SDHC_SLOT_INT_STATUS:
|
| 926 |
ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
|
| 927 |
break;
|
| 928 |
default:
|
| 929 |
ERRPRINT("bad %ub read: addr[0x%04x]\n", size, offset);
|
| 930 |
break;
|
| 931 |
} |
| 932 |
|
| 933 |
ret >>= (offset & 0x3) * 8; |
| 934 |
ret &= (1ULL << (size * 8)) - 1; |
| 935 |
DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, offset, ret, ret);
|
| 936 |
return ret;
|
| 937 |
} |
| 938 |
|
| 939 |
static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) |
| 940 |
{
|
| 941 |
if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
|
| 942 |
return;
|
| 943 |
} |
| 944 |
s->blkgap = value & SDHC_STOP_AT_GAP_REQ; |
| 945 |
|
| 946 |
if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
|
| 947 |
(s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
|
| 948 |
if (s->stopped_state == sdhc_gap_read) {
|
| 949 |
s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; |
| 950 |
SDHCI_GET_CLASS(s)->read_block_from_card(s); |
| 951 |
} else {
|
| 952 |
s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; |
| 953 |
SDHCI_GET_CLASS(s)->write_block_to_card(s); |
| 954 |
} |
| 955 |
s->stopped_state = sdhc_not_stopped; |
| 956 |
} else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { |
| 957 |
if (s->prnsts & SDHC_DOING_READ) {
|
| 958 |
s->stopped_state = sdhc_gap_read; |
| 959 |
} else if (s->prnsts & SDHC_DOING_WRITE) { |
| 960 |
s->stopped_state = sdhc_gap_write; |
| 961 |
} |
| 962 |
} |
| 963 |
} |
| 964 |
|
| 965 |
static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) |
| 966 |
{
|
| 967 |
switch (value) {
|
| 968 |
case SDHC_RESET_ALL:
|
| 969 |
DEVICE_GET_CLASS(s)->reset(DEVICE(s)); |
| 970 |
break;
|
| 971 |
case SDHC_RESET_CMD:
|
| 972 |
s->prnsts &= ~SDHC_CMD_INHIBIT; |
| 973 |
s->norintsts &= ~SDHC_NIS_CMDCMP; |
| 974 |
break;
|
| 975 |
case SDHC_RESET_DATA:
|
| 976 |
s->data_count = 0;
|
| 977 |
s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | |
| 978 |
SDHC_DOING_READ | SDHC_DOING_WRITE | |
| 979 |
SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); |
| 980 |
s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); |
| 981 |
s->stopped_state = sdhc_not_stopped; |
| 982 |
s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | |
| 983 |
SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); |
| 984 |
break;
|
| 985 |
} |
| 986 |
} |
| 987 |
|
| 988 |
static void |
| 989 |
sdhci_write(SDHCIState *s, unsigned int offset, uint32_t value, unsigned size) |
| 990 |
{
|
| 991 |
unsigned shift = 8 * (offset & 0x3); |
| 992 |
uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); |
| 993 |
value <<= shift; |
| 994 |
|
| 995 |
switch (offset & ~0x3) { |
| 996 |
case SDHC_SYSAD:
|
| 997 |
s->sdmasysad = (s->sdmasysad & mask) | value; |
| 998 |
MASKED_WRITE(s->sdmasysad, mask, value); |
| 999 |
/* Writing to last byte of sdmasysad might trigger transfer */
|
| 1000 |
if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && |
| 1001 |
s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
|
| 1002 |
SDHCI_GET_CLASS(s)->do_sdma_multi(s); |
| 1003 |
} |
| 1004 |
break;
|
| 1005 |
case SDHC_BLKSIZE:
|
| 1006 |
if (!TRANSFERRING_DATA(s->prnsts)) {
|
| 1007 |
MASKED_WRITE(s->blksize, mask, value); |
| 1008 |
MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); |
| 1009 |
} |
| 1010 |
break;
|
| 1011 |
case SDHC_ARGUMENT:
|
| 1012 |
MASKED_WRITE(s->argument, mask, value); |
| 1013 |
break;
|
| 1014 |
case SDHC_TRNMOD:
|
| 1015 |
/* DMA can be enabled only if it is supported as indicated by
|
| 1016 |
* capabilities register */
|
| 1017 |
if (!(s->capareg & SDHC_CAN_DO_DMA)) {
|
| 1018 |
value &= ~SDHC_TRNS_DMA; |
| 1019 |
} |
| 1020 |
MASKED_WRITE(s->trnmod, mask, value); |
| 1021 |
MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); |
| 1022 |
|
| 1023 |
/* Writing to the upper byte of CMDREG triggers SD command generation */
|
| 1024 |
if ((mask & 0xFF000000) || !SDHCI_GET_CLASS(s)->can_issue_command(s)) { |
| 1025 |
break;
|
| 1026 |
} |
| 1027 |
|
| 1028 |
SDHCI_GET_CLASS(s)->send_command(s); |
| 1029 |
break;
|
| 1030 |
case SDHC_BDATA:
|
| 1031 |
if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
|
| 1032 |
SDHCI_GET_CLASS(s)->bdata_write(s, value >> shift, size); |
| 1033 |
} |
| 1034 |
break;
|
| 1035 |
case SDHC_HOSTCTL:
|
| 1036 |
if (!(mask & 0xFF0000)) { |
| 1037 |
sdhci_blkgap_write(s, value >> 16);
|
| 1038 |
} |
| 1039 |
MASKED_WRITE(s->hostctl, mask, value); |
| 1040 |
MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); |
| 1041 |
MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); |
| 1042 |
if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || |
| 1043 |
!(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { |
| 1044 |
s->pwrcon &= ~SDHC_POWER_ON; |
| 1045 |
} |
| 1046 |
break;
|
| 1047 |
case SDHC_CLKCON:
|
| 1048 |
if (!(mask & 0xFF000000)) { |
| 1049 |
sdhci_reset_write(s, value >> 24);
|
| 1050 |
} |
| 1051 |
MASKED_WRITE(s->clkcon, mask, value); |
| 1052 |
MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); |
| 1053 |
if (s->clkcon & SDHC_CLOCK_INT_EN) {
|
| 1054 |
s->clkcon |= SDHC_CLOCK_INT_STABLE; |
| 1055 |
} else {
|
| 1056 |
s->clkcon &= ~SDHC_CLOCK_INT_STABLE; |
| 1057 |
} |
| 1058 |
break;
|
| 1059 |
case SDHC_NORINTSTS:
|
| 1060 |
if (s->norintstsen & SDHC_NISEN_CARDINT) {
|
| 1061 |
value &= ~SDHC_NIS_CARDINT; |
| 1062 |
} |
| 1063 |
s->norintsts &= mask | ~value; |
| 1064 |
s->errintsts &= (mask >> 16) | ~(value >> 16); |
| 1065 |
if (s->errintsts) {
|
| 1066 |
s->norintsts |= SDHC_NIS_ERR; |
| 1067 |
} else {
|
| 1068 |
s->norintsts &= ~SDHC_NIS_ERR; |
| 1069 |
} |
| 1070 |
sdhci_update_irq(s); |
| 1071 |
break;
|
| 1072 |
case SDHC_NORINTSTSEN:
|
| 1073 |
MASKED_WRITE(s->norintstsen, mask, value); |
| 1074 |
MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); |
| 1075 |
s->norintsts &= s->norintstsen; |
| 1076 |
s->errintsts &= s->errintstsen; |
| 1077 |
if (s->errintsts) {
|
| 1078 |
s->norintsts |= SDHC_NIS_ERR; |
| 1079 |
} else {
|
| 1080 |
s->norintsts &= ~SDHC_NIS_ERR; |
| 1081 |
} |
| 1082 |
sdhci_update_irq(s); |
| 1083 |
break;
|
| 1084 |
case SDHC_NORINTSIGEN:
|
| 1085 |
MASKED_WRITE(s->norintsigen, mask, value); |
| 1086 |
MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); |
| 1087 |
sdhci_update_irq(s); |
| 1088 |
break;
|
| 1089 |
case SDHC_ADMAERR:
|
| 1090 |
MASKED_WRITE(s->admaerr, mask, value); |
| 1091 |
break;
|
| 1092 |
case SDHC_ADMASYSADDR:
|
| 1093 |
s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
|
| 1094 |
(uint64_t)mask)) | (uint64_t)value; |
| 1095 |
break;
|
| 1096 |
case SDHC_ADMASYSADDR + 4: |
| 1097 |
s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
|
| 1098 |
((uint64_t)mask << 32))) | ((uint64_t)value << 32); |
| 1099 |
break;
|
| 1100 |
case SDHC_FEAER:
|
| 1101 |
s->acmd12errsts |= value; |
| 1102 |
s->errintsts |= (value >> 16) & s->errintstsen;
|
| 1103 |
if (s->acmd12errsts) {
|
| 1104 |
s->errintsts |= SDHC_EIS_CMD12ERR; |
| 1105 |
} |
| 1106 |
if (s->errintsts) {
|
| 1107 |
s->norintsts |= SDHC_NIS_ERR; |
| 1108 |
} |
| 1109 |
sdhci_update_irq(s); |
| 1110 |
break;
|
| 1111 |
default:
|
| 1112 |
ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
|
| 1113 |
size, offset, value >> shift, value >> shift); |
| 1114 |
break;
|
| 1115 |
} |
| 1116 |
DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
|
| 1117 |
size, offset, value >> shift, value >> shift); |
| 1118 |
} |
| 1119 |
|
| 1120 |
static uint64_t
|
| 1121 |
sdhci_readfn(void *opaque, hwaddr offset, unsigned size) |
| 1122 |
{
|
| 1123 |
SDHCIState *s = (SDHCIState *)opaque; |
| 1124 |
|
| 1125 |
return SDHCI_GET_CLASS(s)->mem_read(s, offset, size);
|
| 1126 |
} |
| 1127 |
|
| 1128 |
static void |
| 1129 |
sdhci_writefn(void *opaque, hwaddr off, uint64_t val, unsigned sz) |
| 1130 |
{
|
| 1131 |
SDHCIState *s = (SDHCIState *)opaque; |
| 1132 |
|
| 1133 |
SDHCI_GET_CLASS(s)->mem_write(s, off, val, sz); |
| 1134 |
} |
| 1135 |
|
| 1136 |
static const MemoryRegionOps sdhci_mmio_ops = { |
| 1137 |
.read = sdhci_readfn, |
| 1138 |
.write = sdhci_writefn, |
| 1139 |
.valid = {
|
| 1140 |
.min_access_size = 1,
|
| 1141 |
.max_access_size = 4,
|
| 1142 |
.unaligned = false
|
| 1143 |
}, |
| 1144 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 1145 |
}; |
| 1146 |
|
| 1147 |
static inline unsigned int sdhci_get_fifolen(SDHCIState *s) |
| 1148 |
{
|
| 1149 |
switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) {
|
| 1150 |
case 0: |
| 1151 |
return 512; |
| 1152 |
case 1: |
| 1153 |
return 1024; |
| 1154 |
case 2: |
| 1155 |
return 2048; |
| 1156 |
default:
|
| 1157 |
hw_error("SDHC: unsupported value for maximum block size\n");
|
| 1158 |
return 0; |
| 1159 |
} |
| 1160 |
} |
| 1161 |
|
| 1162 |
static void sdhci_initfn(Object *obj) |
| 1163 |
{
|
| 1164 |
SDHCIState *s = SDHCI(obj); |
| 1165 |
DriveInfo *di; |
| 1166 |
|
| 1167 |
di = drive_get_next(IF_SD); |
| 1168 |
s->card = sd_init(di ? di->bdrv : NULL, 0); |
| 1169 |
s->eject_cb = qemu_allocate_irqs(sdhci_insert_eject_cb, s, 1)[0]; |
| 1170 |
s->ro_cb = qemu_allocate_irqs(sdhci_card_readonly_cb, s, 1)[0]; |
| 1171 |
sd_set_cb(s->card, s->ro_cb, s->eject_cb); |
| 1172 |
|
| 1173 |
s->insert_timer = qemu_new_timer_ns(vm_clock, sdhci_raise_insertion_irq, s); |
| 1174 |
s->transfer_timer = qemu_new_timer_ns(vm_clock, sdhci_do_data_transfer, s); |
| 1175 |
} |
| 1176 |
|
| 1177 |
static void sdhci_uninitfn(Object *obj) |
| 1178 |
{
|
| 1179 |
SDHCIState *s = SDHCI(obj); |
| 1180 |
|
| 1181 |
qemu_del_timer(s->insert_timer); |
| 1182 |
qemu_free_timer(s->insert_timer); |
| 1183 |
qemu_del_timer(s->transfer_timer); |
| 1184 |
qemu_free_timer(s->transfer_timer); |
| 1185 |
qemu_free_irqs(&s->eject_cb); |
| 1186 |
qemu_free_irqs(&s->ro_cb); |
| 1187 |
|
| 1188 |
if (s->fifo_buffer) {
|
| 1189 |
g_free(s->fifo_buffer); |
| 1190 |
s->fifo_buffer = NULL;
|
| 1191 |
} |
| 1192 |
} |
| 1193 |
|
| 1194 |
const VMStateDescription sdhci_vmstate = {
|
| 1195 |
.name = "sdhci",
|
| 1196 |
.version_id = 1,
|
| 1197 |
.minimum_version_id = 1,
|
| 1198 |
.fields = (VMStateField[]) {
|
| 1199 |
VMSTATE_UINT32(sdmasysad, SDHCIState), |
| 1200 |
VMSTATE_UINT16(blksize, SDHCIState), |
| 1201 |
VMSTATE_UINT16(blkcnt, SDHCIState), |
| 1202 |
VMSTATE_UINT32(argument, SDHCIState), |
| 1203 |
VMSTATE_UINT16(trnmod, SDHCIState), |
| 1204 |
VMSTATE_UINT16(cmdreg, SDHCIState), |
| 1205 |
VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
|
| 1206 |
VMSTATE_UINT32(prnsts, SDHCIState), |
| 1207 |
VMSTATE_UINT8(hostctl, SDHCIState), |
| 1208 |
VMSTATE_UINT8(pwrcon, SDHCIState), |
| 1209 |
VMSTATE_UINT8(blkgap, SDHCIState), |
| 1210 |
VMSTATE_UINT8(wakcon, SDHCIState), |
| 1211 |
VMSTATE_UINT16(clkcon, SDHCIState), |
| 1212 |
VMSTATE_UINT8(timeoutcon, SDHCIState), |
| 1213 |
VMSTATE_UINT8(admaerr, SDHCIState), |
| 1214 |
VMSTATE_UINT16(norintsts, SDHCIState), |
| 1215 |
VMSTATE_UINT16(errintsts, SDHCIState), |
| 1216 |
VMSTATE_UINT16(norintstsen, SDHCIState), |
| 1217 |
VMSTATE_UINT16(errintstsen, SDHCIState), |
| 1218 |
VMSTATE_UINT16(norintsigen, SDHCIState), |
| 1219 |
VMSTATE_UINT16(errintsigen, SDHCIState), |
| 1220 |
VMSTATE_UINT16(acmd12errsts, SDHCIState), |
| 1221 |
VMSTATE_UINT16(data_count, SDHCIState), |
| 1222 |
VMSTATE_UINT64(admasysaddr, SDHCIState), |
| 1223 |
VMSTATE_UINT8(stopped_state, SDHCIState), |
| 1224 |
VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz), |
| 1225 |
VMSTATE_TIMER(insert_timer, SDHCIState), |
| 1226 |
VMSTATE_TIMER(transfer_timer, SDHCIState), |
| 1227 |
VMSTATE_END_OF_LIST() |
| 1228 |
} |
| 1229 |
}; |
| 1230 |
|
| 1231 |
/* Capabilities registers provide information on supported features of this
|
| 1232 |
* specific host controller implementation */
|
| 1233 |
static Property sdhci_properties[] = {
|
| 1234 |
DEFINE_PROP_HEX32("capareg", SDHCIState, capareg,
|
| 1235 |
SDHC_CAPAB_REG_DEFAULT), |
| 1236 |
DEFINE_PROP_HEX32("maxcurr", SDHCIState, maxcurr, 0), |
| 1237 |
DEFINE_PROP_END_OF_LIST(), |
| 1238 |
}; |
| 1239 |
|
| 1240 |
static void sdhci_realize(DeviceState *dev, Error ** errp) |
| 1241 |
{
|
| 1242 |
SDHCIState *s = SDHCI(dev); |
| 1243 |
SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 1244 |
|
| 1245 |
s->buf_maxsz = sdhci_get_fifolen(s); |
| 1246 |
s->fifo_buffer = g_malloc0(s->buf_maxsz); |
| 1247 |
sysbus_init_irq(sbd, &s->irq); |
| 1248 |
memory_region_init_io(&s->iomem, &sdhci_mmio_ops, s, "sdhci",
|
| 1249 |
SDHC_REGISTERS_MAP_SIZE); |
| 1250 |
sysbus_init_mmio(sbd, &s->iomem); |
| 1251 |
} |
| 1252 |
|
| 1253 |
static void sdhci_generic_reset(DeviceState *ds) |
| 1254 |
{
|
| 1255 |
SDHCIState *s = SDHCI(ds); |
| 1256 |
SDHCI_GET_CLASS(s)->reset(s); |
| 1257 |
} |
| 1258 |
|
| 1259 |
static void sdhci_class_init(ObjectClass *klass, void *data) |
| 1260 |
{
|
| 1261 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 1262 |
SDHCIClass *k = SDHCI_CLASS(klass); |
| 1263 |
|
| 1264 |
dc->vmsd = &sdhci_vmstate; |
| 1265 |
dc->props = sdhci_properties; |
| 1266 |
dc->reset = sdhci_generic_reset; |
| 1267 |
dc->realize = sdhci_realize; |
| 1268 |
|
| 1269 |
k->reset = sdhci_reset; |
| 1270 |
k->mem_read = sdhci_read; |
| 1271 |
k->mem_write = sdhci_write; |
| 1272 |
k->send_command = sdhci_send_command; |
| 1273 |
k->can_issue_command = sdhci_can_issue_command; |
| 1274 |
k->data_transfer = sdhci_data_transfer; |
| 1275 |
k->end_data_transfer = sdhci_end_transfer; |
| 1276 |
k->do_sdma_single = sdhci_sdma_transfer_single_block; |
| 1277 |
k->do_sdma_multi = sdhci_sdma_transfer_multi_blocks; |
| 1278 |
k->do_adma = sdhci_do_adma; |
| 1279 |
k->read_block_from_card = sdhci_read_block_from_card; |
| 1280 |
k->write_block_to_card = sdhci_write_block_to_card; |
| 1281 |
k->bdata_read = sdhci_read_dataport; |
| 1282 |
k->bdata_write = sdhci_write_dataport; |
| 1283 |
} |
| 1284 |
|
| 1285 |
static const TypeInfo sdhci_type_info = { |
| 1286 |
.name = TYPE_SDHCI, |
| 1287 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 1288 |
.instance_size = sizeof(SDHCIState),
|
| 1289 |
.instance_init = sdhci_initfn, |
| 1290 |
.instance_finalize = sdhci_uninitfn, |
| 1291 |
.class_init = sdhci_class_init, |
| 1292 |
.class_size = sizeof(SDHCIClass)
|
| 1293 |
}; |
| 1294 |
|
| 1295 |
static void sdhci_register_types(void) |
| 1296 |
{
|
| 1297 |
type_register_static(&sdhci_type_info); |
| 1298 |
} |
| 1299 |
|
| 1300 |
type_init(sdhci_register_types) |