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/* alpha-dis.c -- Disassemble Alpha AXP instructions
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   Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
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   Contributed by Richard Henderson <rth@tamu.edu>,
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   patterned after the PPC opcode handling written by Ian Lance Taylor.
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING.  If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA.  */
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#include <stdio.h>
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#include "dis-asm.h"
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/* The opcode table is an array of struct alpha_opcode.  */
27

    
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struct alpha_opcode
29
{
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  /* The opcode name.  */
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  const char *name;
32

    
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  /* The opcode itself.  Those bits which will be filled in with
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     operands are zeroes.  */
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  unsigned opcode;
36

    
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  /* The opcode mask.  This is used by the disassembler.  This is a
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     mask containing ones indicating those bits which must match the
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     opcode field, and zeroes indicating those bits which need not
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     match (and are presumably filled in by operands).  */
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  unsigned mask;
42

    
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  /* One bit flags for the opcode.  These are primarily used to
44
     indicate specific processors and environments support the
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     instructions.  The defined values are listed below. */
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  unsigned flags;
47

    
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  /* An array of operand codes.  Each code is an index into the
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     operand table.  They appear in the order which the operands must
50
     appear in assembly code, and are terminated by a zero.  */
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  unsigned char operands[4];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
55
   in the order in which the disassembler should consider
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   instructions.  */
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extern const struct alpha_opcode alpha_opcodes[];
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extern const unsigned alpha_num_opcodes;
59

    
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/* Values defined for the flags field of a struct alpha_opcode.  */
61

    
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/* CPU Availability */
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#define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */
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#define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */
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#define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */
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#define AXP_OPCODE_EV6   0x0008  /* EV6 specific PALcode insns.  */
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#define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */
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#define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */
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#define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */
70

    
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#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
72

    
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/* A macro to extract the major opcode from an instruction.  */
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#define AXP_OP(i)        (((i) >> 26) & 0x3F)
75

    
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/* The total number of major opcodes. */
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#define AXP_NOPS        0x40
78

    
79
 
80
/* The operands table is an array of struct alpha_operand.  */
81

    
82
struct alpha_operand
83
{
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  /* The number of bits in the operand.  */
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  unsigned int bits : 5;
86

    
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  /* How far the operand is left shifted in the instruction.  */
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  unsigned int shift : 5;
89

    
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  /* The default relocation type for this operand.  */
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  signed int default_reloc : 16;
92

    
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  /* One bit syntax flags.  */
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  unsigned int flags : 16;
95

    
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  /* Insertion function.  This is used by the assembler.  To insert an
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     operand value into an instruction, check this field.
98

99
     If it is NULL, execute
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         i |= (op & ((1 << o->bits) - 1)) << o->shift;
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     (i is the instruction which we are filling in, o is a pointer to
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     this structure, and op is the opcode value; this assumes twos
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     complement arithmetic).
104

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     If this field is not NULL, then simply call it with the
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     instruction and the operand value.  It will return the new value
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     of the instruction.  If the ERRMSG argument is not NULL, then if
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     the operand value is illegal, *ERRMSG will be set to a warning
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     string (the operand will be inserted in any case).  If the
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     operand value is legal, *ERRMSG will be unchanged (most operands
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     can accept any value).  */
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  unsigned (*insert) PARAMS ((unsigned instruction, int op,
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                              const char **errmsg));
114

    
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  /* Extraction function.  This is used by the disassembler.  To
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     extract this operand type from an instruction, check this field.
117

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     If it is NULL, compute
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         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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         if ((o->flags & AXP_OPERAND_SIGNED) != 0
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             && (op & (1 << (o->bits - 1))) != 0)
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           op -= 1 << o->bits;
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     (i is the instruction, o is a pointer to this structure, and op
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     is the result; this assumes twos complement arithmetic).
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     If this field is not NULL, then simply call it with the
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     instruction value.  It will return the value of the operand.  If
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     the INVALID argument is not NULL, *INVALID will be set to
129
     non-zero if this operand type can not actually be extracted from
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     this operand (i.e., the instruction does not match).  If the
131
     operand is valid, *INVALID will not be changed.  */
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  int (*extract) PARAMS ((unsigned instruction, int *invalid));
133
};
134

    
135
/* Elements in the table are retrieved by indexing with values from
136
   the operands field of the alpha_opcodes table.  */
137

    
138
extern const struct alpha_operand alpha_operands[];
139
extern const unsigned alpha_num_operands;
140

    
141
/* Values defined for the flags field of a struct alpha_operand.  */
142

    
143
/* Mask for selecting the type for typecheck purposes */
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#define AXP_OPERAND_TYPECHECK_MASK                                        \
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  (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |                \
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   AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED |         \
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   AXP_OPERAND_UNSIGNED)
148

    
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/* This operand does not actually exist in the assembler input.  This
150
   is used to support extended mnemonics, for which two operands fields
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   are identical.  The assembler should call the insert function with
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   any op value.  The disassembler should call the extract function,
153
   ignore the return value, and check the value placed in the invalid
154
   argument.  */
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#define AXP_OPERAND_FAKE        01
156

    
157
/* The operand should be wrapped in parentheses rather than separated
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   from the previous by a comma.  This is used for the load and store
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   instructions which want their operands to look like "Ra,disp(Rb)".  */
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#define AXP_OPERAND_PARENS        02
161

    
162
/* Used in combination with PARENS, this supresses the supression of
163
   the comma.  This is used for "jmp Ra,(Rb),hint".  */
164
#define AXP_OPERAND_COMMA        04
165

    
166
/* This operand names an integer register.  */
167
#define AXP_OPERAND_IR                010
168

    
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/* This operand names a floating point register.  */
170
#define AXP_OPERAND_FPR                020
171

    
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/* This operand is a relative branch displacement.  The disassembler
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   prints these symbolically if possible.  */
174
#define AXP_OPERAND_RELATIVE        040
175

    
176
/* This operand takes signed values.  */
177
#define AXP_OPERAND_SIGNED        0100
178

    
179
/* This operand takes unsigned values.  This exists primarily so that
180
   a flags value of 0 can be treated as end-of-arguments.  */
181
#define AXP_OPERAND_UNSIGNED        0200
182

    
183
/* Supress overflow detection on this field.  This is used for hints. */
184
#define AXP_OPERAND_NOOVERFLOW        0400
185

    
186
/* Mask for optional argument default value.  */
187
#define AXP_OPERAND_OPTIONAL_MASK 07000
188

    
189
/* This operand defaults to zero.  This is used for jump hints.  */
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#define AXP_OPERAND_DEFAULT_ZERO 01000
191

    
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/* This operand should default to the first (real) operand and is used
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   in conjunction with AXP_OPERAND_OPTIONAL.  This allows
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   "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
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   it, but it's what DEC does.  */
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#define AXP_OPERAND_DEFAULT_FIRST 02000
197

    
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/* Similarly, this operand should default to the second (real) operand.
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   This allows "negl $0" instead of "negl $0,$0".  */
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#define AXP_OPERAND_DEFAULT_SECOND 04000
201

    
202
 
203
/* Register common names */
204

    
205
#define AXP_REG_V0        0
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#define AXP_REG_T0        1
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#define AXP_REG_T1        2
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#define AXP_REG_T2        3
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#define AXP_REG_T3        4
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#define AXP_REG_T4        5
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#define AXP_REG_T5        6
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#define AXP_REG_T6        7
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#define AXP_REG_T7        8
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#define AXP_REG_S0        9
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#define AXP_REG_S1        10
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#define AXP_REG_S2        11
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#define AXP_REG_S3        12
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#define AXP_REG_S4        13
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#define AXP_REG_S5        14
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#define AXP_REG_FP        15
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#define AXP_REG_A0        16
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#define AXP_REG_A1        17
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#define AXP_REG_A2        18
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#define AXP_REG_A3        19
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#define AXP_REG_A4        20
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#define AXP_REG_A5        21
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#define AXP_REG_T8        22
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#define AXP_REG_T9        23
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#define AXP_REG_T10        24
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#define AXP_REG_T11        25
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#define AXP_REG_RA        26
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#define AXP_REG_PV        27
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#define AXP_REG_T12        27
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#define AXP_REG_AT        28
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#define AXP_REG_GP        29
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#define AXP_REG_SP        30
237
#define AXP_REG_ZERO        31
238

    
239
#define bfd_mach_alpha_ev4  0x10
240
#define bfd_mach_alpha_ev5  0x20
241
#define bfd_mach_alpha_ev6  0x30
242

    
243
enum bfd_reloc_code_real {
244
    BFD_RELOC_23_PCREL_S2,
245
    BFD_RELOC_ALPHA_HINT
246
};
247

    
248
/* This file holds the Alpha AXP opcode table.  The opcode table includes
249
   almost all of the extended instruction mnemonics.  This permits the
250
   disassembler to use them, and simplifies the assembler logic, at the
251
   cost of increasing the table size.  The table is strictly constant
252
   data, so the compiler should be able to put it in the text segment.
253

254
   This file also holds the operand table.  All knowledge about inserting
255
   and extracting operands from instructions is kept in this file.
256

257
   The information for the base instruction set was compiled from the
258
   _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
259
   version 2.
260

261
   The information for the post-ev5 architecture extensions BWX, CIX and
262
   MAX came from version 3 of this same document, which is also available
263
   on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
264
   /literature/alphahb2.pdf
265

266
   The information for the EV4 PALcode instructions was compiled from
267
   _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
268
   Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
269
   revision dated June 1994.
270

271
   The information for the EV5 PALcode instructions was compiled from
272
   _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
273
   Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */
274
 
275
/* Local insertion and extraction functions */
276

    
277
static unsigned insert_rba PARAMS((unsigned, int, const char **));
278
static unsigned insert_rca PARAMS((unsigned, int, const char **));
279
static unsigned insert_za PARAMS((unsigned, int, const char **));
280
static unsigned insert_zb PARAMS((unsigned, int, const char **));
281
static unsigned insert_zc PARAMS((unsigned, int, const char **));
282
static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
283
static unsigned insert_jhint PARAMS((unsigned, int, const char **));
284
static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
285

    
286
static int extract_rba PARAMS((unsigned, int *));
287
static int extract_rca PARAMS((unsigned, int *));
288
static int extract_za PARAMS((unsigned, int *));
289
static int extract_zb PARAMS((unsigned, int *));
290
static int extract_zc PARAMS((unsigned, int *));
291
static int extract_bdisp PARAMS((unsigned, int *));
292
static int extract_jhint PARAMS((unsigned, int *));
293
static int extract_ev6hwjhint PARAMS((unsigned, int *));
294

    
295
 
296
/* The operands table  */
297

    
298
const struct alpha_operand alpha_operands[] =
299
{
300
  /* The fields are bits, shift, insert, extract, flags */
301
  /* The zero index is used to indicate end-of-list */
302
#define UNUSED                0
303
  { 0, 0, 0, 0, 0, 0 },
304

    
305
  /* The plain integer register fields */
306
#define RA                (UNUSED + 1)
307
  { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
308
#define RB                (RA + 1)
309
  { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
310
#define RC                (RB + 1)
311
  { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
312

    
313
  /* The plain fp register fields */
314
#define FA                (RC + 1)
315
  { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
316
#define FB                (FA + 1)
317
  { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
318
#define FC                (FB + 1)
319
  { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
320

    
321
  /* The integer registers when they are ZERO */
322
#define ZA                (FC + 1)
323
  { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
324
#define ZB                (ZA + 1)
325
  { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
326
#define ZC                (ZB + 1)
327
  { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
328

    
329
  /* The RB field when it needs parentheses */
330
#define PRB                (ZC + 1)
331
  { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
332

    
333
  /* The RB field when it needs parentheses _and_ a preceding comma */
334
#define CPRB                (PRB + 1)
335
  { 5, 16, 0,
336
    AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
337

    
338
  /* The RB field when it must be the same as the RA field */
339
#define RBA                (CPRB + 1)
340
  { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
341

    
342
  /* The RC field when it must be the same as the RB field */
343
#define RCA                (RBA + 1)
344
  { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
345

    
346
  /* The RC field when it can *default* to RA */
347
#define DRC1                (RCA + 1)
348
  { 5, 0, 0,
349
    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
350

    
351
  /* The RC field when it can *default* to RB */
352
#define DRC2                (DRC1 + 1)
353
  { 5, 0, 0,
354
    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
355

    
356
  /* The FC field when it can *default* to RA */
357
#define DFC1                (DRC2 + 1)
358
  { 5, 0, 0,
359
    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
360

    
361
  /* The FC field when it can *default* to RB */
362
#define DFC2                (DFC1 + 1)
363
  { 5, 0, 0,
364
    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
365

    
366
  /* The unsigned 8-bit literal of Operate format insns */
367
#define LIT                (DFC2 + 1)
368
  { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
369

    
370
  /* The signed 16-bit displacement of Memory format insns.  From here
371
     we can't tell what relocation should be used, so don't use a default. */
372
#define MDISP                (LIT + 1)
373
  { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
374

    
375
  /* The signed "23-bit" aligned displacement of Branch format insns */
376
#define BDISP                (MDISP + 1)
377
  { 21, 0, BFD_RELOC_23_PCREL_S2, 
378
    AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
379

    
380
  /* The 26-bit PALcode function */
381
#define PALFN                (BDISP + 1)
382
  { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
383

    
384
  /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
385
#define JMPHINT                (PALFN + 1)
386
  { 14, 0, BFD_RELOC_ALPHA_HINT,
387
    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
388
    insert_jhint, extract_jhint },
389

    
390
  /* The optional hint to RET/JSR_COROUTINE */
391
#define RETHINT                (JMPHINT + 1)
392
  { 14, 0, -RETHINT,
393
    AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
394

    
395
  /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
396
#define EV4HWDISP        (RETHINT + 1)
397
#define EV6HWDISP        (EV4HWDISP)
398
  { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
399

    
400
  /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
401
#define EV4HWINDEX        (EV4HWDISP + 1)
402
  { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
403

    
404
  /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
405
     that occur in DEC PALcode.  */
406
#define EV4EXTHWINDEX        (EV4HWINDEX + 1)
407
  { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
408

    
409
  /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
410
#define EV5HWDISP        (EV4EXTHWINDEX + 1)
411
  { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
412

    
413
  /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
414
#define EV5HWINDEX        (EV5HWDISP + 1)
415
  { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
416

    
417
  /* The 16-bit combined index/scoreboard mask for the ev6
418
     hw_m[ft]pr (pal19/pal1d) insns */
419
#define EV6HWINDEX        (EV5HWINDEX + 1)
420
  { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
421

    
422
  /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
423
#define EV6HWJMPHINT        (EV6HWINDEX+ 1)
424
  { 8, 0, -EV6HWJMPHINT,
425
    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
426
    insert_ev6hwjhint, extract_ev6hwjhint }
427
};
428

    
429
const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
430

    
431
/* The RB field when it is the same as the RA field in the same insn.
432
   This operand is marked fake.  The insertion function just copies
433
   the RA field into the RB field, and the extraction function just
434
   checks that the fields are the same. */
435

    
436
/*ARGSUSED*/
437
static unsigned
438
insert_rba(insn, value, errmsg)
439
     unsigned insn;
440
     int value ATTRIBUTE_UNUSED;
441
     const char **errmsg ATTRIBUTE_UNUSED;
442
{
443
  return insn | (((insn >> 21) & 0x1f) << 16);
444
}
445

    
446
static int
447
extract_rba(insn, invalid)
448
     unsigned insn;
449
     int *invalid;
450
{
451
  if (invalid != (int *) NULL
452
      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
453
    *invalid = 1;
454
  return 0;
455
}
456

    
457

    
458
/* The same for the RC field */
459

    
460
/*ARGSUSED*/
461
static unsigned
462
insert_rca(insn, value, errmsg)
463
     unsigned insn;
464
     int value ATTRIBUTE_UNUSED;
465
     const char **errmsg ATTRIBUTE_UNUSED;
466
{
467
  return insn | ((insn >> 21) & 0x1f);
468
}
469

    
470
static int
471
extract_rca(insn, invalid)
472
     unsigned insn;
473
     int *invalid;
474
{
475
  if (invalid != (int *) NULL
476
      && ((insn >> 21) & 0x1f) != (insn & 0x1f))
477
    *invalid = 1;
478
  return 0;
479
}
480

    
481

    
482
/* Fake arguments in which the registers must be set to ZERO */
483

    
484
/*ARGSUSED*/
485
static unsigned
486
insert_za(insn, value, errmsg)
487
     unsigned insn;
488
     int value ATTRIBUTE_UNUSED;
489
     const char **errmsg ATTRIBUTE_UNUSED;
490
{
491
  return insn | (31 << 21);
492
}
493

    
494
static int
495
extract_za(insn, invalid)
496
     unsigned insn;
497
     int *invalid;
498
{
499
  if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
500
    *invalid = 1;
501
  return 0;
502
}
503

    
504
/*ARGSUSED*/
505
static unsigned
506
insert_zb(insn, value, errmsg)
507
     unsigned insn;
508
     int value ATTRIBUTE_UNUSED;
509
     const char **errmsg ATTRIBUTE_UNUSED;
510
{
511
  return insn | (31 << 16);
512
}
513

    
514
static int
515
extract_zb(insn, invalid)
516
     unsigned insn;
517
     int *invalid;
518
{
519
  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
520
    *invalid = 1;
521
  return 0;
522
}
523

    
524
/*ARGSUSED*/
525
static unsigned
526
insert_zc(insn, value, errmsg)
527
     unsigned insn;
528
     int value ATTRIBUTE_UNUSED;
529
     const char **errmsg ATTRIBUTE_UNUSED;
530
{
531
  return insn | 31;
532
}
533

    
534
static int
535
extract_zc(insn, invalid)
536
     unsigned insn;
537
     int *invalid;
538
{
539
  if (invalid != (int *) NULL && (insn & 0x1f) != 31)
540
    *invalid = 1;
541
  return 0;
542
}
543

    
544

    
545
/* The displacement field of a Branch format insn.  */
546

    
547
static unsigned
548
insert_bdisp(insn, value, errmsg)
549
     unsigned insn;
550
     int value;
551
     const char **errmsg;
552
{
553
  if (errmsg != (const char **)NULL && (value & 3))
554
    *errmsg = _("branch operand unaligned");
555
  return insn | ((value / 4) & 0x1FFFFF);
556
}
557

    
558
/*ARGSUSED*/
559
static int
560
extract_bdisp(insn, invalid)
561
     unsigned insn;
562
     int *invalid ATTRIBUTE_UNUSED;
563
{
564
  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
565
}
566

    
567

    
568
/* The hint field of a JMP/JSR insn.  */
569

    
570
static unsigned
571
insert_jhint(insn, value, errmsg)
572
     unsigned insn;
573
     int value;
574
     const char **errmsg;
575
{
576
  if (errmsg != (const char **)NULL && (value & 3))
577
    *errmsg = _("jump hint unaligned");
578
  return insn | ((value / 4) & 0x3FFF);
579
}
580

    
581
/*ARGSUSED*/
582
static int
583
extract_jhint(insn, invalid)
584
     unsigned insn;
585
     int *invalid ATTRIBUTE_UNUSED;
586
{
587
  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
588
}
589

    
590
/* The hint field of an EV6 HW_JMP/JSR insn.  */
591

    
592
static unsigned
593
insert_ev6hwjhint(insn, value, errmsg)
594
     unsigned insn;
595
     int value;
596
     const char **errmsg;
597
{
598
  if (errmsg != (const char **)NULL && (value & 3))
599
    *errmsg = _("jump hint unaligned");
600
  return insn | ((value / 4) & 0x1FFF);
601
}
602

    
603
/*ARGSUSED*/
604
static int
605
extract_ev6hwjhint(insn, invalid)
606
     unsigned insn;
607
     int *invalid ATTRIBUTE_UNUSED;
608
{
609
  return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
610
}
611

    
612
 
613
/* Macros used to form opcodes */
614

    
615
/* The main opcode */
616
#define OP(x)                (((x) & 0x3F) << 26)
617
#define OP_MASK                0xFC000000
618

    
619
/* Branch format instructions */
620
#define BRA_(oo)        OP(oo)
621
#define BRA_MASK        OP_MASK
622
#define BRA(oo)                BRA_(oo), BRA_MASK
623

    
624
/* Floating point format instructions */
625
#define FP_(oo,fff)        (OP(oo) | (((fff) & 0x7FF) << 5))
626
#define FP_MASK                (OP_MASK | 0xFFE0)
627
#define FP(oo,fff)        FP_(oo,fff), FP_MASK
628

    
629
/* Memory format instructions */
630
#define MEM_(oo)        OP(oo)
631
#define MEM_MASK        OP_MASK
632
#define MEM(oo)                MEM_(oo), MEM_MASK
633

    
634
/* Memory/Func Code format instructions */
635
#define MFC_(oo,ffff)        (OP(oo) | ((ffff) & 0xFFFF))
636
#define MFC_MASK        (OP_MASK | 0xFFFF)
637
#define MFC(oo,ffff)        MFC_(oo,ffff), MFC_MASK
638

    
639
/* Memory/Branch format instructions */
640
#define MBR_(oo,h)        (OP(oo) | (((h) & 3) << 14))
641
#define MBR_MASK        (OP_MASK | 0xC000)
642
#define MBR(oo,h)        MBR_(oo,h), MBR_MASK
643

    
644
/* Operate format instructions.  The OPRL variant specifies a
645
   literal second argument. */
646
#define OPR_(oo,ff)        (OP(oo) | (((ff) & 0x7F) << 5))
647
#define OPRL_(oo,ff)        (OPR_((oo),(ff)) | 0x1000)
648
#define OPR_MASK        (OP_MASK | 0x1FE0)
649
#define OPR(oo,ff)        OPR_(oo,ff), OPR_MASK
650
#define OPRL(oo,ff)        OPRL_(oo,ff), OPR_MASK
651

    
652
/* Generic PALcode format instructions */
653
#define PCD_(oo)        OP(oo)
654
#define PCD_MASK        OP_MASK
655
#define PCD(oo)                PCD_(oo), PCD_MASK
656

    
657
/* Specific PALcode instructions */
658
#define SPCD_(oo,ffff)        (OP(oo) | ((ffff) & 0x3FFFFFF))
659
#define SPCD_MASK        0xFFFFFFFF
660
#define SPCD(oo,ffff)        SPCD_(oo,ffff), SPCD_MASK
661

    
662
/* Hardware memory (hw_{ld,st}) instructions */
663
#define EV4HWMEM_(oo,f)        (OP(oo) | (((f) & 0xF) << 12))
664
#define EV4HWMEM_MASK        (OP_MASK | 0xF000)
665
#define EV4HWMEM(oo,f)        EV4HWMEM_(oo,f), EV4HWMEM_MASK
666

    
667
#define EV5HWMEM_(oo,f)        (OP(oo) | (((f) & 0x3F) << 10))
668
#define EV5HWMEM_MASK        (OP_MASK | 0xF800)
669
#define EV5HWMEM(oo,f)        EV5HWMEM_(oo,f), EV5HWMEM_MASK
670

    
671
#define EV6HWMEM_(oo,f)        (OP(oo) | (((f) & 0xF) << 12))
672
#define EV6HWMEM_MASK        (OP_MASK | 0xF000)
673
#define EV6HWMEM(oo,f)        EV6HWMEM_(oo,f), EV6HWMEM_MASK
674

    
675
#define EV6HWMBR_(oo,h)        (OP(oo) | (((h) & 7) << 13))
676
#define EV6HWMBR_MASK        (OP_MASK | 0xE000)
677
#define EV6HWMBR(oo,h)        EV6HWMBR_(oo,h), EV6HWMBR_MASK
678

    
679
/* Abbreviations for instruction subsets.  */
680
#define BASE                        AXP_OPCODE_BASE
681
#define EV4                        AXP_OPCODE_EV4
682
#define EV5                        AXP_OPCODE_EV5
683
#define EV6                        AXP_OPCODE_EV6
684
#define BWX                        AXP_OPCODE_BWX
685
#define CIX                        AXP_OPCODE_CIX
686
#define MAX                        AXP_OPCODE_MAX
687

    
688
/* Common combinations of arguments */
689
#define ARG_NONE                { 0 }
690
#define ARG_BRA                        { RA, BDISP }
691
#define ARG_FBRA                { FA, BDISP }
692
#define ARG_FP                        { FA, FB, DFC1 }
693
#define ARG_FPZ1                { ZA, FB, DFC1 }
694
#define ARG_MEM                        { RA, MDISP, PRB }
695
#define ARG_FMEM                { FA, MDISP, PRB }
696
#define ARG_OPR                        { RA, RB, DRC1 }
697
#define ARG_OPRL                { RA, LIT, DRC1 }
698
#define ARG_OPRZ1                { ZA, RB, DRC1 }
699
#define ARG_OPRLZ1                { ZA, LIT, RC }
700
#define ARG_PCD                        { PALFN }
701
#define ARG_EV4HWMEM                { RA, EV4HWDISP, PRB }
702
#define ARG_EV4HWMPR                { RA, RBA, EV4HWINDEX }
703
#define ARG_EV5HWMEM                { RA, EV5HWDISP, PRB }
704
#define ARG_EV6HWMEM                { RA, EV6HWDISP, PRB }
705
 
706
/* The opcode table.
707

708
   The format of the opcode table is:
709

710
   NAME OPCODE MASK { OPERANDS }
711

712
   NAME                is the name of the instruction.
713

714
   OPCODE        is the instruction opcode.
715

716
   MASK                is the opcode mask; this is used to tell the disassembler
717
                    which bits in the actual opcode must match OPCODE.
718

719
   OPERANDS        is the list of operands.
720

721
   The preceding macros merge the text of the OPCODE and MASK fields.
722

723
   The disassembler reads the table in order and prints the first
724
   instruction which matches, so this table is sorted to put more
725
   specific instructions before more general instructions.
726

727
   Otherwise, it is sorted by major opcode and minor function code.
728

729
   There are three classes of not-really-instructions in this table:
730

731
   ALIAS        is another name for another instruction.  Some of
732
                these come from the Architecture Handbook, some
733
                come from the original gas opcode tables.  In all
734
                cases, the functionality of the opcode is unchanged.
735

736
   PSEUDO        a stylized code form endorsed by Chapter A.4 of the
737
                Architecture Handbook.
738

739
   EXTRA        a stylized code form found in the original gas tables.
740

741
   And two annotations:
742

743
   EV56 BUT        opcodes that are officially introduced as of the ev56,
744
                   but with defined results on previous implementations.
745

746
   EV56 UNA        opcodes that were introduced as of the ev56 with
747
                   presumably undefined results on previous implementations
748
                that were not assigned to a particular extension.
749
*/
750

    
751
const struct alpha_opcode alpha_opcodes[] = {
752
  { "halt",                SPCD(0x00,0x0000), BASE, ARG_NONE },
753
  { "draina",                SPCD(0x00,0x0002), BASE, ARG_NONE },
754
  { "bpt",                SPCD(0x00,0x0080), BASE, ARG_NONE },
755
  { "bugchk",                SPCD(0x00,0x0081), BASE, ARG_NONE },
756
  { "callsys",                SPCD(0x00,0x0083), BASE, ARG_NONE },
757
  { "chmk",                 SPCD(0x00,0x0083), BASE, ARG_NONE },
758
  { "imb",                SPCD(0x00,0x0086), BASE, ARG_NONE },
759
  { "rduniq",                SPCD(0x00,0x009e), BASE, ARG_NONE },
760
  { "wruniq",                SPCD(0x00,0x009f), BASE, ARG_NONE },
761
  { "gentrap",                SPCD(0x00,0x00aa), BASE, ARG_NONE },
762
  { "call_pal",                PCD(0x00), BASE, ARG_PCD },
763
  { "pal",                PCD(0x00), BASE, ARG_PCD },                /* alias */
764

    
765
  { "lda",                MEM(0x08), BASE, { RA, MDISP, ZB } },        /* pseudo */
766
  { "lda",                MEM(0x08), BASE, ARG_MEM },
767
  { "ldah",                MEM(0x09), BASE, { RA, MDISP, ZB } },        /* pseudo */
768
  { "ldah",                MEM(0x09), BASE, ARG_MEM },
769
  { "ldbu",                MEM(0x0A), BWX, ARG_MEM },
770
  { "unop",                MEM_(0x0B) | (30 << 16),
771
                        MEM_MASK, BASE, { ZA } },                /* pseudo */
772
  { "ldq_u",                MEM(0x0B), BASE, ARG_MEM },
773
  { "ldwu",                MEM(0x0C), BWX, ARG_MEM },
774
  { "stw",                MEM(0x0D), BWX, ARG_MEM },
775
  { "stb",                MEM(0x0E), BWX, ARG_MEM },
776
  { "stq_u",                MEM(0x0F), BASE, ARG_MEM },
777

    
778
  { "sextl",                OPR(0x10,0x00), BASE, ARG_OPRZ1 },        /* pseudo */
779
  { "sextl",                OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },        /* pseudo */
780
  { "addl",                OPR(0x10,0x00), BASE, ARG_OPR },
781
  { "addl",                OPRL(0x10,0x00), BASE, ARG_OPRL },
782
  { "s4addl",                OPR(0x10,0x02), BASE, ARG_OPR },
783
  { "s4addl",                OPRL(0x10,0x02), BASE, ARG_OPRL },
784
  { "negl",                OPR(0x10,0x09), BASE, ARG_OPRZ1 },        /* pseudo */
785
  { "negl",                OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },        /* pseudo */
786
  { "subl",                OPR(0x10,0x09), BASE, ARG_OPR },
787
  { "subl",                OPRL(0x10,0x09), BASE, ARG_OPRL },
788
  { "s4subl",                OPR(0x10,0x0B), BASE, ARG_OPR },
789
  { "s4subl",                OPRL(0x10,0x0B), BASE, ARG_OPRL },
790
  { "cmpbge",                OPR(0x10,0x0F), BASE, ARG_OPR },
791
  { "cmpbge",                OPRL(0x10,0x0F), BASE, ARG_OPRL },
792
  { "s8addl",                OPR(0x10,0x12), BASE, ARG_OPR },
793
  { "s8addl",                OPRL(0x10,0x12), BASE, ARG_OPRL },
794
  { "s8subl",                OPR(0x10,0x1B), BASE, ARG_OPR },
795
  { "s8subl",                OPRL(0x10,0x1B), BASE, ARG_OPRL },
796
  { "cmpult",                OPR(0x10,0x1D), BASE, ARG_OPR },
797
  { "cmpult",                OPRL(0x10,0x1D), BASE, ARG_OPRL },
798
  { "addq",                OPR(0x10,0x20), BASE, ARG_OPR },
799
  { "addq",                OPRL(0x10,0x20), BASE, ARG_OPRL },
800
  { "s4addq",                OPR(0x10,0x22), BASE, ARG_OPR },
801
  { "s4addq",                OPRL(0x10,0x22), BASE, ARG_OPRL },
802
  { "negq",                 OPR(0x10,0x29), BASE, ARG_OPRZ1 },        /* pseudo */
803
  { "negq",                 OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },        /* pseudo */
804
  { "subq",                OPR(0x10,0x29), BASE, ARG_OPR },
805
  { "subq",                OPRL(0x10,0x29), BASE, ARG_OPRL },
806
  { "s4subq",                OPR(0x10,0x2B), BASE, ARG_OPR },
807
  { "s4subq",                OPRL(0x10,0x2B), BASE, ARG_OPRL },
808
  { "cmpeq",                OPR(0x10,0x2D), BASE, ARG_OPR },
809
  { "cmpeq",                OPRL(0x10,0x2D), BASE, ARG_OPRL },
810
  { "s8addq",                OPR(0x10,0x32), BASE, ARG_OPR },
811
  { "s8addq",                OPRL(0x10,0x32), BASE, ARG_OPRL },
812
  { "s8subq",                OPR(0x10,0x3B), BASE, ARG_OPR },
813
  { "s8subq",                OPRL(0x10,0x3B), BASE, ARG_OPRL },
814
  { "cmpule",                OPR(0x10,0x3D), BASE, ARG_OPR },
815
  { "cmpule",                OPRL(0x10,0x3D), BASE, ARG_OPRL },
816
  { "addl/v",                OPR(0x10,0x40), BASE, ARG_OPR },
817
  { "addl/v",                OPRL(0x10,0x40), BASE, ARG_OPRL },
818
  { "negl/v",                OPR(0x10,0x49), BASE, ARG_OPRZ1 },        /* pseudo */
819
  { "negl/v",                OPRL(0x10,0x49), BASE, ARG_OPRLZ1 },        /* pseudo */
820
  { "subl/v",                OPR(0x10,0x49), BASE, ARG_OPR },
821
  { "subl/v",                OPRL(0x10,0x49), BASE, ARG_OPRL },
822
  { "cmplt",                OPR(0x10,0x4D), BASE, ARG_OPR },
823
  { "cmplt",                OPRL(0x10,0x4D), BASE, ARG_OPRL },
824
  { "addq/v",                OPR(0x10,0x60), BASE, ARG_OPR },
825
  { "addq/v",                OPRL(0x10,0x60), BASE, ARG_OPRL },
826
  { "negq/v",                OPR(0x10,0x69), BASE, ARG_OPRZ1 },        /* pseudo */
827
  { "negq/v",                OPRL(0x10,0x69), BASE, ARG_OPRLZ1 },        /* pseudo */
828
  { "subq/v",                OPR(0x10,0x69), BASE, ARG_OPR },
829
  { "subq/v",                OPRL(0x10,0x69), BASE, ARG_OPRL },
830
  { "cmple",                OPR(0x10,0x6D), BASE, ARG_OPR },
831
  { "cmple",                OPRL(0x10,0x6D), BASE, ARG_OPRL },
832

    
833
  { "and",                OPR(0x11,0x00), BASE, ARG_OPR },
834
  { "and",                OPRL(0x11,0x00), BASE, ARG_OPRL },
835
  { "andnot",                OPR(0x11,0x08), BASE, ARG_OPR },        /* alias */
836
  { "andnot",                OPRL(0x11,0x08), BASE, ARG_OPRL },        /* alias */
837
  { "bic",                OPR(0x11,0x08), BASE, ARG_OPR },
838
  { "bic",                OPRL(0x11,0x08), BASE, ARG_OPRL },
839
  { "cmovlbs",                OPR(0x11,0x14), BASE, ARG_OPR },
840
  { "cmovlbs",                OPRL(0x11,0x14), BASE, ARG_OPRL },
841
  { "cmovlbc",                OPR(0x11,0x16), BASE, ARG_OPR },
842
  { "cmovlbc",                OPRL(0x11,0x16), BASE, ARG_OPRL },
843
  { "nop",                OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
844
  { "clr",                OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
845
  { "mov",                OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
846
  { "mov",                OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
847
  { "mov",                OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
848
  { "or",                OPR(0x11,0x20), BASE, ARG_OPR },        /* alias */
849
  { "or",                OPRL(0x11,0x20), BASE, ARG_OPRL },        /* alias */
850
  { "bis",                OPR(0x11,0x20), BASE, ARG_OPR },
851
  { "bis",                OPRL(0x11,0x20), BASE, ARG_OPRL },
852
  { "cmoveq",                OPR(0x11,0x24), BASE, ARG_OPR },
853
  { "cmoveq",                OPRL(0x11,0x24), BASE, ARG_OPRL },
854
  { "cmovne",                OPR(0x11,0x26), BASE, ARG_OPR },
855
  { "cmovne",                OPRL(0x11,0x26), BASE, ARG_OPRL },
856
  { "not",                OPR(0x11,0x28), BASE, ARG_OPRZ1 },        /* pseudo */
857
  { "not",                OPRL(0x11,0x28), BASE, ARG_OPRLZ1 },        /* pseudo */
858
  { "ornot",                OPR(0x11,0x28), BASE, ARG_OPR },
859
  { "ornot",                OPRL(0x11,0x28), BASE, ARG_OPRL },
860
  { "xor",                OPR(0x11,0x40), BASE, ARG_OPR },
861
  { "xor",                OPRL(0x11,0x40), BASE, ARG_OPRL },
862
  { "cmovlt",                OPR(0x11,0x44), BASE, ARG_OPR },
863
  { "cmovlt",                OPRL(0x11,0x44), BASE, ARG_OPRL },
864
  { "cmovge",                OPR(0x11,0x46), BASE, ARG_OPR },
865
  { "cmovge",                OPRL(0x11,0x46), BASE, ARG_OPRL },
866
  { "eqv",                OPR(0x11,0x48), BASE, ARG_OPR },
867
  { "eqv",                OPRL(0x11,0x48), BASE, ARG_OPRL },
868
  { "xornot",                OPR(0x11,0x48), BASE, ARG_OPR },        /* alias */
869
  { "xornot",                OPRL(0x11,0x48), BASE, ARG_OPRL },        /* alias */
870
  { "amask",                OPR(0x11,0x61), BASE, ARG_OPRZ1 },        /* ev56 but */
871
  { "amask",                OPRL(0x11,0x61), BASE, ARG_OPRLZ1 },        /* ev56 but */
872
  { "cmovle",                OPR(0x11,0x64), BASE, ARG_OPR },
873
  { "cmovle",                OPRL(0x11,0x64), BASE, ARG_OPRL },
874
  { "cmovgt",                OPR(0x11,0x66), BASE, ARG_OPR },
875
  { "cmovgt",                OPRL(0x11,0x66), BASE, ARG_OPRL },
876
  { "implver",                OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
877
                            0xFFFFFFE0, BASE, { RC } },                /* ev56 but */
878

    
879
  { "mskbl",                OPR(0x12,0x02), BASE, ARG_OPR },
880
  { "mskbl",                OPRL(0x12,0x02), BASE, ARG_OPRL },
881
  { "extbl",                OPR(0x12,0x06), BASE, ARG_OPR },
882
  { "extbl",                OPRL(0x12,0x06), BASE, ARG_OPRL },
883
  { "insbl",                OPR(0x12,0x0B), BASE, ARG_OPR },
884
  { "insbl",                OPRL(0x12,0x0B), BASE, ARG_OPRL },
885
  { "mskwl",                OPR(0x12,0x12), BASE, ARG_OPR },
886
  { "mskwl",                OPRL(0x12,0x12), BASE, ARG_OPRL },
887
  { "extwl",                OPR(0x12,0x16), BASE, ARG_OPR },
888
  { "extwl",                OPRL(0x12,0x16), BASE, ARG_OPRL },
889
  { "inswl",                OPR(0x12,0x1B), BASE, ARG_OPR },
890
  { "inswl",                OPRL(0x12,0x1B), BASE, ARG_OPRL },
891
  { "mskll",                OPR(0x12,0x22), BASE, ARG_OPR },
892
  { "mskll",                OPRL(0x12,0x22), BASE, ARG_OPRL },
893
  { "extll",                OPR(0x12,0x26), BASE, ARG_OPR },
894
  { "extll",                OPRL(0x12,0x26), BASE, ARG_OPRL },
895
  { "insll",                OPR(0x12,0x2B), BASE, ARG_OPR },
896
  { "insll",                OPRL(0x12,0x2B), BASE, ARG_OPRL },
897
  { "zap",                OPR(0x12,0x30), BASE, ARG_OPR },
898
  { "zap",                OPRL(0x12,0x30), BASE, ARG_OPRL },
899
  { "zapnot",                OPR(0x12,0x31), BASE, ARG_OPR },
900
  { "zapnot",                OPRL(0x12,0x31), BASE, ARG_OPRL },
901
  { "mskql",                OPR(0x12,0x32), BASE, ARG_OPR },
902
  { "mskql",                OPRL(0x12,0x32), BASE, ARG_OPRL },
903
  { "srl",                OPR(0x12,0x34), BASE, ARG_OPR },
904
  { "srl",                OPRL(0x12,0x34), BASE, ARG_OPRL },
905
  { "extql",                OPR(0x12,0x36), BASE, ARG_OPR },
906
  { "extql",                OPRL(0x12,0x36), BASE, ARG_OPRL },
907
  { "sll",                OPR(0x12,0x39), BASE, ARG_OPR },
908
  { "sll",                OPRL(0x12,0x39), BASE, ARG_OPRL },
909
  { "insql",                OPR(0x12,0x3B), BASE, ARG_OPR },
910
  { "insql",                OPRL(0x12,0x3B), BASE, ARG_OPRL },
911
  { "sra",                OPR(0x12,0x3C), BASE, ARG_OPR },
912
  { "sra",                OPRL(0x12,0x3C), BASE, ARG_OPRL },
913
  { "mskwh",                OPR(0x12,0x52), BASE, ARG_OPR },
914
  { "mskwh",                OPRL(0x12,0x52), BASE, ARG_OPRL },
915
  { "inswh",                OPR(0x12,0x57), BASE, ARG_OPR },
916
  { "inswh",                OPRL(0x12,0x57), BASE, ARG_OPRL },
917
  { "extwh",                OPR(0x12,0x5A), BASE, ARG_OPR },
918
  { "extwh",                OPRL(0x12,0x5A), BASE, ARG_OPRL },
919
  { "msklh",                OPR(0x12,0x62), BASE, ARG_OPR },
920
  { "msklh",                OPRL(0x12,0x62), BASE, ARG_OPRL },
921
  { "inslh",                OPR(0x12,0x67), BASE, ARG_OPR },
922
  { "inslh",                OPRL(0x12,0x67), BASE, ARG_OPRL },
923
  { "extlh",                OPR(0x12,0x6A), BASE, ARG_OPR },
924
  { "extlh",                OPRL(0x12,0x6A), BASE, ARG_OPRL },
925
  { "mskqh",                OPR(0x12,0x72), BASE, ARG_OPR },
926
  { "mskqh",                OPRL(0x12,0x72), BASE, ARG_OPRL },
927
  { "insqh",                OPR(0x12,0x77), BASE, ARG_OPR },
928
  { "insqh",                OPRL(0x12,0x77), BASE, ARG_OPRL },
929
  { "extqh",                OPR(0x12,0x7A), BASE, ARG_OPR },
930
  { "extqh",                OPRL(0x12,0x7A), BASE, ARG_OPRL },
931

    
932
  { "mull",                OPR(0x13,0x00), BASE, ARG_OPR },
933
  { "mull",                OPRL(0x13,0x00), BASE, ARG_OPRL },
934
  { "mulq",                OPR(0x13,0x20), BASE, ARG_OPR },
935
  { "mulq",                OPRL(0x13,0x20), BASE, ARG_OPRL },
936
  { "umulh",                OPR(0x13,0x30), BASE, ARG_OPR },
937
  { "umulh",                OPRL(0x13,0x30), BASE, ARG_OPRL },
938
  { "mull/v",                OPR(0x13,0x40), BASE, ARG_OPR },
939
  { "mull/v",                OPRL(0x13,0x40), BASE, ARG_OPRL },
940
  { "mulq/v",                OPR(0x13,0x60), BASE, ARG_OPR },
941
  { "mulq/v",                OPRL(0x13,0x60), BASE, ARG_OPRL },
942

    
943
  { "itofs",                FP(0x14,0x004), CIX, { RA, ZB, FC } },
944
  { "sqrtf/c",                FP(0x14,0x00A), CIX, ARG_FPZ1 },
945
  { "sqrts/c",                FP(0x14,0x00B), CIX, ARG_FPZ1 },
946
  { "itoff",                FP(0x14,0x014), CIX, { RA, ZB, FC } },
947
  { "itoft",                FP(0x14,0x024), CIX, { RA, ZB, FC } },
948
  { "sqrtg/c",                FP(0x14,0x02A), CIX, ARG_FPZ1 },
949
  { "sqrtt/c",                FP(0x14,0x02B), CIX, ARG_FPZ1 },
950
  { "sqrts/m",                FP(0x14,0x04B), CIX, ARG_FPZ1 },
951
  { "sqrtt/m",                FP(0x14,0x06B), CIX, ARG_FPZ1 },
952
  { "sqrtf",                FP(0x14,0x08A), CIX, ARG_FPZ1 },
953
  { "sqrts",                FP(0x14,0x08B), CIX, ARG_FPZ1 },
954
  { "sqrtg",                FP(0x14,0x0AA), CIX, ARG_FPZ1 },
955
  { "sqrtt",                FP(0x14,0x0AB), CIX, ARG_FPZ1 },
956
  { "sqrts/d",                FP(0x14,0x0CB), CIX, ARG_FPZ1 },
957
  { "sqrtt/d",                FP(0x14,0x0EB), CIX, ARG_FPZ1 },
958
  { "sqrtf/uc",                FP(0x14,0x10A), CIX, ARG_FPZ1 },
959
  { "sqrts/uc",                FP(0x14,0x10B), CIX, ARG_FPZ1 },
960
  { "sqrtg/uc",                FP(0x14,0x12A), CIX, ARG_FPZ1 },
961
  { "sqrtt/uc",                FP(0x14,0x12B), CIX, ARG_FPZ1 },
962
  { "sqrts/um",                FP(0x14,0x14B), CIX, ARG_FPZ1 },
963
  { "sqrtt/um",                FP(0x14,0x16B), CIX, ARG_FPZ1 },
964
  { "sqrtf/u",                FP(0x14,0x18A), CIX, ARG_FPZ1 },
965
  { "sqrts/u",                FP(0x14,0x18B), CIX, ARG_FPZ1 },
966
  { "sqrtg/u",                FP(0x14,0x1AA), CIX, ARG_FPZ1 },
967
  { "sqrtt/u",                FP(0x14,0x1AB), CIX, ARG_FPZ1 },
968
  { "sqrts/ud",                FP(0x14,0x1CB), CIX, ARG_FPZ1 },
969
  { "sqrtt/ud",                FP(0x14,0x1EB), CIX, ARG_FPZ1 },
970
  { "sqrtf/sc",                FP(0x14,0x40A), CIX, ARG_FPZ1 },
971
  { "sqrtg/sc",                FP(0x14,0x42A), CIX, ARG_FPZ1 },
972
  { "sqrtf/s",                FP(0x14,0x48A), CIX, ARG_FPZ1 },
973
  { "sqrtg/s",                FP(0x14,0x4AA), CIX, ARG_FPZ1 },
974
  { "sqrtf/suc",        FP(0x14,0x50A), CIX, ARG_FPZ1 },
975
  { "sqrts/suc",        FP(0x14,0x50B), CIX, ARG_FPZ1 },
976
  { "sqrtg/suc",        FP(0x14,0x52A), CIX, ARG_FPZ1 },
977
  { "sqrtt/suc",        FP(0x14,0x52B), CIX, ARG_FPZ1 },
978
  { "sqrts/sum",        FP(0x14,0x54B), CIX, ARG_FPZ1 },
979
  { "sqrtt/sum",        FP(0x14,0x56B), CIX, ARG_FPZ1 },
980
  { "sqrtf/su",                FP(0x14,0x58A), CIX, ARG_FPZ1 },
981
  { "sqrts/su",                FP(0x14,0x58B), CIX, ARG_FPZ1 },
982
  { "sqrtg/su",                FP(0x14,0x5AA), CIX, ARG_FPZ1 },
983
  { "sqrtt/su",                FP(0x14,0x5AB), CIX, ARG_FPZ1 },
984
  { "sqrts/sud",        FP(0x14,0x5CB), CIX, ARG_FPZ1 },
985
  { "sqrtt/sud",        FP(0x14,0x5EB), CIX, ARG_FPZ1 },
986
  { "sqrts/suic",        FP(0x14,0x70B), CIX, ARG_FPZ1 },
987
  { "sqrtt/suic",        FP(0x14,0x72B), CIX, ARG_FPZ1 },
988
  { "sqrts/suim",        FP(0x14,0x74B), CIX, ARG_FPZ1 },
989
  { "sqrtt/suim",        FP(0x14,0x76B), CIX, ARG_FPZ1 },
990
  { "sqrts/sui",        FP(0x14,0x78B), CIX, ARG_FPZ1 },
991
  { "sqrtt/sui",        FP(0x14,0x7AB), CIX, ARG_FPZ1 },
992
  { "sqrts/suid",        FP(0x14,0x7CB), CIX, ARG_FPZ1 },
993
  { "sqrtt/suid",        FP(0x14,0x7EB), CIX, ARG_FPZ1 },
994

    
995
  { "addf/c",                FP(0x15,0x000), BASE, ARG_FP },
996
  { "subf/c",                FP(0x15,0x001), BASE, ARG_FP },
997
  { "mulf/c",                FP(0x15,0x002), BASE, ARG_FP },
998
  { "divf/c",                FP(0x15,0x003), BASE, ARG_FP },
999
  { "cvtdg/c",                FP(0x15,0x01E), BASE, ARG_FPZ1 },
1000
  { "addg/c",                FP(0x15,0x020), BASE, ARG_FP },
1001
  { "subg/c",                FP(0x15,0x021), BASE, ARG_FP },
1002
  { "mulg/c",                FP(0x15,0x022), BASE, ARG_FP },
1003
  { "divg/c",                FP(0x15,0x023), BASE, ARG_FP },
1004
  { "cvtgf/c",                FP(0x15,0x02C), BASE, ARG_FPZ1 },
1005
  { "cvtgd/c",                FP(0x15,0x02D), BASE, ARG_FPZ1 },
1006
  { "cvtgq/c",                FP(0x15,0x02F), BASE, ARG_FPZ1 },
1007
  { "cvtqf/c",                FP(0x15,0x03C), BASE, ARG_FPZ1 },
1008
  { "cvtqg/c",                FP(0x15,0x03E), BASE, ARG_FPZ1 },
1009
  { "addf",                FP(0x15,0x080), BASE, ARG_FP },
1010
  { "negf",                FP(0x15,0x081), BASE, ARG_FPZ1 },        /* pseudo */
1011
  { "subf",                FP(0x15,0x081), BASE, ARG_FP },
1012
  { "mulf",                FP(0x15,0x082), BASE, ARG_FP },
1013
  { "divf",                FP(0x15,0x083), BASE, ARG_FP },
1014
  { "cvtdg",                FP(0x15,0x09E), BASE, ARG_FPZ1 },
1015
  { "addg",                FP(0x15,0x0A0), BASE, ARG_FP },
1016
  { "negg",                FP(0x15,0x0A1), BASE, ARG_FPZ1 },        /* pseudo */
1017
  { "subg",                FP(0x15,0x0A1), BASE, ARG_FP },
1018
  { "mulg",                FP(0x15,0x0A2), BASE, ARG_FP },
1019
  { "divg",                FP(0x15,0x0A3), BASE, ARG_FP },
1020
  { "cmpgeq",                FP(0x15,0x0A5), BASE, ARG_FP },
1021
  { "cmpglt",                FP(0x15,0x0A6), BASE, ARG_FP },
1022
  { "cmpgle",                FP(0x15,0x0A7), BASE, ARG_FP },
1023
  { "cvtgf",                FP(0x15,0x0AC), BASE, ARG_FPZ1 },
1024
  { "cvtgd",                FP(0x15,0x0AD), BASE, ARG_FPZ1 },
1025
  { "cvtgq",                FP(0x15,0x0AF), BASE, ARG_FPZ1 },
1026
  { "cvtqf",                FP(0x15,0x0BC), BASE, ARG_FPZ1 },
1027
  { "cvtqg",                FP(0x15,0x0BE), BASE, ARG_FPZ1 },
1028
  { "addf/uc",                FP(0x15,0x100), BASE, ARG_FP },
1029
  { "subf/uc",                FP(0x15,0x101), BASE, ARG_FP },
1030
  { "mulf/uc",                FP(0x15,0x102), BASE, ARG_FP },
1031
  { "divf/uc",                FP(0x15,0x103), BASE, ARG_FP },
1032
  { "cvtdg/uc",                FP(0x15,0x11E), BASE, ARG_FPZ1 },
1033
  { "addg/uc",                FP(0x15,0x120), BASE, ARG_FP },
1034
  { "subg/uc",                FP(0x15,0x121), BASE, ARG_FP },
1035
  { "mulg/uc",                FP(0x15,0x122), BASE, ARG_FP },
1036
  { "divg/uc",                FP(0x15,0x123), BASE, ARG_FP },
1037
  { "cvtgf/uc",                FP(0x15,0x12C), BASE, ARG_FPZ1 },
1038
  { "cvtgd/uc",                FP(0x15,0x12D), BASE, ARG_FPZ1 },
1039
  { "cvtgq/vc",                FP(0x15,0x12F), BASE, ARG_FPZ1 },
1040
  { "addf/u",                FP(0x15,0x180), BASE, ARG_FP },
1041
  { "subf/u",                FP(0x15,0x181), BASE, ARG_FP },
1042
  { "mulf/u",                FP(0x15,0x182), BASE, ARG_FP },
1043
  { "divf/u",                FP(0x15,0x183), BASE, ARG_FP },
1044
  { "cvtdg/u",                FP(0x15,0x19E), BASE, ARG_FPZ1 },
1045
  { "addg/u",                FP(0x15,0x1A0), BASE, ARG_FP },
1046
  { "subg/u",                FP(0x15,0x1A1), BASE, ARG_FP },
1047
  { "mulg/u",                FP(0x15,0x1A2), BASE, ARG_FP },
1048
  { "divg/u",                FP(0x15,0x1A3), BASE, ARG_FP },
1049
  { "cvtgf/u",                FP(0x15,0x1AC), BASE, ARG_FPZ1 },
1050
  { "cvtgd/u",                FP(0x15,0x1AD), BASE, ARG_FPZ1 },
1051
  { "cvtgq/v",                FP(0x15,0x1AF), BASE, ARG_FPZ1 },
1052
  { "addf/sc",                FP(0x15,0x400), BASE, ARG_FP },
1053
  { "subf/sc",                FP(0x15,0x401), BASE, ARG_FP },
1054
  { "mulf/sc",                FP(0x15,0x402), BASE, ARG_FP },
1055
  { "divf/sc",                FP(0x15,0x403), BASE, ARG_FP },
1056
  { "cvtdg/sc",                FP(0x15,0x41E), BASE, ARG_FPZ1 },
1057
  { "addg/sc",                FP(0x15,0x420), BASE, ARG_FP },
1058
  { "subg/sc",                FP(0x15,0x421), BASE, ARG_FP },
1059
  { "mulg/sc",                FP(0x15,0x422), BASE, ARG_FP },
1060
  { "divg/sc",                FP(0x15,0x423), BASE, ARG_FP },
1061
  { "cvtgf/sc",                FP(0x15,0x42C), BASE, ARG_FPZ1 },
1062
  { "cvtgd/sc",                FP(0x15,0x42D), BASE, ARG_FPZ1 },
1063
  { "cvtgq/sc",                FP(0x15,0x42F), BASE, ARG_FPZ1 },
1064
  { "addf/s",                FP(0x15,0x480), BASE, ARG_FP },
1065
  { "negf/s",                FP(0x15,0x481), BASE, ARG_FPZ1 },        /* pseudo */
1066
  { "subf/s",                FP(0x15,0x481), BASE, ARG_FP },
1067
  { "mulf/s",                FP(0x15,0x482), BASE, ARG_FP },
1068
  { "divf/s",                FP(0x15,0x483), BASE, ARG_FP },
1069
  { "cvtdg/s",                FP(0x15,0x49E), BASE, ARG_FPZ1 },
1070
  { "addg/s",                FP(0x15,0x4A0), BASE, ARG_FP },
1071
  { "negg/s",                FP(0x15,0x4A1), BASE, ARG_FPZ1 },        /* pseudo */
1072
  { "subg/s",                FP(0x15,0x4A1), BASE, ARG_FP },
1073
  { "mulg/s",                FP(0x15,0x4A2), BASE, ARG_FP },
1074
  { "divg/s",                FP(0x15,0x4A3), BASE, ARG_FP },
1075
  { "cmpgeq/s",                FP(0x15,0x4A5), BASE, ARG_FP },
1076
  { "cmpglt/s",                FP(0x15,0x4A6), BASE, ARG_FP },
1077
  { "cmpgle/s",                FP(0x15,0x4A7), BASE, ARG_FP },
1078
  { "cvtgf/s",                FP(0x15,0x4AC), BASE, ARG_FPZ1 },
1079
  { "cvtgd/s",                FP(0x15,0x4AD), BASE, ARG_FPZ1 },
1080
  { "cvtgq/s",                FP(0x15,0x4AF), BASE, ARG_FPZ1 },
1081
  { "addf/suc",                FP(0x15,0x500), BASE, ARG_FP },
1082
  { "subf/suc",                FP(0x15,0x501), BASE, ARG_FP },
1083
  { "mulf/suc",                FP(0x15,0x502), BASE, ARG_FP },
1084
  { "divf/suc",                FP(0x15,0x503), BASE, ARG_FP },
1085
  { "cvtdg/suc",        FP(0x15,0x51E), BASE, ARG_FPZ1 },
1086
  { "addg/suc",                FP(0x15,0x520), BASE, ARG_FP },
1087
  { "subg/suc",                FP(0x15,0x521), BASE, ARG_FP },
1088
  { "mulg/suc",                FP(0x15,0x522), BASE, ARG_FP },
1089
  { "divg/suc",                FP(0x15,0x523), BASE, ARG_FP },
1090
  { "cvtgf/suc",        FP(0x15,0x52C), BASE, ARG_FPZ1 },
1091
  { "cvtgd/suc",        FP(0x15,0x52D), BASE, ARG_FPZ1 },
1092
  { "cvtgq/svc",        FP(0x15,0x52F), BASE, ARG_FPZ1 },
1093
  { "addf/su",                FP(0x15,0x580), BASE, ARG_FP },
1094
  { "subf/su",                FP(0x15,0x581), BASE, ARG_FP },
1095
  { "mulf/su",                FP(0x15,0x582), BASE, ARG_FP },
1096
  { "divf/su",                FP(0x15,0x583), BASE, ARG_FP },
1097
  { "cvtdg/su",                FP(0x15,0x59E), BASE, ARG_FPZ1 },
1098
  { "addg/su",                FP(0x15,0x5A0), BASE, ARG_FP },
1099
  { "subg/su",                FP(0x15,0x5A1), BASE, ARG_FP },
1100
  { "mulg/su",                FP(0x15,0x5A2), BASE, ARG_FP },
1101
  { "divg/su",                FP(0x15,0x5A3), BASE, ARG_FP },
1102
  { "cvtgf/su",                FP(0x15,0x5AC), BASE, ARG_FPZ1 },
1103
  { "cvtgd/su",                FP(0x15,0x5AD), BASE, ARG_FPZ1 },
1104
  { "cvtgq/sv",                FP(0x15,0x5AF), BASE, ARG_FPZ1 },
1105

    
1106
  { "adds/c",                FP(0x16,0x000), BASE, ARG_FP },
1107
  { "subs/c",                FP(0x16,0x001), BASE, ARG_FP },
1108
  { "muls/c",                FP(0x16,0x002), BASE, ARG_FP },
1109
  { "divs/c",                FP(0x16,0x003), BASE, ARG_FP },
1110
  { "addt/c",                FP(0x16,0x020), BASE, ARG_FP },
1111
  { "subt/c",                FP(0x16,0x021), BASE, ARG_FP },
1112
  { "mult/c",                FP(0x16,0x022), BASE, ARG_FP },
1113
  { "divt/c",                FP(0x16,0x023), BASE, ARG_FP },
1114
  { "cvtts/c",                FP(0x16,0x02C), BASE, ARG_FPZ1 },
1115
  { "cvttq/c",                FP(0x16,0x02F), BASE, ARG_FPZ1 },
1116
  { "cvtqs/c",                FP(0x16,0x03C), BASE, ARG_FPZ1 },
1117
  { "cvtqt/c",                FP(0x16,0x03E), BASE, ARG_FPZ1 },
1118
  { "adds/m",                FP(0x16,0x040), BASE, ARG_FP },
1119
  { "subs/m",                FP(0x16,0x041), BASE, ARG_FP },
1120
  { "muls/m",                FP(0x16,0x042), BASE, ARG_FP },
1121
  { "divs/m",                FP(0x16,0x043), BASE, ARG_FP },
1122
  { "addt/m",                FP(0x16,0x060), BASE, ARG_FP },
1123
  { "subt/m",                FP(0x16,0x061), BASE, ARG_FP },
1124
  { "mult/m",                FP(0x16,0x062), BASE, ARG_FP },
1125
  { "divt/m",                FP(0x16,0x063), BASE, ARG_FP },
1126
  { "cvtts/m",                FP(0x16,0x06C), BASE, ARG_FPZ1 },
1127
  { "cvttq/m",                FP(0x16,0x06F), BASE, ARG_FPZ1 },
1128
  { "cvtqs/m",                FP(0x16,0x07C), BASE, ARG_FPZ1 },
1129
  { "cvtqt/m",                FP(0x16,0x07E), BASE, ARG_FPZ1 },
1130
  { "adds",                FP(0x16,0x080), BASE, ARG_FP },
1131
  { "negs",                 FP(0x16,0x081), BASE, ARG_FPZ1 },        /* pseudo */
1132
  { "subs",                FP(0x16,0x081), BASE, ARG_FP },
1133
  { "muls",                FP(0x16,0x082), BASE, ARG_FP },
1134
  { "divs",                FP(0x16,0x083), BASE, ARG_FP },
1135
  { "addt",                FP(0x16,0x0A0), BASE, ARG_FP },
1136
  { "negt",                 FP(0x16,0x0A1), BASE, ARG_FPZ1 },        /* pseudo */
1137
  { "subt",                FP(0x16,0x0A1), BASE, ARG_FP },
1138
  { "mult",                FP(0x16,0x0A2), BASE, ARG_FP },
1139
  { "divt",                FP(0x16,0x0A3), BASE, ARG_FP },
1140
  { "cmptun",                FP(0x16,0x0A4), BASE, ARG_FP },
1141
  { "cmpteq",                FP(0x16,0x0A5), BASE, ARG_FP },
1142
  { "cmptlt",                FP(0x16,0x0A6), BASE, ARG_FP },
1143
  { "cmptle",                FP(0x16,0x0A7), BASE, ARG_FP },
1144
  { "cvtts",                FP(0x16,0x0AC), BASE, ARG_FPZ1 },
1145
  { "cvttq",                FP(0x16,0x0AF), BASE, ARG_FPZ1 },
1146
  { "cvtqs",                FP(0x16,0x0BC), BASE, ARG_FPZ1 },
1147
  { "cvtqt",                FP(0x16,0x0BE), BASE, ARG_FPZ1 },
1148
  { "adds/d",                FP(0x16,0x0C0), BASE, ARG_FP },
1149
  { "subs/d",                FP(0x16,0x0C1), BASE, ARG_FP },
1150
  { "muls/d",                FP(0x16,0x0C2), BASE, ARG_FP },
1151
  { "divs/d",                FP(0x16,0x0C3), BASE, ARG_FP },
1152
  { "addt/d",                FP(0x16,0x0E0), BASE, ARG_FP },
1153
  { "subt/d",                FP(0x16,0x0E1), BASE, ARG_FP },
1154
  { "mult/d",                FP(0x16,0x0E2), BASE, ARG_FP },
1155
  { "divt/d",                FP(0x16,0x0E3), BASE, ARG_FP },
1156
  { "cvtts/d",                FP(0x16,0x0EC), BASE, ARG_FPZ1 },
1157
  { "cvttq/d",                FP(0x16,0x0EF), BASE, ARG_FPZ1 },
1158
  { "cvtqs/d",                FP(0x16,0x0FC), BASE, ARG_FPZ1 },
1159
  { "cvtqt/d",                FP(0x16,0x0FE), BASE, ARG_FPZ1 },
1160
  { "adds/uc",                FP(0x16,0x100), BASE, ARG_FP },
1161
  { "subs/uc",                FP(0x16,0x101), BASE, ARG_FP },
1162
  { "muls/uc",                FP(0x16,0x102), BASE, ARG_FP },
1163
  { "divs/uc",                FP(0x16,0x103), BASE, ARG_FP },
1164
  { "addt/uc",                FP(0x16,0x120), BASE, ARG_FP },
1165
  { "subt/uc",                FP(0x16,0x121), BASE, ARG_FP },
1166
  { "mult/uc",                FP(0x16,0x122), BASE, ARG_FP },
1167
  { "divt/uc",                FP(0x16,0x123), BASE, ARG_FP },
1168
  { "cvtts/uc",                FP(0x16,0x12C), BASE, ARG_FPZ1 },
1169
  { "cvttq/vc",                FP(0x16,0x12F), BASE, ARG_FPZ1 },
1170
  { "adds/um",                FP(0x16,0x140), BASE, ARG_FP },
1171
  { "subs/um",                FP(0x16,0x141), BASE, ARG_FP },
1172
  { "muls/um",                FP(0x16,0x142), BASE, ARG_FP },
1173
  { "divs/um",                FP(0x16,0x143), BASE, ARG_FP },
1174
  { "addt/um",                FP(0x16,0x160), BASE, ARG_FP },
1175
  { "subt/um",                FP(0x16,0x161), BASE, ARG_FP },
1176
  { "mult/um",                FP(0x16,0x162), BASE, ARG_FP },
1177
  { "divt/um",                FP(0x16,0x163), BASE, ARG_FP },
1178
  { "cvtts/um",                FP(0x16,0x16C), BASE, ARG_FPZ1 },
1179
  { "cvttq/vm",                FP(0x16,0x16F), BASE, ARG_FPZ1 },
1180
  { "adds/u",                FP(0x16,0x180), BASE, ARG_FP },
1181
  { "subs/u",                FP(0x16,0x181), BASE, ARG_FP },
1182
  { "muls/u",                FP(0x16,0x182), BASE, ARG_FP },
1183
  { "divs/u",                FP(0x16,0x183), BASE, ARG_FP },
1184
  { "addt/u",                FP(0x16,0x1A0), BASE, ARG_FP },
1185
  { "subt/u",                FP(0x16,0x1A1), BASE, ARG_FP },
1186
  { "mult/u",                FP(0x16,0x1A2), BASE, ARG_FP },
1187
  { "divt/u",                FP(0x16,0x1A3), BASE, ARG_FP },
1188
  { "cvtts/u",                FP(0x16,0x1AC), BASE, ARG_FPZ1 },
1189
  { "cvttq/v",                FP(0x16,0x1AF), BASE, ARG_FPZ1 },
1190
  { "adds/ud",                FP(0x16,0x1C0), BASE, ARG_FP },
1191
  { "subs/ud",                FP(0x16,0x1C1), BASE, ARG_FP },
1192
  { "muls/ud",                FP(0x16,0x1C2), BASE, ARG_FP },
1193
  { "divs/ud",                FP(0x16,0x1C3), BASE, ARG_FP },
1194
  { "addt/ud",                FP(0x16,0x1E0), BASE, ARG_FP },
1195
  { "subt/ud",                FP(0x16,0x1E1), BASE, ARG_FP },
1196
  { "mult/ud",                FP(0x16,0x1E2), BASE, ARG_FP },
1197
  { "divt/ud",                FP(0x16,0x1E3), BASE, ARG_FP },
1198
  { "cvtts/ud",                FP(0x16,0x1EC), BASE, ARG_FPZ1 },
1199
  { "cvttq/vd",                FP(0x16,0x1EF), BASE, ARG_FPZ1 },
1200
  { "cvtst",                FP(0x16,0x2AC), BASE, ARG_FPZ1 },
1201
  { "adds/suc",                FP(0x16,0x500), BASE, ARG_FP },
1202
  { "subs/suc",                FP(0x16,0x501), BASE, ARG_FP },
1203
  { "muls/suc",                FP(0x16,0x502), BASE, ARG_FP },
1204
  { "divs/suc",                FP(0x16,0x503), BASE, ARG_FP },
1205
  { "addt/suc",                FP(0x16,0x520), BASE, ARG_FP },
1206
  { "subt/suc",                FP(0x16,0x521), BASE, ARG_FP },
1207
  { "mult/suc",                FP(0x16,0x522), BASE, ARG_FP },
1208
  { "divt/suc",                FP(0x16,0x523), BASE, ARG_FP },
1209
  { "cvtts/suc",        FP(0x16,0x52C), BASE, ARG_FPZ1 },
1210
  { "cvttq/svc",        FP(0x16,0x52F), BASE, ARG_FPZ1 },
1211
  { "adds/sum",                FP(0x16,0x540), BASE, ARG_FP },
1212
  { "subs/sum",                FP(0x16,0x541), BASE, ARG_FP },
1213
  { "muls/sum",                FP(0x16,0x542), BASE, ARG_FP },
1214
  { "divs/sum",                FP(0x16,0x543), BASE, ARG_FP },
1215
  { "addt/sum",                FP(0x16,0x560), BASE, ARG_FP },
1216
  { "subt/sum",                FP(0x16,0x561), BASE, ARG_FP },
1217
  { "mult/sum",                FP(0x16,0x562), BASE, ARG_FP },
1218
  { "divt/sum",                FP(0x16,0x563), BASE, ARG_FP },
1219
  { "cvtts/sum",        FP(0x16,0x56C), BASE, ARG_FPZ1 },
1220
  { "cvttq/svm",        FP(0x16,0x56F), BASE, ARG_FPZ1 },
1221
  { "adds/su",                FP(0x16,0x580), BASE, ARG_FP },
1222
  { "negs/su",                FP(0x16,0x581), BASE, ARG_FPZ1 },        /* pseudo */
1223
  { "subs/su",                FP(0x16,0x581), BASE, ARG_FP },
1224
  { "muls/su",                FP(0x16,0x582), BASE, ARG_FP },
1225
  { "divs/su",                FP(0x16,0x583), BASE, ARG_FP },
1226
  { "addt/su",                FP(0x16,0x5A0), BASE, ARG_FP },
1227
  { "negt/su",                FP(0x16,0x5A1), BASE, ARG_FPZ1 },        /* pseudo */
1228
  { "subt/su",                FP(0x16,0x5A1), BASE, ARG_FP },
1229
  { "mult/su",                FP(0x16,0x5A2), BASE, ARG_FP },
1230
  { "divt/su",                FP(0x16,0x5A3), BASE, ARG_FP },
1231
  { "cmptun/su",        FP(0x16,0x5A4), BASE, ARG_FP },
1232
  { "cmpteq/su",        FP(0x16,0x5A5), BASE, ARG_FP },
1233
  { "cmptlt/su",        FP(0x16,0x5A6), BASE, ARG_FP },
1234
  { "cmptle/su",        FP(0x16,0x5A7), BASE, ARG_FP },
1235
  { "cvtts/su",                FP(0x16,0x5AC), BASE, ARG_FPZ1 },
1236
  { "cvttq/sv",                FP(0x16,0x5AF), BASE, ARG_FPZ1 },
1237
  { "adds/sud",                FP(0x16,0x5C0), BASE, ARG_FP },
1238
  { "subs/sud",                FP(0x16,0x5C1), BASE, ARG_FP },
1239
  { "muls/sud",                FP(0x16,0x5C2), BASE, ARG_FP },
1240
  { "divs/sud",                FP(0x16,0x5C3), BASE, ARG_FP },
1241
  { "addt/sud",                FP(0x16,0x5E0), BASE, ARG_FP },
1242
  { "subt/sud",                FP(0x16,0x5E1), BASE, ARG_FP },
1243
  { "mult/sud",                FP(0x16,0x5E2), BASE, ARG_FP },
1244
  { "divt/sud",                FP(0x16,0x5E3), BASE, ARG_FP },
1245
  { "cvtts/sud",        FP(0x16,0x5EC), BASE, ARG_FPZ1 },
1246
  { "cvttq/svd",        FP(0x16,0x5EF), BASE, ARG_FPZ1 },
1247
  { "cvtst/s",                FP(0x16,0x6AC), BASE, ARG_FPZ1 },
1248
  { "adds/suic",        FP(0x16,0x700), BASE, ARG_FP },
1249
  { "subs/suic",        FP(0x16,0x701), BASE, ARG_FP },
1250
  { "muls/suic",        FP(0x16,0x702), BASE, ARG_FP },
1251
  { "divs/suic",        FP(0x16,0x703), BASE, ARG_FP },
1252
  { "addt/suic",        FP(0x16,0x720), BASE, ARG_FP },
1253
  { "subt/suic",        FP(0x16,0x721), BASE, ARG_FP },
1254
  { "mult/suic",        FP(0x16,0x722), BASE, ARG_FP },
1255
  { "divt/suic",        FP(0x16,0x723), BASE, ARG_FP },
1256
  { "cvtts/suic",        FP(0x16,0x72C), BASE, ARG_FPZ1 },
1257
  { "cvttq/svic",        FP(0x16,0x72F), BASE, ARG_FPZ1 },
1258
  { "cvtqs/suic",        FP(0x16,0x73C), BASE, ARG_FPZ1 },
1259
  { "cvtqt/suic",        FP(0x16,0x73E), BASE, ARG_FPZ1 },
1260
  { "adds/suim",        FP(0x16,0x740), BASE, ARG_FP },
1261
  { "subs/suim",        FP(0x16,0x741), BASE, ARG_FP },
1262
  { "muls/suim",        FP(0x16,0x742), BASE, ARG_FP },
1263
  { "divs/suim",        FP(0x16,0x743), BASE, ARG_FP },
1264
  { "addt/suim",        FP(0x16,0x760), BASE, ARG_FP },
1265
  { "subt/suim",        FP(0x16,0x761), BASE, ARG_FP },
1266
  { "mult/suim",        FP(0x16,0x762), BASE, ARG_FP },
1267
  { "divt/suim",        FP(0x16,0x763), BASE, ARG_FP },
1268
  { "cvtts/suim",        FP(0x16,0x76C), BASE, ARG_FPZ1 },
1269
  { "cvttq/svim",        FP(0x16,0x76F), BASE, ARG_FPZ1 },
1270
  { "cvtqs/suim",        FP(0x16,0x77C), BASE, ARG_FPZ1 },
1271
  { "cvtqt/suim",        FP(0x16,0x77E), BASE, ARG_FPZ1 },
1272
  { "adds/sui",                FP(0x16,0x780), BASE, ARG_FP },
1273
  { "negs/sui",         FP(0x16,0x781), BASE, ARG_FPZ1 },        /* pseudo */
1274
  { "subs/sui",                FP(0x16,0x781), BASE, ARG_FP },
1275
  { "muls/sui",                FP(0x16,0x782), BASE, ARG_FP },
1276
  { "divs/sui",                FP(0x16,0x783), BASE, ARG_FP },
1277
  { "addt/sui",                FP(0x16,0x7A0), BASE, ARG_FP },
1278
  { "negt/sui",         FP(0x16,0x7A1), BASE, ARG_FPZ1 },        /* pseudo */
1279
  { "subt/sui",                FP(0x16,0x7A1), BASE, ARG_FP },
1280
  { "mult/sui",                FP(0x16,0x7A2), BASE, ARG_FP },
1281
  { "divt/sui",                FP(0x16,0x7A3), BASE, ARG_FP },
1282
  { "cvtts/sui",        FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1283
  { "cvttq/svi",        FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1284
  { "cvtqs/sui",        FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1285
  { "cvtqt/sui",        FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1286
  { "adds/suid",        FP(0x16,0x7C0), BASE, ARG_FP },
1287
  { "subs/suid",        FP(0x16,0x7C1), BASE, ARG_FP },
1288
  { "muls/suid",        FP(0x16,0x7C2), BASE, ARG_FP },
1289
  { "divs/suid",        FP(0x16,0x7C3), BASE, ARG_FP },
1290
  { "addt/suid",        FP(0x16,0x7E0), BASE, ARG_FP },
1291
  { "subt/suid",        FP(0x16,0x7E1), BASE, ARG_FP },
1292
  { "mult/suid",        FP(0x16,0x7E2), BASE, ARG_FP },
1293
  { "divt/suid",        FP(0x16,0x7E3), BASE, ARG_FP },
1294
  { "cvtts/suid",        FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1295
  { "cvttq/svid",        FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1296
  { "cvtqs/suid",        FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1297
  { "cvtqt/suid",        FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1298

    
1299
  { "cvtlq",                FP(0x17,0x010), BASE, ARG_FPZ1 },
1300
  { "fnop",                FP(0x17,0x020), BASE, { ZA, ZB, ZC } },        /* pseudo */
1301
  { "fclr",                FP(0x17,0x020), BASE, { ZA, ZB, FC } },        /* pseudo */
1302
  { "fabs",                FP(0x17,0x020), BASE, ARG_FPZ1 },        /* pseudo */
1303
  { "fmov",                FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1304
  { "cpys",                FP(0x17,0x020), BASE, ARG_FP },
1305
  { "fneg",                FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1306
  { "cpysn",                FP(0x17,0x021), BASE, ARG_FP },
1307
  { "cpyse",                FP(0x17,0x022), BASE, ARG_FP },
1308
  { "mt_fpcr",                FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1309
  { "mf_fpcr",                FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1310
  { "fcmoveq",                FP(0x17,0x02A), BASE, ARG_FP },
1311
  { "fcmovne",                FP(0x17,0x02B), BASE, ARG_FP },
1312
  { "fcmovlt",                FP(0x17,0x02C), BASE, ARG_FP },
1313
  { "fcmovge",                FP(0x17,0x02D), BASE, ARG_FP },
1314
  { "fcmovle",                FP(0x17,0x02E), BASE, ARG_FP },
1315
  { "fcmovgt",                FP(0x17,0x02F), BASE, ARG_FP },
1316
  { "cvtql",                FP(0x17,0x030), BASE, ARG_FPZ1 },
1317
  { "cvtql/v",                FP(0x17,0x130), BASE, ARG_FPZ1 },
1318
  { "cvtql/sv",                FP(0x17,0x530), BASE, ARG_FPZ1 },
1319

    
1320
  { "trapb",                MFC(0x18,0x0000), BASE, ARG_NONE },
1321
  { "draint",                MFC(0x18,0x0000), BASE, ARG_NONE },        /* alias */
1322
  { "excb",                MFC(0x18,0x0400), BASE, ARG_NONE },
1323
  { "mb",                MFC(0x18,0x4000), BASE, ARG_NONE },
1324
  { "wmb",                MFC(0x18,0x4400), BASE, ARG_NONE },
1325
  { "fetch",                MFC(0x18,0x8000), BASE, { ZA, PRB } },
1326
  { "fetch_m",                MFC(0x18,0xA000), BASE, { ZA, PRB } },
1327
  { "rpcc",                MFC(0x18,0xC000), BASE, { RA } },
1328
  { "rc",                MFC(0x18,0xE000), BASE, { RA } },
1329
  { "ecb",                MFC(0x18,0xE800), BASE, { ZA, PRB } },        /* ev56 una */
1330
  { "rs",                MFC(0x18,0xF000), BASE, { RA } },
1331
  { "wh64",                MFC(0x18,0xF800), BASE, { ZA, PRB } },        /* ev56 una */
1332
  { "wh64en",                MFC(0x18,0xFC00), BASE, { ZA, PRB } },        /* ev7 una */
1333

    
1334
  { "hw_mfpr",                OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1335
  { "hw_mfpr",                OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1336
  { "hw_mfpr",                OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1337
  { "hw_mfpr/i",        OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1338
  { "hw_mfpr/a",        OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1339
  { "hw_mfpr/ai",        OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1340
  { "hw_mfpr/p",        OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1341
  { "hw_mfpr/pi",        OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1342
  { "hw_mfpr/pa",        OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1343
  { "hw_mfpr/pai",        OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1344
  { "pal19",                PCD(0x19), BASE, ARG_PCD },
1345

    
1346
  { "jmp",                MBR_(0x1A,0), MBR_MASK | 0x3FFF,        /* pseudo */
1347
                        BASE, { ZA, CPRB } },
1348
  { "jmp",                MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1349
  { "jsr",                MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1350
  { "ret",                MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
1351
                        0xFFFFFFFF, BASE, { 0 } },
1352
  { "ret",                MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1353
  { "jcr",                MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1354
  { "jsr_coroutine",        MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1355

    
1356
  { "hw_ldl",                EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1357
  { "hw_ldl",                EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1358
  { "hw_ldl",                EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1359
  { "hw_ldl/a",                EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1360
  { "hw_ldl/a",                EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1361
  { "hw_ldl/a",                EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1362
  { "hw_ldl/al",        EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1363
  { "hw_ldl/ar",        EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1364
  { "hw_ldl/av",        EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1365
  { "hw_ldl/avl",        EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1366
  { "hw_ldl/aw",        EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1367
  { "hw_ldl/awl",        EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1368
  { "hw_ldl/awv",        EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1369
  { "hw_ldl/awvl",        EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1370
  { "hw_ldl/l",                EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1371
  { "hw_ldl/p",                EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1372
  { "hw_ldl/p",                EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1373
  { "hw_ldl/p",                EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1374
  { "hw_ldl/pa",        EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1375
  { "hw_ldl/pa",        EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1376
  { "hw_ldl/pal",        EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1377
  { "hw_ldl/par",        EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1378
  { "hw_ldl/pav",        EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1379
  { "hw_ldl/pavl",        EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1380
  { "hw_ldl/paw",        EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1381
  { "hw_ldl/pawl",        EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1382
  { "hw_ldl/pawv",        EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1383
  { "hw_ldl/pawvl",        EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1384
  { "hw_ldl/pl",        EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1385
  { "hw_ldl/pr",        EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1386
  { "hw_ldl/pv",        EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1387
  { "hw_ldl/pvl",        EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1388
  { "hw_ldl/pw",        EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1389
  { "hw_ldl/pwl",        EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1390
  { "hw_ldl/pwv",        EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1391
  { "hw_ldl/pwvl",        EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1392
  { "hw_ldl/r",                EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1393
  { "hw_ldl/v",                EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1394
  { "hw_ldl/v",                EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1395
  { "hw_ldl/vl",        EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1396
  { "hw_ldl/w",                EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1397
  { "hw_ldl/w",                EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1398
  { "hw_ldl/wa",        EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1399
  { "hw_ldl/wl",        EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1400
  { "hw_ldl/wv",        EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1401
  { "hw_ldl/wvl",        EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1402
  { "hw_ldl_l",                EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1403
  { "hw_ldl_l/a",        EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1404
  { "hw_ldl_l/av",        EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1405
  { "hw_ldl_l/aw",        EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1406
  { "hw_ldl_l/awv",        EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1407
  { "hw_ldl_l/p",        EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1408
  { "hw_ldl_l/p",        EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1409
  { "hw_ldl_l/pa",        EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1410
  { "hw_ldl_l/pav",        EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1411
  { "hw_ldl_l/paw",        EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1412
  { "hw_ldl_l/pawv",        EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1413
  { "hw_ldl_l/pv",        EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1414
  { "hw_ldl_l/pw",        EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1415
  { "hw_ldl_l/pwv",        EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1416
  { "hw_ldl_l/v",        EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1417
  { "hw_ldl_l/w",        EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1418
  { "hw_ldl_l/wv",        EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1419
  { "hw_ldq",                EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1420
  { "hw_ldq",                EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1421
  { "hw_ldq",                EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1422
  { "hw_ldq/a",                EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1423
  { "hw_ldq/a",                EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1424
  { "hw_ldq/a",                EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1425
  { "hw_ldq/al",        EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1426
  { "hw_ldq/ar",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1427
  { "hw_ldq/av",        EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1428
  { "hw_ldq/avl",        EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1429
  { "hw_ldq/aw",        EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1430
  { "hw_ldq/awl",        EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1431
  { "hw_ldq/awv",        EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1432
  { "hw_ldq/awvl",        EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1433
  { "hw_ldq/l",                EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1434
  { "hw_ldq/p",                EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1435
  { "hw_ldq/p",                EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1436
  { "hw_ldq/p",                EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1437
  { "hw_ldq/pa",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1438
  { "hw_ldq/pa",        EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1439
  { "hw_ldq/pal",        EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1440
  { "hw_ldq/par",        EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1441
  { "hw_ldq/pav",        EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1442
  { "hw_ldq/pavl",        EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1443
  { "hw_ldq/paw",        EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1444
  { "hw_ldq/pawl",        EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1445
  { "hw_ldq/pawv",        EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1446
  { "hw_ldq/pawvl",        EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1447
  { "hw_ldq/pl",        EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1448
  { "hw_ldq/pr",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1449
  { "hw_ldq/pv",        EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1450
  { "hw_ldq/pvl",        EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1451
  { "hw_ldq/pw",        EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1452
  { "hw_ldq/pwl",        EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1453
  { "hw_ldq/pwv",        EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1454
  { "hw_ldq/pwvl",        EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1455
  { "hw_ldq/r",                EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1456
  { "hw_ldq/v",                EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1457
  { "hw_ldq/v",                EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1458
  { "hw_ldq/vl",        EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1459
  { "hw_ldq/w",                EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1460
  { "hw_ldq/w",                EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1461
  { "hw_ldq/wa",        EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1462
  { "hw_ldq/wl",        EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1463
  { "hw_ldq/wv",        EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1464
  { "hw_ldq/wvl",        EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1465
  { "hw_ldq_l",                EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1466
  { "hw_ldq_l/a",        EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1467
  { "hw_ldq_l/av",        EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1468
  { "hw_ldq_l/aw",        EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1469
  { "hw_ldq_l/awv",        EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1470
  { "hw_ldq_l/p",        EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1471
  { "hw_ldq_l/p",        EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1472
  { "hw_ldq_l/pa",        EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1473
  { "hw_ldq_l/pav",        EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1474
  { "hw_ldq_l/paw",        EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1475
  { "hw_ldq_l/pawv",        EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1476
  { "hw_ldq_l/pv",        EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1477
  { "hw_ldq_l/pw",        EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1478
  { "hw_ldq_l/pwv",        EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1479
  { "hw_ldq_l/v",        EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1480
  { "hw_ldq_l/w",        EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1481
  { "hw_ldq_l/wv",        EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1482
  { "hw_ld",                EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1483
  { "hw_ld",                EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1484
  { "hw_ld/a",                EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1485
  { "hw_ld/a",                EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1486
  { "hw_ld/al",                EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1487
  { "hw_ld/aq",                EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1488
  { "hw_ld/aq",                EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1489
  { "hw_ld/aql",        EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1490
  { "hw_ld/aqv",        EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1491
  { "hw_ld/aqvl",        EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1492
  { "hw_ld/ar",                EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1493
  { "hw_ld/arq",        EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1494
  { "hw_ld/av",                EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1495
  { "hw_ld/avl",        EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1496
  { "hw_ld/aw",                EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1497
  { "hw_ld/awl",        EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1498
  { "hw_ld/awq",        EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1499
  { "hw_ld/awql",        EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1500
  { "hw_ld/awqv",        EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1501
  { "hw_ld/awqvl",        EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1502
  { "hw_ld/awv",        EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1503
  { "hw_ld/awvl",        EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1504
  { "hw_ld/l",                EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1505
  { "hw_ld/p",                EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1506
  { "hw_ld/p",                EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1507
  { "hw_ld/pa",                EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1508
  { "hw_ld/pa",                EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1509
  { "hw_ld/pal",        EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1510
  { "hw_ld/paq",        EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1511
  { "hw_ld/paq",        EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1512
  { "hw_ld/paql",        EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1513
  { "hw_ld/paqv",        EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1514
  { "hw_ld/paqvl",        EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1515
  { "hw_ld/par",        EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1516
  { "hw_ld/parq",        EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1517
  { "hw_ld/pav",        EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1518
  { "hw_ld/pavl",        EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1519
  { "hw_ld/paw",        EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1520
  { "hw_ld/pawl",        EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1521
  { "hw_ld/pawq",        EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1522
  { "hw_ld/pawql",        EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1523
  { "hw_ld/pawqv",        EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1524
  { "hw_ld/pawqvl",        EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1525
  { "hw_ld/pawv",        EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1526
  { "hw_ld/pawvl",        EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1527
  { "hw_ld/pl",                EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1528
  { "hw_ld/pq",                EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1529
  { "hw_ld/pq",                EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1530
  { "hw_ld/pql",        EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1531
  { "hw_ld/pqv",        EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1532
  { "hw_ld/pqvl",        EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1533
  { "hw_ld/pr",                EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1534
  { "hw_ld/prq",        EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1535
  { "hw_ld/pv",                EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1536
  { "hw_ld/pvl",        EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1537
  { "hw_ld/pw",                EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1538
  { "hw_ld/pwl",        EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1539
  { "hw_ld/pwq",        EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1540
  { "hw_ld/pwql",        EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1541
  { "hw_ld/pwqv",        EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1542
  { "hw_ld/pwqvl",        EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1543
  { "hw_ld/pwv",        EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1544
  { "hw_ld/pwvl",        EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1545
  { "hw_ld/q",                EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1546
  { "hw_ld/q",                EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1547
  { "hw_ld/ql",                EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1548
  { "hw_ld/qv",                EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1549
  { "hw_ld/qvl",        EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1550
  { "hw_ld/r",                EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1551
  { "hw_ld/rq",                EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1552
  { "hw_ld/v",                EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1553
  { "hw_ld/vl",                EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1554
  { "hw_ld/w",                EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1555
  { "hw_ld/wl",                EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1556
  { "hw_ld/wq",                EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1557
  { "hw_ld/wql",        EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1558
  { "hw_ld/wqv",        EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1559
  { "hw_ld/wqvl",        EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1560
  { "hw_ld/wv",                EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1561
  { "hw_ld/wvl",        EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1562
  { "pal1b",                PCD(0x1B), BASE, ARG_PCD },
1563

    
1564
  { "sextb",                OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1565
  { "sextw",                OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1566
  { "ctpop",                OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1567
  { "perr",                OPR(0x1C, 0x31), MAX, ARG_OPR },
1568
  { "ctlz",                OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1569
  { "cttz",                OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1570
  { "unpkbw",                OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1571
  { "unpkbl",                OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1572
  { "pkwb",                OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1573
  { "pklb",                OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1574
  { "minsb8",                 OPR(0x1C, 0x38), MAX, ARG_OPR },
1575
  { "minsb8",                 OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1576
  { "minsw4",                 OPR(0x1C, 0x39), MAX, ARG_OPR },
1577
  { "minsw4",                 OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1578
  { "minub8",                 OPR(0x1C, 0x3A), MAX, ARG_OPR },
1579
  { "minub8",                 OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1580
  { "minuw4",                 OPR(0x1C, 0x3B), MAX, ARG_OPR },
1581
  { "minuw4",                 OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1582
  { "maxub8",                OPR(0x1C, 0x3C), MAX, ARG_OPR },
1583
  { "maxub8",                OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1584
  { "maxuw4",                OPR(0x1C, 0x3D), MAX, ARG_OPR },
1585
  { "maxuw4",                OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1586
  { "maxsb8",                OPR(0x1C, 0x3E), MAX, ARG_OPR },
1587
  { "maxsb8",                OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1588
  { "maxsw4",                OPR(0x1C, 0x3F), MAX, ARG_OPR },
1589
  { "maxsw4",                OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1590
  { "ftoit",                FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1591
  { "ftois",                FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1592

    
1593
  { "hw_mtpr",                OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1594
  { "hw_mtpr",                OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1595
  { "hw_mtpr",                OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1596
  { "hw_mtpr/i",         OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1597
  { "hw_mtpr/a",         OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1598
  { "hw_mtpr/ai",        OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1599
  { "hw_mtpr/p",         OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1600
  { "hw_mtpr/pi",        OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1601
  { "hw_mtpr/pa",        OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1602
  { "hw_mtpr/pai",        OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1603
  { "pal1d",                PCD(0x1D), BASE, ARG_PCD },
1604

    
1605
  { "hw_rei",                SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1606
  { "hw_rei_stall",        SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1607
  { "hw_jmp",                 EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1608
  { "hw_jsr",                 EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1609
  { "hw_ret",                 EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1610
  { "hw_jcr",                 EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1611
  { "hw_coroutine",        EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1612
  { "hw_jmp/stall",        EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1613
  { "hw_jsr/stall",         EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1614
  { "hw_ret/stall",        EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1615
  { "hw_jcr/stall",         EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1616
  { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1617
  { "pal1e",                PCD(0x1E), BASE, ARG_PCD },
1618

    
1619
  { "hw_stl",                EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1620
  { "hw_stl",                EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1621
  { "hw_stl",                EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1622
  { "hw_stl/a",                EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1623
  { "hw_stl/a",                EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1624
  { "hw_stl/a",                EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1625
  { "hw_stl/ac",        EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1626
  { "hw_stl/ar",        EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1627
  { "hw_stl/av",        EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1628
  { "hw_stl/avc",        EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1629
  { "hw_stl/c",                EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1630
  { "hw_stl/p",                EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1631
  { "hw_stl/p",                EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1632
  { "hw_stl/p",                EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1633
  { "hw_stl/pa",        EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1634
  { "hw_stl/pa",        EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1635
  { "hw_stl/pac",        EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1636
  { "hw_stl/pav",        EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1637
  { "hw_stl/pavc",        EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1638
  { "hw_stl/pc",        EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1639
  { "hw_stl/pr",        EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1640
  { "hw_stl/pv",        EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1641
  { "hw_stl/pvc",        EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1642
  { "hw_stl/r",                EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1643
  { "hw_stl/v",                EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1644
  { "hw_stl/vc",        EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1645
  { "hw_stl_c",                EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1646
  { "hw_stl_c/a",        EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1647
  { "hw_stl_c/av",        EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1648
  { "hw_stl_c/p",        EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1649
  { "hw_stl_c/p",        EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1650
  { "hw_stl_c/pa",        EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1651
  { "hw_stl_c/pav",        EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1652
  { "hw_stl_c/pv",        EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1653
  { "hw_stl_c/v",        EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1654
  { "hw_stq",                EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1655
  { "hw_stq",                EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1656
  { "hw_stq",                EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1657
  { "hw_stq/a",                EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1658
  { "hw_stq/a",                EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1659
  { "hw_stq/a",                EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1660
  { "hw_stq/ac",        EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1661
  { "hw_stq/ar",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1662
  { "hw_stq/av",        EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1663
  { "hw_stq/avc",        EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1664
  { "hw_stq/c",                EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1665
  { "hw_stq/p",                EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1666
  { "hw_stq/p",                EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1667
  { "hw_stq/p",                EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1668
  { "hw_stq/pa",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1669
  { "hw_stq/pa",        EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1670
  { "hw_stq/pac",        EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1671
  { "hw_stq/par",        EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1672
  { "hw_stq/par",        EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1673
  { "hw_stq/pav",        EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1674
  { "hw_stq/pavc",        EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1675
  { "hw_stq/pc",        EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1676
  { "hw_stq/pr",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1677
  { "hw_stq/pv",        EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1678
  { "hw_stq/pvc",        EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1679
  { "hw_stq/r",                EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1680
  { "hw_stq/v",                EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1681
  { "hw_stq/vc",        EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1682
  { "hw_stq_c",                EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1683
  { "hw_stq_c/a",        EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1684
  { "hw_stq_c/av",        EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1685
  { "hw_stq_c/p",        EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1686
  { "hw_stq_c/p",        EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1687
  { "hw_stq_c/pa",        EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1688
  { "hw_stq_c/pav",        EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1689
  { "hw_stq_c/pv",        EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1690
  { "hw_stq_c/v",        EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1691
  { "hw_st",                EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1692
  { "hw_st",                EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1693
  { "hw_st/a",                EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1694
  { "hw_st/a",                EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1695
  { "hw_st/ac",                EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1696
  { "hw_st/aq",                EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1697
  { "hw_st/aq",                EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1698
  { "hw_st/aqc",        EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1699
  { "hw_st/aqv",        EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1700
  { "hw_st/aqvc",        EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1701
  { "hw_st/ar",                EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1702
  { "hw_st/arq",        EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1703
  { "hw_st/av",                EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1704
  { "hw_st/avc",        EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1705
  { "hw_st/c",                EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1706
  { "hw_st/p",                EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1707
  { "hw_st/p",                EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1708
  { "hw_st/pa",                EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1709
  { "hw_st/pa",                EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1710
  { "hw_st/pac",        EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1711
  { "hw_st/paq",        EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1712
  { "hw_st/paq",        EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1713
  { "hw_st/paqc",        EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1714
  { "hw_st/paqv",        EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1715
  { "hw_st/paqvc",        EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1716
  { "hw_st/par",        EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1717
  { "hw_st/parq",        EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1718
  { "hw_st/pav",        EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1719
  { "hw_st/pavc",        EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1720
  { "hw_st/pc",                EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1721
  { "hw_st/pq",                EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1722
  { "hw_st/pq",                EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1723
  { "hw_st/pqc",        EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1724
  { "hw_st/pqv",        EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1725
  { "hw_st/pqvc",        EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1726
  { "hw_st/pr",                EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1727
  { "hw_st/prq",        EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1728
  { "hw_st/pv",                EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1729
  { "hw_st/pvc",        EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1730
  { "hw_st/q",                EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1731
  { "hw_st/q",                EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1732
  { "hw_st/qc",                EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1733
  { "hw_st/qv",                EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1734
  { "hw_st/qvc",        EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1735
  { "hw_st/r",                EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1736
  { "hw_st/v",                EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1737
  { "hw_st/vc",                EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1738
  { "pal1f",                PCD(0x1F), BASE, ARG_PCD },
1739

    
1740
  { "ldf",                MEM(0x20), BASE, ARG_FMEM },
1741
  { "ldg",                MEM(0x21), BASE, ARG_FMEM },
1742
  { "lds",                MEM(0x22), BASE, ARG_FMEM },
1743
  { "ldt",                MEM(0x23), BASE, ARG_FMEM },
1744
  { "stf",                MEM(0x24), BASE, ARG_FMEM },
1745
  { "stg",                MEM(0x25), BASE, ARG_FMEM },
1746
  { "sts",                MEM(0x26), BASE, ARG_FMEM },
1747
  { "stt",                MEM(0x27), BASE, ARG_FMEM },
1748

    
1749
  { "ldl",                MEM(0x28), BASE, ARG_MEM },
1750
  { "ldq",                MEM(0x29), BASE, ARG_MEM },
1751
  { "ldl_l",                MEM(0x2A), BASE, ARG_MEM },
1752
  { "ldq_l",                MEM(0x2B), BASE, ARG_MEM },
1753
  { "stl",                MEM(0x2C), BASE, ARG_MEM },
1754
  { "stq",                MEM(0x2D), BASE, ARG_MEM },
1755
  { "stl_c",                MEM(0x2E), BASE, ARG_MEM },
1756
  { "stq_c",                MEM(0x2F), BASE, ARG_MEM },
1757

    
1758
  { "br",                BRA(0x30), BASE, { ZA, BDISP } },        /* pseudo */
1759
  { "br",                BRA(0x30), BASE, ARG_BRA },
1760
  { "fbeq",                BRA(0x31), BASE, ARG_FBRA },
1761
  { "fblt",                BRA(0x32), BASE, ARG_FBRA },
1762
  { "fble",                BRA(0x33), BASE, ARG_FBRA },
1763
  { "bsr",                BRA(0x34), BASE, ARG_BRA },
1764
  { "fbne",                BRA(0x35), BASE, ARG_FBRA },
1765
  { "fbge",                BRA(0x36), BASE, ARG_FBRA },
1766
  { "fbgt",                BRA(0x37), BASE, ARG_FBRA },
1767
  { "blbc",                BRA(0x38), BASE, ARG_BRA },
1768
  { "beq",                BRA(0x39), BASE, ARG_BRA },
1769
  { "blt",                BRA(0x3A), BASE, ARG_BRA },
1770
  { "ble",                BRA(0x3B), BASE, ARG_BRA },
1771
  { "blbs",                BRA(0x3C), BASE, ARG_BRA },
1772
  { "bne",                BRA(0x3D), BASE, ARG_BRA },
1773
  { "bge",                BRA(0x3E), BASE, ARG_BRA },
1774
  { "bgt",                BRA(0x3F), BASE, ARG_BRA },
1775
};
1776

    
1777
const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
1778

    
1779
/* OSF register names.  */
1780

    
1781
static const char * const osf_regnames[64] = {
1782
  "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
1783
  "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
1784
  "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
1785
  "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
1786
  "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1787
  "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1788
  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1789
  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
1790
};
1791

    
1792
/* VMS register names.  */
1793

    
1794
static const char * const vms_regnames[64] = {
1795
  "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
1796
  "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
1797
  "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
1798
  "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
1799
  "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
1800
  "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
1801
  "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
1802
  "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
1803
};
1804

    
1805
/* Disassemble Alpha instructions.  */
1806

    
1807
int
1808
print_insn_alpha (memaddr, info)
1809
     bfd_vma memaddr;
1810
     struct disassemble_info *info;
1811
{
1812
  static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
1813
  const char * const * regnames;
1814
  const struct alpha_opcode *opcode, *opcode_end;
1815
  const unsigned char *opindex;
1816
  unsigned insn, op, isa_mask;
1817
  int need_comma;
1818

    
1819
  /* Initialize the majorop table the first time through */
1820
  if (!opcode_index[0])
1821
    {
1822
      opcode = alpha_opcodes;
1823
      opcode_end = opcode + alpha_num_opcodes;
1824

    
1825
      for (op = 0; op < AXP_NOPS; ++op)
1826
        {
1827
          opcode_index[op] = opcode;
1828
          while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
1829
            ++opcode;
1830
        }
1831
      opcode_index[op] = opcode;
1832
    }
1833

    
1834
  if (info->flavour == bfd_target_evax_flavour)
1835
    regnames = vms_regnames;
1836
  else
1837
    regnames = osf_regnames;
1838

    
1839
  isa_mask = AXP_OPCODE_NOPAL;
1840
  switch (info->mach)
1841
    {
1842
    case bfd_mach_alpha_ev4:
1843
      isa_mask |= AXP_OPCODE_EV4;
1844
      break;
1845
    case bfd_mach_alpha_ev5:
1846
      isa_mask |= AXP_OPCODE_EV5;
1847
      break;
1848
    case bfd_mach_alpha_ev6:
1849
      isa_mask |= AXP_OPCODE_EV6;
1850
      break;
1851
    }
1852

    
1853
  /* Read the insn into a host word */
1854
  {
1855
    bfd_byte buffer[4];
1856
    int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
1857
    if (status != 0)
1858
      {
1859
        (*info->memory_error_func) (status, memaddr, info);
1860
        return -1;
1861
      }
1862
    insn = bfd_getl32 (buffer);
1863
  }
1864

    
1865
  /* Get the major opcode of the instruction.  */
1866
  op = AXP_OP (insn);
1867

    
1868
  /* Find the first match in the opcode table.  */
1869
  opcode_end = opcode_index[op + 1];
1870
  for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
1871
    {
1872
      if ((insn ^ opcode->opcode) & opcode->mask)
1873
        continue;
1874

    
1875
      if (!(opcode->flags & isa_mask))
1876
        continue;
1877

    
1878
      /* Make two passes over the operands.  First see if any of them
1879
         have extraction functions, and, if they do, make sure the
1880
         instruction is valid.  */
1881
      {
1882
        int invalid = 0;
1883
        for (opindex = opcode->operands; *opindex != 0; opindex++)
1884
          {
1885
            const struct alpha_operand *operand = alpha_operands + *opindex;
1886
            if (operand->extract)
1887
              (*operand->extract) (insn, &invalid);
1888
          }
1889
        if (invalid)
1890
          continue;
1891
      }
1892

    
1893
      /* The instruction is valid.  */
1894
      goto found;
1895
    }
1896

    
1897
  /* No instruction found */
1898
  (*info->fprintf_func) (info->stream, ".long %#08x", insn);
1899

    
1900
  return 4;
1901

    
1902
found:
1903
  (*info->fprintf_func) (info->stream, "%s", opcode->name);
1904
  if (opcode->operands[0] != 0)
1905
    (*info->fprintf_func) (info->stream, "\t");
1906

    
1907
  /* Now extract and print the operands.  */
1908
  need_comma = 0;
1909
  for (opindex = opcode->operands; *opindex != 0; opindex++)
1910
    {
1911
      const struct alpha_operand *operand = alpha_operands + *opindex;
1912
      int value;
1913

    
1914
      /* Operands that are marked FAKE are simply ignored.  We
1915
         already made sure that the extract function considered
1916
         the instruction to be valid.  */
1917
      if ((operand->flags & AXP_OPERAND_FAKE) != 0)
1918
        continue;
1919

    
1920
      /* Extract the value from the instruction.  */
1921
      if (operand->extract)
1922
        value = (*operand->extract) (insn, (int *) NULL);
1923
      else
1924
        {
1925
          value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
1926
          if (operand->flags & AXP_OPERAND_SIGNED)
1927
            {
1928
              int signbit = 1 << (operand->bits - 1);
1929
              value = (value ^ signbit) - signbit;
1930
            }
1931
        }
1932

    
1933
      if (need_comma &&
1934
          ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
1935
           != AXP_OPERAND_PARENS))
1936
        {
1937
          (*info->fprintf_func) (info->stream, ",");
1938
        }
1939
      if (operand->flags & AXP_OPERAND_PARENS)
1940
        (*info->fprintf_func) (info->stream, "(");
1941

    
1942
      /* Print the operand as directed by the flags.  */
1943
      if (operand->flags & AXP_OPERAND_IR)
1944
        (*info->fprintf_func) (info->stream, "%s", regnames[value]);
1945
      else if (operand->flags & AXP_OPERAND_FPR)
1946
        (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
1947
      else if (operand->flags & AXP_OPERAND_RELATIVE)
1948
        (*info->print_address_func) (memaddr + 4 + value, info);
1949
      else if (operand->flags & AXP_OPERAND_SIGNED)
1950
        (*info->fprintf_func) (info->stream, "%d", value);
1951
      else
1952
        (*info->fprintf_func) (info->stream, "%#x", value);
1953

    
1954
      if (operand->flags & AXP_OPERAND_PARENS)
1955
        (*info->fprintf_func) (info->stream, ")");
1956
      need_comma = 1;
1957
    }
1958

    
1959
  return 4;
1960
}