Revision 486579de hw/sh7750.c
b/hw/sh7750.c | ||
---|---|---|
60 | 60 |
uint16_t periph_portdirb; /* Direction seen from the peripherals */ |
61 | 61 |
sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ |
62 | 62 |
|
63 |
uint16_t icr; |
|
64 | 63 |
/* Cache */ |
65 | 64 |
uint32_t ccr; |
66 | 65 |
|
... | ... | |
222 | 221 |
return porta_lines(s); |
223 | 222 |
case SH7750_PDTRB_A7: |
224 | 223 |
return portb_lines(s); |
225 |
case 0x1fd00000: |
|
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return s->icr; |
|
227 | 224 |
default: |
228 | 225 |
error_access("word read", addr); |
229 | 226 |
assert(0); |
... | ... | |
328 | 325 |
assert(0); |
329 | 326 |
} |
330 | 327 |
return; |
331 |
case 0x1fd00000: |
|
332 |
s->icr = mem_value; |
|
333 |
return; |
|
334 | 328 |
default: |
335 | 329 |
error_access("word write", addr); |
336 | 330 |
assert(0); |
... | ... | |
687 | 681 |
sh7750_io_memory = cpu_register_io_memory(0, |
688 | 682 |
sh7750_mem_read, |
689 | 683 |
sh7750_mem_write, s); |
690 |
cpu_register_physical_memory_offset(0x1c000000, 0x04000000, |
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sh7750_io_memory, 0x1c000000); |
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cpu_register_physical_memory_offset(0x1f000000, 0x1000, |
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sh7750_io_memory, 0x1f000000); |
|
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cpu_register_physical_memory_offset(0x1f800000, 0x1000, |
|
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sh7750_io_memory, 0x1f800000); |
|
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cpu_register_physical_memory_offset(0x1fc00000, 0x1000, |
|
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sh7750_io_memory, 0x1fc00000); |
|
692 | 690 |
|
693 | 691 |
sh7750_mm_cache_and_tlb = cpu_register_io_memory(0, |
694 | 692 |
sh7750_mmct_read, |
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