Revision 486579de hw/sm501.c
b/hw/sm501.c | ||
---|---|---|
638 | 638 |
&sm501_system_config_write, |
639 | 639 |
}; |
640 | 640 |
|
641 |
static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) |
|
642 |
{ |
|
643 |
SM501State * s = (SM501State *)opaque; |
|
644 |
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); |
|
645 |
|
|
646 |
/* TODO : consider BYTE/WORD access */ |
|
647 |
/* TODO : consider endian */ |
|
648 |
|
|
649 |
assert(0 <= addr && addr < 0x400 * 3); |
|
650 |
return *(uint32_t*)&s->dc_palette[addr]; |
|
651 |
} |
|
652 |
|
|
653 |
static void sm501_palette_write(void *opaque, |
|
654 |
target_phys_addr_t addr, uint32_t value) |
|
655 |
{ |
|
656 |
SM501State * s = (SM501State *)opaque; |
|
657 |
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", |
|
658 |
(int)addr, value); |
|
659 |
|
|
660 |
/* TODO : consider BYTE/WORD access */ |
|
661 |
/* TODO : consider endian */ |
|
662 |
|
|
663 |
assert(0 <= addr && addr < 0x400 * 3); |
|
664 |
*(uint32_t*)&s->dc_palette[addr] = value; |
|
665 |
} |
|
666 |
|
|
641 | 667 |
static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr) |
642 | 668 |
{ |
643 | 669 |
SM501State * s = (SM501State *)opaque; |
... | ... | |
719 | 745 |
ret = s->dc_crt_hwc_addr; |
720 | 746 |
break; |
721 | 747 |
|
748 |
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: |
|
749 |
ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); |
|
750 |
break; |
|
751 |
|
|
722 | 752 |
default: |
723 | 753 |
printf("sm501 disp ctrl : not implemented register read." |
724 | 754 |
" addr=%x\n", (int)addr); |
... | ... | |
823 | 853 |
s->dc_crt_hwc_addr = value & 0x0000FFFF; |
824 | 854 |
break; |
825 | 855 |
|
856 |
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: |
|
857 |
sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); |
|
858 |
break; |
|
859 |
|
|
826 | 860 |
default: |
827 | 861 |
printf("sm501 disp ctrl : not implemented register write." |
828 | 862 |
" addr=%x, val=%x\n", (int)addr, value); |
... | ... | |
842 | 876 |
&sm501_disp_ctrl_write, |
843 | 877 |
}; |
844 | 878 |
|
845 |
static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) |
|
846 |
{ |
|
847 |
SM501State * s = (SM501State *)opaque; |
|
848 |
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); |
|
849 |
|
|
850 |
/* TODO : consider BYTE/WORD access */ |
|
851 |
/* TODO : consider endian */ |
|
852 |
|
|
853 |
assert(0 <= addr && addr < 0x400 * 3); |
|
854 |
return *(uint32_t*)&s->dc_palette[addr]; |
|
855 |
} |
|
856 |
|
|
857 |
static void sm501_palette_write(void *opaque, |
|
858 |
target_phys_addr_t addr, uint32_t value) |
|
859 |
{ |
|
860 |
SM501State * s = (SM501State *)opaque; |
|
861 |
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", |
|
862 |
(int)addr, value); |
|
863 |
|
|
864 |
/* TODO : consider BYTE/WORD access */ |
|
865 |
/* TODO : consider endian */ |
|
866 |
|
|
867 |
assert(0 <= addr && addr < 0x400 * 3); |
|
868 |
*(uint32_t*)&s->dc_palette[addr] = value; |
|
869 |
} |
|
870 |
|
|
871 |
static CPUReadMemoryFunc *sm501_palette_readfn[] = { |
|
872 |
&sm501_palette_read, |
|
873 |
&sm501_palette_read, |
|
874 |
&sm501_palette_read, |
|
875 |
}; |
|
876 |
|
|
877 |
static CPUWriteMemoryFunc *sm501_palette_writefn[] = { |
|
878 |
&sm501_palette_write, |
|
879 |
&sm501_palette_write, |
|
880 |
&sm501_palette_write, |
|
881 |
}; |
|
882 |
|
|
883 |
|
|
884 | 879 |
/* draw line functions for all console modes */ |
885 | 880 |
|
886 | 881 |
#include "pixel_ops.h" |
... | ... | |
1070 | 1065 |
SM501State * s; |
1071 | 1066 |
int sm501_system_config_index; |
1072 | 1067 |
int sm501_disp_ctrl_index; |
1073 |
int sm501_palette_index; |
|
1074 | 1068 |
|
1075 | 1069 |
/* allocate management data region */ |
1076 | 1070 |
s = (SM501State *)qemu_mallocz(sizeof(SM501State)); |
... | ... | |
1098 | 1092 |
sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn, |
1099 | 1093 |
sm501_disp_ctrl_writefn, s); |
1100 | 1094 |
cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC, |
1101 |
0x400, sm501_disp_ctrl_index); |
|
1102 |
|
|
1103 |
sm501_palette_index = cpu_register_io_memory(0, sm501_palette_readfn, |
|
1104 |
sm501_palette_writefn, s); |
|
1105 |
cpu_register_physical_memory(base + MMIO_BASE_OFFSET |
|
1106 |
+ SM501_DC + SM501_DC_PANEL_PALETTE, |
|
1107 |
0x400 * 3, sm501_palette_index); |
|
1095 |
0x1000, sm501_disp_ctrl_index); |
|
1108 | 1096 |
|
1109 | 1097 |
/* bridge to serial emulation module */ |
1110 | 1098 |
if (chr) |
Also available in: Unified diff