Revision 487414f1 hw/ppc405_uc.c
b/hw/ppc405_uc.c | ||
---|---|---|
169 | 169 |
ppc4xx_plb_t *plb; |
170 | 170 |
|
171 | 171 |
plb = qemu_mallocz(sizeof(ppc4xx_plb_t)); |
172 |
if (plb != NULL) { |
|
173 |
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
|
174 |
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
|
175 |
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
|
176 |
ppc4xx_plb_reset(plb); |
|
177 |
qemu_register_reset(ppc4xx_plb_reset, plb); |
|
178 |
} |
|
172 |
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
|
173 |
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
|
174 |
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
|
175 |
ppc4xx_plb_reset(plb); |
|
176 |
qemu_register_reset(ppc4xx_plb_reset, plb); |
|
179 | 177 |
} |
180 | 178 |
|
181 | 179 |
/*****************************************************************************/ |
... | ... | |
248 | 246 |
ppc4xx_pob_t *pob; |
249 | 247 |
|
250 | 248 |
pob = qemu_mallocz(sizeof(ppc4xx_pob_t)); |
251 |
if (pob != NULL) { |
|
252 |
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
|
253 |
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
|
254 |
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
|
255 |
qemu_register_reset(ppc4xx_pob_reset, pob); |
|
256 |
ppc4xx_pob_reset(env); |
|
257 |
} |
|
249 |
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
|
250 |
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
|
251 |
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
|
252 |
qemu_register_reset(ppc4xx_pob_reset, pob); |
|
253 |
ppc4xx_pob_reset(env); |
|
258 | 254 |
} |
259 | 255 |
|
260 | 256 |
/*****************************************************************************/ |
... | ... | |
384 | 380 |
ppc4xx_opba_t *opba; |
385 | 381 |
|
386 | 382 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t)); |
387 |
if (opba != NULL) { |
|
388 |
opba->base = offset; |
|
383 |
opba->base = offset; |
|
389 | 384 |
#ifdef DEBUG_OPBA |
390 |
printf("%s: offset " PADDRX "\n", __func__, offset);
|
|
385 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
|
391 | 386 |
#endif |
392 |
ppc4xx_mmio_register(env, mmio, offset, 0x002, |
|
393 |
opba_read, opba_write, opba); |
|
394 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
|
395 |
ppc4xx_opba_reset(opba); |
|
396 |
} |
|
387 |
ppc4xx_mmio_register(env, mmio, offset, 0x002, |
|
388 |
opba_read, opba_write, opba); |
|
389 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
|
390 |
ppc4xx_opba_reset(opba); |
|
397 | 391 |
} |
398 | 392 |
|
399 | 393 |
/*****************************************************************************/ |
... | ... | |
585 | 579 |
ppc4xx_ebc_t *ebc; |
586 | 580 |
|
587 | 581 |
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t)); |
588 |
if (ebc != NULL) { |
|
589 |
ebc_reset(ebc); |
|
590 |
qemu_register_reset(&ebc_reset, ebc); |
|
591 |
ppc_dcr_register(env, EBC0_CFGADDR, |
|
592 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
|
593 |
ppc_dcr_register(env, EBC0_CFGDATA, |
|
594 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
|
595 |
} |
|
582 |
ebc_reset(ebc); |
|
583 |
qemu_register_reset(&ebc_reset, ebc); |
|
584 |
ppc_dcr_register(env, EBC0_CFGADDR, |
|
585 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
|
586 |
ppc_dcr_register(env, EBC0_CFGDATA, |
|
587 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
|
596 | 588 |
} |
597 | 589 |
|
598 | 590 |
/*****************************************************************************/ |
... | ... | |
678 | 670 |
ppc405_dma_t *dma; |
679 | 671 |
|
680 | 672 |
dma = qemu_mallocz(sizeof(ppc405_dma_t)); |
681 |
if (dma != NULL) { |
|
682 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
|
683 |
ppc405_dma_reset(dma); |
|
684 |
qemu_register_reset(&ppc405_dma_reset, dma); |
|
685 |
ppc_dcr_register(env, DMA0_CR0, |
|
686 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
687 |
ppc_dcr_register(env, DMA0_CT0, |
|
688 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
689 |
ppc_dcr_register(env, DMA0_DA0, |
|
690 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
691 |
ppc_dcr_register(env, DMA0_SA0, |
|
692 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
693 |
ppc_dcr_register(env, DMA0_SG0, |
|
694 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
695 |
ppc_dcr_register(env, DMA0_CR1, |
|
696 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
697 |
ppc_dcr_register(env, DMA0_CT1, |
|
698 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
699 |
ppc_dcr_register(env, DMA0_DA1, |
|
700 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
701 |
ppc_dcr_register(env, DMA0_SA1, |
|
702 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
703 |
ppc_dcr_register(env, DMA0_SG1, |
|
704 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
705 |
ppc_dcr_register(env, DMA0_CR2, |
|
706 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
707 |
ppc_dcr_register(env, DMA0_CT2, |
|
708 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
709 |
ppc_dcr_register(env, DMA0_DA2, |
|
710 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
711 |
ppc_dcr_register(env, DMA0_SA2, |
|
712 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
713 |
ppc_dcr_register(env, DMA0_SG2, |
|
714 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
715 |
ppc_dcr_register(env, DMA0_CR3, |
|
716 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
717 |
ppc_dcr_register(env, DMA0_CT3, |
|
718 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
719 |
ppc_dcr_register(env, DMA0_DA3, |
|
720 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
721 |
ppc_dcr_register(env, DMA0_SA3, |
|
722 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
723 |
ppc_dcr_register(env, DMA0_SG3, |
|
724 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
725 |
ppc_dcr_register(env, DMA0_SR, |
|
726 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
727 |
ppc_dcr_register(env, DMA0_SGC, |
|
728 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
729 |
ppc_dcr_register(env, DMA0_SLP, |
|
730 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
731 |
ppc_dcr_register(env, DMA0_POL, |
|
732 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
733 |
} |
|
673 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
|
674 |
ppc405_dma_reset(dma); |
|
675 |
qemu_register_reset(&ppc405_dma_reset, dma); |
|
676 |
ppc_dcr_register(env, DMA0_CR0, |
|
677 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
678 |
ppc_dcr_register(env, DMA0_CT0, |
|
679 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
680 |
ppc_dcr_register(env, DMA0_DA0, |
|
681 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
682 |
ppc_dcr_register(env, DMA0_SA0, |
|
683 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
684 |
ppc_dcr_register(env, DMA0_SG0, |
|
685 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
686 |
ppc_dcr_register(env, DMA0_CR1, |
|
687 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
688 |
ppc_dcr_register(env, DMA0_CT1, |
|
689 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
690 |
ppc_dcr_register(env, DMA0_DA1, |
|
691 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
692 |
ppc_dcr_register(env, DMA0_SA1, |
|
693 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
694 |
ppc_dcr_register(env, DMA0_SG1, |
|
695 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
696 |
ppc_dcr_register(env, DMA0_CR2, |
|
697 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
698 |
ppc_dcr_register(env, DMA0_CT2, |
|
699 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
700 |
ppc_dcr_register(env, DMA0_DA2, |
|
701 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
702 |
ppc_dcr_register(env, DMA0_SA2, |
|
703 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
704 |
ppc_dcr_register(env, DMA0_SG2, |
|
705 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
706 |
ppc_dcr_register(env, DMA0_CR3, |
|
707 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
708 |
ppc_dcr_register(env, DMA0_CT3, |
|
709 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
710 |
ppc_dcr_register(env, DMA0_DA3, |
|
711 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
712 |
ppc_dcr_register(env, DMA0_SA3, |
|
713 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
714 |
ppc_dcr_register(env, DMA0_SG3, |
|
715 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
716 |
ppc_dcr_register(env, DMA0_SR, |
|
717 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
718 |
ppc_dcr_register(env, DMA0_SGC, |
|
719 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
720 |
ppc_dcr_register(env, DMA0_SLP, |
|
721 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
722 |
ppc_dcr_register(env, DMA0_POL, |
|
723 |
dma, &dcr_read_dma, &dcr_write_dma); |
|
734 | 724 |
} |
735 | 725 |
|
736 | 726 |
/*****************************************************************************/ |
... | ... | |
845 | 835 |
ppc405_gpio_t *gpio; |
846 | 836 |
|
847 | 837 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t)); |
848 |
if (gpio != NULL) { |
|
849 |
gpio->base = offset; |
|
850 |
ppc405_gpio_reset(gpio); |
|
851 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
|
838 |
gpio->base = offset; |
|
839 |
ppc405_gpio_reset(gpio); |
|
840 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
|
852 | 841 |
#ifdef DEBUG_GPIO |
853 |
printf("%s: offset " PADDRX "\n", __func__, offset);
|
|
842 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
|
854 | 843 |
#endif |
855 |
ppc4xx_mmio_register(env, mmio, offset, 0x038, |
|
856 |
ppc405_gpio_read, ppc405_gpio_write, gpio); |
|
857 |
} |
|
844 |
ppc4xx_mmio_register(env, mmio, offset, 0x038, |
|
845 |
ppc405_gpio_read, ppc405_gpio_write, gpio); |
|
858 | 846 |
} |
859 | 847 |
|
860 | 848 |
/*****************************************************************************/ |
... | ... | |
1038 | 1026 |
ppc405_ocm_t *ocm; |
1039 | 1027 |
|
1040 | 1028 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); |
1041 |
if (ocm != NULL) { |
|
1042 |
ocm->offset = offset; |
|
1043 |
ocm_reset(ocm); |
|
1044 |
qemu_register_reset(&ocm_reset, ocm); |
|
1045 |
ppc_dcr_register(env, OCM0_ISARC, |
|
1046 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1047 |
ppc_dcr_register(env, OCM0_ISACNTL, |
|
1048 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1049 |
ppc_dcr_register(env, OCM0_DSARC, |
|
1050 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1051 |
ppc_dcr_register(env, OCM0_DSACNTL, |
|
1052 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1053 |
} |
|
1029 |
ocm->offset = offset; |
|
1030 |
ocm_reset(ocm); |
|
1031 |
qemu_register_reset(&ocm_reset, ocm); |
|
1032 |
ppc_dcr_register(env, OCM0_ISARC, |
|
1033 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1034 |
ppc_dcr_register(env, OCM0_ISACNTL, |
|
1035 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1036 |
ppc_dcr_register(env, OCM0_DSARC, |
|
1037 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1038 |
ppc_dcr_register(env, OCM0_DSACNTL, |
|
1039 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
|
1054 | 1040 |
} |
1055 | 1041 |
|
1056 | 1042 |
/*****************************************************************************/ |
... | ... | |
1286 | 1272 |
ppc4xx_i2c_t *i2c; |
1287 | 1273 |
|
1288 | 1274 |
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t)); |
1289 |
if (i2c != NULL) { |
|
1290 |
i2c->base = offset; |
|
1291 |
i2c->irq = irq; |
|
1292 |
ppc4xx_i2c_reset(i2c); |
|
1275 |
i2c->base = offset; |
|
1276 |
i2c->irq = irq; |
|
1277 |
ppc4xx_i2c_reset(i2c); |
|
1293 | 1278 |
#ifdef DEBUG_I2C |
1294 |
printf("%s: offset " PADDRX "\n", __func__, offset);
|
|
1279 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
|
1295 | 1280 |
#endif |
1296 |
ppc4xx_mmio_register(env, mmio, offset, 0x011, |
|
1297 |
i2c_read, i2c_write, i2c); |
|
1298 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
|
1299 |
} |
|
1281 |
ppc4xx_mmio_register(env, mmio, offset, 0x011, |
|
1282 |
i2c_read, i2c_write, i2c); |
|
1283 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
|
1300 | 1284 |
} |
1301 | 1285 |
|
1302 | 1286 |
/*****************************************************************************/ |
... | ... | |
1568 | 1552 |
int i; |
1569 | 1553 |
|
1570 | 1554 |
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t)); |
1571 |
if (gpt != NULL) { |
|
1572 |
gpt->base = offset; |
|
1573 |
for (i = 0; i < 5; i++) |
|
1574 |
gpt->irqs[i] = irqs[i]; |
|
1575 |
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
|
1576 |
ppc4xx_gpt_reset(gpt); |
|
1555 |
gpt->base = offset; |
|
1556 |
for (i = 0; i < 5; i++) |
|
1557 |
gpt->irqs[i] = irqs[i]; |
|
1558 |
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
|
1559 |
ppc4xx_gpt_reset(gpt); |
|
1577 | 1560 |
#ifdef DEBUG_GPT |
1578 |
printf("%s: offset " PADDRX "\n", __func__, offset);
|
|
1561 |
printf("%s: offset " PADDRX "\n", __func__, offset); |
|
1579 | 1562 |
#endif |
1580 |
ppc4xx_mmio_register(env, mmio, offset, 0x0D4, |
|
1581 |
gpt_read, gpt_write, gpt); |
|
1582 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
|
1583 |
} |
|
1563 |
ppc4xx_mmio_register(env, mmio, offset, 0x0D4, |
|
1564 |
gpt_read, gpt_write, gpt); |
|
1565 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
|
1584 | 1566 |
} |
1585 | 1567 |
|
1586 | 1568 |
/*****************************************************************************/ |
... | ... | |
1802 | 1784 |
int i; |
1803 | 1785 |
|
1804 | 1786 |
mal = qemu_mallocz(sizeof(ppc40x_mal_t)); |
1805 |
if (mal != NULL) { |
|
1806 |
for (i = 0; i < 4; i++) |
|
1807 |
mal->irqs[i] = irqs[i]; |
|
1808 |
ppc40x_mal_reset(mal); |
|
1809 |
qemu_register_reset(&ppc40x_mal_reset, mal); |
|
1810 |
ppc_dcr_register(env, MAL0_CFG, |
|
1811 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1812 |
ppc_dcr_register(env, MAL0_ESR, |
|
1813 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1814 |
ppc_dcr_register(env, MAL0_IER, |
|
1815 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1816 |
ppc_dcr_register(env, MAL0_TXCASR, |
|
1817 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1818 |
ppc_dcr_register(env, MAL0_TXCARR, |
|
1819 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1820 |
ppc_dcr_register(env, MAL0_TXEOBISR, |
|
1821 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1822 |
ppc_dcr_register(env, MAL0_TXDEIR, |
|
1823 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1824 |
ppc_dcr_register(env, MAL0_RXCASR, |
|
1825 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1826 |
ppc_dcr_register(env, MAL0_RXCARR, |
|
1827 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1828 |
ppc_dcr_register(env, MAL0_RXEOBISR, |
|
1829 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1830 |
ppc_dcr_register(env, MAL0_RXDEIR, |
|
1831 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1832 |
ppc_dcr_register(env, MAL0_TXCTP0R, |
|
1833 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1834 |
ppc_dcr_register(env, MAL0_TXCTP1R, |
|
1835 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1836 |
ppc_dcr_register(env, MAL0_TXCTP2R, |
|
1837 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1838 |
ppc_dcr_register(env, MAL0_TXCTP3R, |
|
1839 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1840 |
ppc_dcr_register(env, MAL0_RXCTP0R, |
|
1841 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1842 |
ppc_dcr_register(env, MAL0_RXCTP1R, |
|
1843 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1844 |
ppc_dcr_register(env, MAL0_RCBS0, |
|
1845 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1846 |
ppc_dcr_register(env, MAL0_RCBS1, |
|
1847 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1848 |
} |
|
1787 |
for (i = 0; i < 4; i++) |
|
1788 |
mal->irqs[i] = irqs[i]; |
|
1789 |
ppc40x_mal_reset(mal); |
|
1790 |
qemu_register_reset(&ppc40x_mal_reset, mal); |
|
1791 |
ppc_dcr_register(env, MAL0_CFG, |
|
1792 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1793 |
ppc_dcr_register(env, MAL0_ESR, |
|
1794 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1795 |
ppc_dcr_register(env, MAL0_IER, |
|
1796 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1797 |
ppc_dcr_register(env, MAL0_TXCASR, |
|
1798 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1799 |
ppc_dcr_register(env, MAL0_TXCARR, |
|
1800 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1801 |
ppc_dcr_register(env, MAL0_TXEOBISR, |
|
1802 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1803 |
ppc_dcr_register(env, MAL0_TXDEIR, |
|
1804 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1805 |
ppc_dcr_register(env, MAL0_RXCASR, |
|
1806 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1807 |
ppc_dcr_register(env, MAL0_RXCARR, |
|
1808 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1809 |
ppc_dcr_register(env, MAL0_RXEOBISR, |
|
1810 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1811 |
ppc_dcr_register(env, MAL0_RXDEIR, |
|
1812 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1813 |
ppc_dcr_register(env, MAL0_TXCTP0R, |
|
1814 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1815 |
ppc_dcr_register(env, MAL0_TXCTP1R, |
|
1816 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1817 |
ppc_dcr_register(env, MAL0_TXCTP2R, |
|
1818 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1819 |
ppc_dcr_register(env, MAL0_TXCTP3R, |
|
1820 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1821 |
ppc_dcr_register(env, MAL0_RXCTP0R, |
|
1822 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1823 |
ppc_dcr_register(env, MAL0_RXCTP1R, |
|
1824 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1825 |
ppc_dcr_register(env, MAL0_RCBS0, |
|
1826 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1827 |
ppc_dcr_register(env, MAL0_RCBS1, |
|
1828 |
mal, &dcr_read_mal, &dcr_write_mal); |
|
1849 | 1829 |
} |
1850 | 1830 |
|
1851 | 1831 |
/*****************************************************************************/ |
... | ... | |
2170 | 2150 |
ppc405cr_cpc_t *cpc; |
2171 | 2151 |
|
2172 | 2152 |
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t)); |
2173 |
if (cpc != NULL) { |
|
2174 |
memcpy(cpc->clk_setup, clk_setup, |
|
2175 |
PPC405CR_CLK_NB * sizeof(clk_setup_t)); |
|
2176 |
cpc->sysclk = sysclk; |
|
2177 |
cpc->jtagid = 0x42051049; |
|
2178 |
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
|
2179 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2180 |
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
|
2181 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2182 |
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
|
2183 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2184 |
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
|
2185 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2186 |
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
|
2187 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2188 |
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
|
2189 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2190 |
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
|
2191 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2192 |
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
|
2193 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2194 |
ppc405cr_clk_init(cpc); |
|
2195 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
|
2196 |
ppc405cr_cpc_reset(cpc); |
|
2197 |
} |
|
2153 |
memcpy(cpc->clk_setup, clk_setup, |
|
2154 |
PPC405CR_CLK_NB * sizeof(clk_setup_t)); |
|
2155 |
cpc->sysclk = sysclk; |
|
2156 |
cpc->jtagid = 0x42051049; |
|
2157 |
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
|
2158 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2159 |
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
|
2160 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2161 |
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
|
2162 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2163 |
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
|
2164 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2165 |
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
|
2166 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2167 |
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
|
2168 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2169 |
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
|
2170 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2171 |
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
|
2172 |
&dcr_read_crcpc, &dcr_write_crcpc); |
|
2173 |
ppc405cr_clk_init(cpc); |
|
2174 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
|
2175 |
ppc405cr_cpc_reset(cpc); |
|
2198 | 2176 |
} |
2199 | 2177 |
|
2200 | 2178 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
... | ... | |
2516 | 2494 |
ppc405ep_cpc_t *cpc; |
2517 | 2495 |
|
2518 | 2496 |
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t)); |
2519 |
if (cpc != NULL) { |
|
2520 |
memcpy(cpc->clk_setup, clk_setup, |
|
2521 |
PPC405EP_CLK_NB * sizeof(clk_setup_t)); |
|
2522 |
cpc->jtagid = 0x20267049; |
|
2523 |
cpc->sysclk = sysclk; |
|
2524 |
ppc405ep_cpc_reset(cpc); |
|
2525 |
qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
|
2526 |
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
|
2527 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2528 |
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
|
2529 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2530 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
|
2531 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2532 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
|
2533 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2534 |
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
|
2535 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2536 |
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
|
2537 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2538 |
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
|
2539 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2540 |
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
|
2541 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2497 |
memcpy(cpc->clk_setup, clk_setup, |
|
2498 |
PPC405EP_CLK_NB * sizeof(clk_setup_t)); |
|
2499 |
cpc->jtagid = 0x20267049; |
|
2500 |
cpc->sysclk = sysclk; |
|
2501 |
ppc405ep_cpc_reset(cpc); |
|
2502 |
qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
|
2503 |
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
|
2504 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2505 |
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
|
2506 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2507 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
|
2508 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2509 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
|
2510 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2511 |
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
|
2512 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2513 |
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
|
2514 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2515 |
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
|
2516 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2517 |
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
|
2518 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2542 | 2519 |
#if 0 |
2543 |
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
|
2544 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
|
2545 |
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
|
2546 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
|
2547 |
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
|
2548 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
|
2520 |
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, |
|
2521 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2522 |
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, |
|
2523 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2524 |
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, |
|
2525 |
&dcr_read_epcpc, &dcr_write_epcpc); |
|
2549 | 2526 |
#endif |
2550 |
} |
|
2551 | 2527 |
} |
2552 | 2528 |
|
2553 | 2529 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
Also available in: Unified diff