Revision 487414f1 hw/ppc4xx_devs.c
b/hw/ppc4xx_devs.c | ||
---|---|---|
246 | 246 |
int mmio_memory; |
247 | 247 |
|
248 | 248 |
mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t)); |
249 |
if (mmio != NULL) { |
|
250 |
mmio->base = base; |
|
251 |
mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio); |
|
249 |
mmio->base = base; |
|
250 |
mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio); |
|
252 | 251 |
#if defined(DEBUG_MMIO) |
253 |
printf("%s: base " PADDRX " len %08x %d\n", __func__,
|
|
254 |
base, TARGET_PAGE_SIZE, mmio_memory);
|
|
252 |
printf("%s: base " PADDRX " len %08x %d\n", __func__, |
|
253 |
base, TARGET_PAGE_SIZE, mmio_memory); |
|
255 | 254 |
#endif |
256 |
cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
|
257 |
ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE, |
|
258 |
unassigned_mmio_read, unassigned_mmio_write, |
|
259 |
mmio); |
|
260 |
} |
|
255 |
cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
|
256 |
ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE, |
|
257 |
unassigned_mmio_read, unassigned_mmio_write, |
|
258 |
mmio); |
|
261 | 259 |
|
262 | 260 |
return mmio; |
263 | 261 |
} |
... | ... | |
492 | 490 |
int i; |
493 | 491 |
|
494 | 492 |
uic = qemu_mallocz(sizeof(ppcuic_t)); |
495 |
if (uic != NULL) { |
|
496 |
uic->dcr_base = dcr_base; |
|
497 |
uic->irqs = irqs; |
|
498 |
if (has_vr) |
|
499 |
uic->use_vectors = 1; |
|
500 |
for (i = 0; i < DCR_UICMAX; i++) { |
|
501 |
ppc_dcr_register(env, dcr_base + i, uic, |
|
502 |
&dcr_read_uic, &dcr_write_uic); |
|
503 |
} |
|
504 |
qemu_register_reset(ppcuic_reset, uic); |
|
505 |
ppcuic_reset(uic); |
|
493 |
uic->dcr_base = dcr_base; |
|
494 |
uic->irqs = irqs; |
|
495 |
if (has_vr) |
|
496 |
uic->use_vectors = 1; |
|
497 |
for (i = 0; i < DCR_UICMAX; i++) { |
|
498 |
ppc_dcr_register(env, dcr_base + i, uic, |
|
499 |
&dcr_read_uic, &dcr_write_uic); |
|
506 | 500 |
} |
501 |
qemu_register_reset(ppcuic_reset, uic); |
|
502 |
ppcuic_reset(uic); |
|
507 | 503 |
|
508 | 504 |
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); |
509 | 505 |
} |
... | ... | |
829 | 825 |
ppc4xx_sdram_t *sdram; |
830 | 826 |
|
831 | 827 |
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t)); |
832 |
if (sdram != NULL) { |
|
833 |
sdram->irq = irq; |
|
834 |
sdram->nbanks = nbanks; |
|
835 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
|
836 |
memcpy(sdram->ram_bases, ram_bases, |
|
837 |
nbanks * sizeof(target_phys_addr_t)); |
|
838 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
|
839 |
memcpy(sdram->ram_sizes, ram_sizes, |
|
840 |
nbanks * sizeof(target_phys_addr_t)); |
|
841 |
sdram_reset(sdram); |
|
842 |
qemu_register_reset(&sdram_reset, sdram); |
|
843 |
ppc_dcr_register(env, SDRAM0_CFGADDR, |
|
844 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
|
845 |
ppc_dcr_register(env, SDRAM0_CFGDATA, |
|
846 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
|
847 |
if (do_init) |
|
848 |
sdram_map_bcr(sdram); |
|
849 |
} |
|
828 |
sdram->irq = irq; |
|
829 |
sdram->nbanks = nbanks; |
|
830 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
|
831 |
memcpy(sdram->ram_bases, ram_bases, |
|
832 |
nbanks * sizeof(target_phys_addr_t)); |
|
833 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
|
834 |
memcpy(sdram->ram_sizes, ram_sizes, |
|
835 |
nbanks * sizeof(target_phys_addr_t)); |
|
836 |
sdram_reset(sdram); |
|
837 |
qemu_register_reset(&sdram_reset, sdram); |
|
838 |
ppc_dcr_register(env, SDRAM0_CFGADDR, |
|
839 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
|
840 |
ppc_dcr_register(env, SDRAM0_CFGDATA, |
|
841 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
|
842 |
if (do_init) |
|
843 |
sdram_map_bcr(sdram); |
|
850 | 844 |
} |
851 | 845 |
|
852 | 846 |
/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. |
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