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/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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#include "host-utils.h" |
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|
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//#define DEBUG_APIC
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//#define DEBUG_IOAPIC
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0 |
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#define APIC_LVT_THERMAL 1 |
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#define APIC_LVT_PERFORM 2 |
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#define APIC_LVT_LINT0 3 |
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#define APIC_LVT_LINT1 4 |
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#define APIC_LVT_ERROR 5 |
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#define APIC_LVT_NB 6 |
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|
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0 |
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#define APIC_DM_LOWPRI 1 |
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#define APIC_DM_SMI 2 |
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#define APIC_DM_NMI 4 |
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#define APIC_DM_INIT 5 |
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#define APIC_DM_SIPI 6 |
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#define APIC_DM_EXTINT 7 |
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|
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/* APIC destination mode */
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#define APIC_DESTMODE_FLAT 0xf |
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#define APIC_DESTMODE_CLUSTER 1 |
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|
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#define APIC_TRIGGER_EDGE 0 |
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#define APIC_TRIGGER_LEVEL 1 |
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|
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#define APIC_LVT_TIMER_PERIODIC (1<<17) |
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#define APIC_LVT_MASKED (1<<16) |
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#define APIC_LVT_LEVEL_TRIGGER (1<<15) |
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#define APIC_LVT_REMOTE_IRR (1<<14) |
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#define APIC_INPUT_POLARITY (1<<13) |
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#define APIC_SEND_PENDING (1<<12) |
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|
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#define IOAPIC_NUM_PINS 0x18 |
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|
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#define ESR_ILLEGAL_ADDRESS (1 << 7) |
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|
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#define APIC_SV_ENABLE (1 << 8) |
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|
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#define MAX_APICS 255 |
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#define MAX_APIC_WORDS 8 |
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|
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typedef struct APICState { |
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CPUState *cpu_env; |
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uint32_t apicbase; |
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uint8_t id; |
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uint8_t arb_id; |
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uint8_t tpr; |
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uint32_t spurious_vec; |
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uint8_t log_dest; |
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uint8_t dest_mode; |
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uint32_t isr[8]; /* in service register */ |
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uint32_t tmr[8]; /* trigger mode register */ |
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uint32_t irr[8]; /* interrupt request register */ |
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uint32_t lvt[APIC_LVT_NB]; |
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uint32_t esr; /* error register */
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uint32_t icr[2];
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|
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uint32_t divide_conf; |
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int count_shift;
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uint32_t initial_count; |
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int64_t initial_count_load_time, next_time; |
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QEMUTimer *timer; |
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} APICState; |
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|
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struct IOAPICState {
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uint8_t id; |
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uint8_t ioregsel; |
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|
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uint32_t irr; |
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uint64_t ioredtbl[IOAPIC_NUM_PINS]; |
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}; |
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|
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static int apic_io_memory; |
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static APICState *local_apics[MAX_APICS + 1]; |
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static int last_apic_id = 0; |
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static int apic_irq_delivered; |
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|
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|
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static void apic_init_ipi(APICState *s); |
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
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static void apic_update_irq(APICState *s); |
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|
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/* Find first bit starting from msb */
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static int fls_bit(uint32_t value) |
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{
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return 31 - clz32(value); |
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} |
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|
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/* Find first bit starting from lsb */
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static int ffs_bit(uint32_t value) |
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{
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return ctz32(value);
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} |
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|
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static inline void set_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] |= mask; |
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} |
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|
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static inline void reset_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] &= ~mask; |
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} |
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|
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static inline int get_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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return !!(tab[i] & mask);
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} |
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|
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static void apic_local_deliver(CPUState *env, int vector) |
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{
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APICState *s = env->apic_state; |
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uint32_t lvt = s->lvt[vector]; |
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int trigger_mode;
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_SMI:
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cpu_interrupt(env, CPU_INTERRUPT_SMI); |
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break;
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|
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case APIC_DM_NMI:
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cpu_interrupt(env, CPU_INTERRUPT_NMI); |
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break;
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|
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case APIC_DM_EXTINT:
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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break;
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE; |
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER)) |
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trigger_mode = APIC_TRIGGER_LEVEL; |
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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} |
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} |
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|
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void apic_deliver_pic_intr(CPUState *env, int level) |
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{
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if (level)
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apic_local_deliver(env, APIC_LVT_LINT0); |
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else {
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APICState *s = env->apic_state; |
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uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
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|
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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break;
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} |
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} |
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} |
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|
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
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__mask = deliver_bitmask[__i];\ |
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\ |
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if (__mask & (1 << __j)) {\ |
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\ |
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}\ |
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}\ |
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}\ |
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}\ |
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}\ |
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} |
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|
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static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
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uint8_t delivery_mode, |
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uint8_t vector_num, uint8_t polarity, |
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uint8_t trigger_mode) |
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{
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APICState *apic_iter; |
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) { |
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if (deliver_bitmask[i]) {
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d = i * 32 + ffs_bit(deliver_bitmask[i]);
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break;
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} |
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} |
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if (d >= 0) { |
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apic_iter = local_apics[d]; |
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode); |
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} |
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} |
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} |
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return;
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|
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case APIC_DM_FIXED:
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break;
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|
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case APIC_DM_SMI:
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
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return;
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|
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case APIC_DM_NMI:
|
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
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return;
|
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|
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case APIC_DM_INIT:
|
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/* normal INIT IPI sent to processors */
|
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foreach_apic(apic_iter, deliver_bitmask, |
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apic_init_ipi(apic_iter) ); |
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return;
|
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|
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case APIC_DM_EXTINT:
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/* handled in I/O APIC code */
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break;
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|
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default:
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return;
|
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} |
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|
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foreach_apic(apic_iter, deliver_bitmask, |
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apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
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} |
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|
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void cpu_set_apic_base(CPUState *env, uint64_t val)
|
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{
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APICState *s = env->apic_state; |
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#ifdef DEBUG_APIC
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printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
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#endif
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s->apicbase = (val & 0xfffff000) |
|
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
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/* if disabled, cannot be enabled again */
|
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
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env->cpuid_features &= ~CPUID_APIC; |
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s->spurious_vec &= ~APIC_SV_ENABLE; |
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} |
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} |
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|
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uint64_t cpu_get_apic_base(CPUState *env) |
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{
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APICState *s = env->apic_state; |
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#ifdef DEBUG_APIC
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printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase); |
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#endif
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return s->apicbase;
|
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} |
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|
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void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
|
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{
|
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APICState *s = env->apic_state; |
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s->tpr = (val & 0x0f) << 4; |
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apic_update_irq(s); |
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} |
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|
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uint8_t cpu_get_apic_tpr(CPUX86State *env) |
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{
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APICState *s = env->apic_state; |
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return s->tpr >> 4; |
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} |
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|
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/* return -1 if no bit is set */
|
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static int get_highest_priority_int(uint32_t *tab) |
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{
|
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int i;
|
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for(i = 7; i >= 0; i--) { |
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if (tab[i] != 0) { |
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return i * 32 + fls_bit(tab[i]); |
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} |
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} |
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return -1; |
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} |
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|
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static int apic_get_ppr(APICState *s) |
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{
|
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int tpr, isrv, ppr;
|
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|
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tpr = (s->tpr >> 4);
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isrv = get_highest_priority_int(s->isr); |
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if (isrv < 0) |
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isrv = 0;
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isrv >>= 4;
|
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if (tpr >= isrv)
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ppr = s->tpr; |
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else
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ppr = isrv << 4;
|
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return ppr;
|
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} |
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|
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static int apic_get_arb_pri(APICState *s) |
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{
|
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/* XXX: arbitration */
|
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return 0; |
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} |
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|
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/* signal the CPU if an irq is pending */
|
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static void apic_update_irq(APICState *s) |
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{
|
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int irrv, ppr;
|
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if (!(s->spurious_vec & APIC_SV_ENABLE))
|
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return;
|
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irrv = get_highest_priority_int(s->irr); |
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if (irrv < 0) |
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return;
|
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ppr = apic_get_ppr(s); |
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if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
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return;
|
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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} |
| 361 |
|
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void apic_reset_irq_delivered(void) |
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{
|
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apic_irq_delivered = 0;
|
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} |
| 366 |
|
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int apic_get_irq_delivered(void) |
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{
|
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return apic_irq_delivered;
|
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} |
| 371 |
|
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
| 373 |
{
|
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apic_irq_delivered += !get_bit(s->irr, vector_num); |
| 375 |
|
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set_bit(s->irr, vector_num); |
| 377 |
if (trigger_mode)
|
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set_bit(s->tmr, vector_num); |
| 379 |
else
|
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reset_bit(s->tmr, vector_num); |
| 381 |
apic_update_irq(s); |
| 382 |
} |
| 383 |
|
| 384 |
static void apic_eoi(APICState *s) |
| 385 |
{
|
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int isrv;
|
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isrv = get_highest_priority_int(s->isr); |
| 388 |
if (isrv < 0) |
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return;
|
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reset_bit(s->isr, isrv); |
| 391 |
/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
|
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set the remote IRR bit for level triggered interrupts. */
|
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apic_update_irq(s); |
| 394 |
} |
| 395 |
|
| 396 |
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
| 397 |
uint8_t dest, uint8_t dest_mode) |
| 398 |
{
|
| 399 |
APICState *apic_iter; |
| 400 |
int i;
|
| 401 |
|
| 402 |
if (dest_mode == 0) { |
| 403 |
if (dest == 0xff) { |
| 404 |
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 405 |
} else {
|
| 406 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 407 |
set_bit(deliver_bitmask, dest); |
| 408 |
} |
| 409 |
} else {
|
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/* XXX: cluster mode */
|
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memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 412 |
for(i = 0; i < MAX_APICS; i++) { |
| 413 |
apic_iter = local_apics[i]; |
| 414 |
if (apic_iter) {
|
| 415 |
if (apic_iter->dest_mode == 0xf) { |
| 416 |
if (dest & apic_iter->log_dest)
|
| 417 |
set_bit(deliver_bitmask, i); |
| 418 |
} else if (apic_iter->dest_mode == 0x0) { |
| 419 |
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
| 420 |
(dest & apic_iter->log_dest & 0x0f)) {
|
| 421 |
set_bit(deliver_bitmask, i); |
| 422 |
} |
| 423 |
} |
| 424 |
} |
| 425 |
} |
| 426 |
} |
| 427 |
} |
| 428 |
|
| 429 |
|
| 430 |
static void apic_init_ipi(APICState *s) |
| 431 |
{
|
| 432 |
int i;
|
| 433 |
|
| 434 |
s->tpr = 0;
|
| 435 |
s->spurious_vec = 0xff;
|
| 436 |
s->log_dest = 0;
|
| 437 |
s->dest_mode = 0xf;
|
| 438 |
memset(s->isr, 0, sizeof(s->isr)); |
| 439 |
memset(s->tmr, 0, sizeof(s->tmr)); |
| 440 |
memset(s->irr, 0, sizeof(s->irr)); |
| 441 |
for(i = 0; i < APIC_LVT_NB; i++) |
| 442 |
s->lvt[i] = 1 << 16; /* mask LVT */ |
| 443 |
s->esr = 0;
|
| 444 |
memset(s->icr, 0, sizeof(s->icr)); |
| 445 |
s->divide_conf = 0;
|
| 446 |
s->count_shift = 0;
|
| 447 |
s->initial_count = 0;
|
| 448 |
s->initial_count_load_time = 0;
|
| 449 |
s->next_time = 0;
|
| 450 |
|
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cpu_reset(s->cpu_env); |
| 452 |
|
| 453 |
if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
|
| 454 |
s->cpu_env->halted = 1;
|
| 455 |
} |
| 456 |
|
| 457 |
/* send a SIPI message to the CPU to start it */
|
| 458 |
static void apic_startup(APICState *s, int vector_num) |
| 459 |
{
|
| 460 |
CPUState *env = s->cpu_env; |
| 461 |
if (!env->halted)
|
| 462 |
return;
|
| 463 |
env->eip = 0;
|
| 464 |
cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, |
| 465 |
0xffff, 0); |
| 466 |
env->halted = 0;
|
| 467 |
} |
| 468 |
|
| 469 |
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
| 470 |
uint8_t delivery_mode, uint8_t vector_num, |
| 471 |
uint8_t polarity, uint8_t trigger_mode) |
| 472 |
{
|
| 473 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
| 474 |
int dest_shorthand = (s->icr[0] >> 18) & 3; |
| 475 |
APICState *apic_iter; |
| 476 |
|
| 477 |
switch (dest_shorthand) {
|
| 478 |
case 0: |
| 479 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
| 480 |
break;
|
| 481 |
case 1: |
| 482 |
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
| 483 |
set_bit(deliver_bitmask, s->id); |
| 484 |
break;
|
| 485 |
case 2: |
| 486 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
| 487 |
break;
|
| 488 |
case 3: |
| 489 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
| 490 |
reset_bit(deliver_bitmask, s->id); |
| 491 |
break;
|
| 492 |
} |
| 493 |
|
| 494 |
switch (delivery_mode) {
|
| 495 |
case APIC_DM_INIT:
|
| 496 |
{
|
| 497 |
int trig_mode = (s->icr[0] >> 15) & 1; |
| 498 |
int level = (s->icr[0] >> 14) & 1; |
| 499 |
if (level == 0 && trig_mode == 1) { |
| 500 |
foreach_apic(apic_iter, deliver_bitmask, |
| 501 |
apic_iter->arb_id = apic_iter->id ); |
| 502 |
return;
|
| 503 |
} |
| 504 |
} |
| 505 |
break;
|
| 506 |
|
| 507 |
case APIC_DM_SIPI:
|
| 508 |
foreach_apic(apic_iter, deliver_bitmask, |
| 509 |
apic_startup(apic_iter, vector_num) ); |
| 510 |
return;
|
| 511 |
} |
| 512 |
|
| 513 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
| 514 |
trigger_mode); |
| 515 |
} |
| 516 |
|
| 517 |
int apic_get_interrupt(CPUState *env)
|
| 518 |
{
|
| 519 |
APICState *s = env->apic_state; |
| 520 |
int intno;
|
| 521 |
|
| 522 |
/* if the APIC is installed or enabled, we let the 8259 handle the
|
| 523 |
IRQs */
|
| 524 |
if (!s)
|
| 525 |
return -1; |
| 526 |
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
| 527 |
return -1; |
| 528 |
|
| 529 |
/* XXX: spurious IRQ handling */
|
| 530 |
intno = get_highest_priority_int(s->irr); |
| 531 |
if (intno < 0) |
| 532 |
return -1; |
| 533 |
if (s->tpr && intno <= s->tpr)
|
| 534 |
return s->spurious_vec & 0xff; |
| 535 |
reset_bit(s->irr, intno); |
| 536 |
set_bit(s->isr, intno); |
| 537 |
apic_update_irq(s); |
| 538 |
return intno;
|
| 539 |
} |
| 540 |
|
| 541 |
int apic_accept_pic_intr(CPUState *env)
|
| 542 |
{
|
| 543 |
APICState *s = env->apic_state; |
| 544 |
uint32_t lvt0; |
| 545 |
|
| 546 |
if (!s)
|
| 547 |
return -1; |
| 548 |
|
| 549 |
lvt0 = s->lvt[APIC_LVT_LINT0]; |
| 550 |
|
| 551 |
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
| 552 |
(lvt0 & APIC_LVT_MASKED) == 0)
|
| 553 |
return 1; |
| 554 |
|
| 555 |
return 0; |
| 556 |
} |
| 557 |
|
| 558 |
static uint32_t apic_get_current_count(APICState *s)
|
| 559 |
{
|
| 560 |
int64_t d; |
| 561 |
uint32_t val; |
| 562 |
d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
| 563 |
s->count_shift; |
| 564 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
| 565 |
/* periodic */
|
| 566 |
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
| 567 |
} else {
|
| 568 |
if (d >= s->initial_count)
|
| 569 |
val = 0;
|
| 570 |
else
|
| 571 |
val = s->initial_count - d; |
| 572 |
} |
| 573 |
return val;
|
| 574 |
} |
| 575 |
|
| 576 |
static void apic_timer_update(APICState *s, int64_t current_time) |
| 577 |
{
|
| 578 |
int64_t next_time, d; |
| 579 |
|
| 580 |
if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
| 581 |
d = (current_time - s->initial_count_load_time) >> |
| 582 |
s->count_shift; |
| 583 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
| 584 |
if (!s->initial_count)
|
| 585 |
goto no_timer;
|
| 586 |
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
| 587 |
} else {
|
| 588 |
if (d >= s->initial_count)
|
| 589 |
goto no_timer;
|
| 590 |
d = (uint64_t)s->initial_count + 1;
|
| 591 |
} |
| 592 |
next_time = s->initial_count_load_time + (d << s->count_shift); |
| 593 |
qemu_mod_timer(s->timer, next_time); |
| 594 |
s->next_time = next_time; |
| 595 |
} else {
|
| 596 |
no_timer:
|
| 597 |
qemu_del_timer(s->timer); |
| 598 |
} |
| 599 |
} |
| 600 |
|
| 601 |
static void apic_timer(void *opaque) |
| 602 |
{
|
| 603 |
APICState *s = opaque; |
| 604 |
|
| 605 |
apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
| 606 |
apic_timer_update(s, s->next_time); |
| 607 |
} |
| 608 |
|
| 609 |
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
| 610 |
{
|
| 611 |
return 0; |
| 612 |
} |
| 613 |
|
| 614 |
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
| 615 |
{
|
| 616 |
return 0; |
| 617 |
} |
| 618 |
|
| 619 |
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 620 |
{
|
| 621 |
} |
| 622 |
|
| 623 |
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 624 |
{
|
| 625 |
} |
| 626 |
|
| 627 |
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
| 628 |
{
|
| 629 |
CPUState *env; |
| 630 |
APICState *s; |
| 631 |
uint32_t val; |
| 632 |
int index;
|
| 633 |
|
| 634 |
env = cpu_single_env; |
| 635 |
if (!env)
|
| 636 |
return 0; |
| 637 |
s = env->apic_state; |
| 638 |
|
| 639 |
index = (addr >> 4) & 0xff; |
| 640 |
switch(index) {
|
| 641 |
case 0x02: /* id */ |
| 642 |
val = s->id << 24;
|
| 643 |
break;
|
| 644 |
case 0x03: /* version */ |
| 645 |
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
| 646 |
break;
|
| 647 |
case 0x08: |
| 648 |
val = s->tpr; |
| 649 |
break;
|
| 650 |
case 0x09: |
| 651 |
val = apic_get_arb_pri(s); |
| 652 |
break;
|
| 653 |
case 0x0a: |
| 654 |
/* ppr */
|
| 655 |
val = apic_get_ppr(s); |
| 656 |
break;
|
| 657 |
case 0x0b: |
| 658 |
val = 0;
|
| 659 |
break;
|
| 660 |
case 0x0d: |
| 661 |
val = s->log_dest << 24;
|
| 662 |
break;
|
| 663 |
case 0x0e: |
| 664 |
val = s->dest_mode << 28;
|
| 665 |
break;
|
| 666 |
case 0x0f: |
| 667 |
val = s->spurious_vec; |
| 668 |
break;
|
| 669 |
case 0x10 ... 0x17: |
| 670 |
val = s->isr[index & 7];
|
| 671 |
break;
|
| 672 |
case 0x18 ... 0x1f: |
| 673 |
val = s->tmr[index & 7];
|
| 674 |
break;
|
| 675 |
case 0x20 ... 0x27: |
| 676 |
val = s->irr[index & 7];
|
| 677 |
break;
|
| 678 |
case 0x28: |
| 679 |
val = s->esr; |
| 680 |
break;
|
| 681 |
case 0x30: |
| 682 |
case 0x31: |
| 683 |
val = s->icr[index & 1];
|
| 684 |
break;
|
| 685 |
case 0x32 ... 0x37: |
| 686 |
val = s->lvt[index - 0x32];
|
| 687 |
break;
|
| 688 |
case 0x38: |
| 689 |
val = s->initial_count; |
| 690 |
break;
|
| 691 |
case 0x39: |
| 692 |
val = apic_get_current_count(s); |
| 693 |
break;
|
| 694 |
case 0x3e: |
| 695 |
val = s->divide_conf; |
| 696 |
break;
|
| 697 |
default:
|
| 698 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
| 699 |
val = 0;
|
| 700 |
break;
|
| 701 |
} |
| 702 |
#ifdef DEBUG_APIC
|
| 703 |
printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
|
| 704 |
#endif
|
| 705 |
return val;
|
| 706 |
} |
| 707 |
|
| 708 |
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 709 |
{
|
| 710 |
CPUState *env; |
| 711 |
APICState *s; |
| 712 |
int index;
|
| 713 |
|
| 714 |
env = cpu_single_env; |
| 715 |
if (!env)
|
| 716 |
return;
|
| 717 |
s = env->apic_state; |
| 718 |
|
| 719 |
#ifdef DEBUG_APIC
|
| 720 |
printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
| 721 |
#endif
|
| 722 |
|
| 723 |
index = (addr >> 4) & 0xff; |
| 724 |
switch(index) {
|
| 725 |
case 0x02: |
| 726 |
s->id = (val >> 24);
|
| 727 |
break;
|
| 728 |
case 0x03: |
| 729 |
break;
|
| 730 |
case 0x08: |
| 731 |
s->tpr = val; |
| 732 |
apic_update_irq(s); |
| 733 |
break;
|
| 734 |
case 0x09: |
| 735 |
case 0x0a: |
| 736 |
break;
|
| 737 |
case 0x0b: /* EOI */ |
| 738 |
apic_eoi(s); |
| 739 |
break;
|
| 740 |
case 0x0d: |
| 741 |
s->log_dest = val >> 24;
|
| 742 |
break;
|
| 743 |
case 0x0e: |
| 744 |
s->dest_mode = val >> 28;
|
| 745 |
break;
|
| 746 |
case 0x0f: |
| 747 |
s->spurious_vec = val & 0x1ff;
|
| 748 |
apic_update_irq(s); |
| 749 |
break;
|
| 750 |
case 0x10 ... 0x17: |
| 751 |
case 0x18 ... 0x1f: |
| 752 |
case 0x20 ... 0x27: |
| 753 |
case 0x28: |
| 754 |
break;
|
| 755 |
case 0x30: |
| 756 |
s->icr[0] = val;
|
| 757 |
apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
| 758 |
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
| 759 |
(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
| 760 |
break;
|
| 761 |
case 0x31: |
| 762 |
s->icr[1] = val;
|
| 763 |
break;
|
| 764 |
case 0x32 ... 0x37: |
| 765 |
{
|
| 766 |
int n = index - 0x32; |
| 767 |
s->lvt[n] = val; |
| 768 |
if (n == APIC_LVT_TIMER)
|
| 769 |
apic_timer_update(s, qemu_get_clock(vm_clock)); |
| 770 |
} |
| 771 |
break;
|
| 772 |
case 0x38: |
| 773 |
s->initial_count = val; |
| 774 |
s->initial_count_load_time = qemu_get_clock(vm_clock); |
| 775 |
apic_timer_update(s, s->initial_count_load_time); |
| 776 |
break;
|
| 777 |
case 0x39: |
| 778 |
break;
|
| 779 |
case 0x3e: |
| 780 |
{
|
| 781 |
int v;
|
| 782 |
s->divide_conf = val & 0xb;
|
| 783 |
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
| 784 |
s->count_shift = (v + 1) & 7; |
| 785 |
} |
| 786 |
break;
|
| 787 |
default:
|
| 788 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
| 789 |
break;
|
| 790 |
} |
| 791 |
} |
| 792 |
|
| 793 |
static void apic_save(QEMUFile *f, void *opaque) |
| 794 |
{
|
| 795 |
APICState *s = opaque; |
| 796 |
int i;
|
| 797 |
|
| 798 |
qemu_put_be32s(f, &s->apicbase); |
| 799 |
qemu_put_8s(f, &s->id); |
| 800 |
qemu_put_8s(f, &s->arb_id); |
| 801 |
qemu_put_8s(f, &s->tpr); |
| 802 |
qemu_put_be32s(f, &s->spurious_vec); |
| 803 |
qemu_put_8s(f, &s->log_dest); |
| 804 |
qemu_put_8s(f, &s->dest_mode); |
| 805 |
for (i = 0; i < 8; i++) { |
| 806 |
qemu_put_be32s(f, &s->isr[i]); |
| 807 |
qemu_put_be32s(f, &s->tmr[i]); |
| 808 |
qemu_put_be32s(f, &s->irr[i]); |
| 809 |
} |
| 810 |
for (i = 0; i < APIC_LVT_NB; i++) { |
| 811 |
qemu_put_be32s(f, &s->lvt[i]); |
| 812 |
} |
| 813 |
qemu_put_be32s(f, &s->esr); |
| 814 |
qemu_put_be32s(f, &s->icr[0]);
|
| 815 |
qemu_put_be32s(f, &s->icr[1]);
|
| 816 |
qemu_put_be32s(f, &s->divide_conf); |
| 817 |
qemu_put_be32(f, s->count_shift); |
| 818 |
qemu_put_be32s(f, &s->initial_count); |
| 819 |
qemu_put_be64(f, s->initial_count_load_time); |
| 820 |
qemu_put_be64(f, s->next_time); |
| 821 |
|
| 822 |
qemu_put_timer(f, s->timer); |
| 823 |
} |
| 824 |
|
| 825 |
static int apic_load(QEMUFile *f, void *opaque, int version_id) |
| 826 |
{
|
| 827 |
APICState *s = opaque; |
| 828 |
int i;
|
| 829 |
|
| 830 |
if (version_id > 2) |
| 831 |
return -EINVAL;
|
| 832 |
|
| 833 |
/* XXX: what if the base changes? (registered memory regions) */
|
| 834 |
qemu_get_be32s(f, &s->apicbase); |
| 835 |
qemu_get_8s(f, &s->id); |
| 836 |
qemu_get_8s(f, &s->arb_id); |
| 837 |
qemu_get_8s(f, &s->tpr); |
| 838 |
qemu_get_be32s(f, &s->spurious_vec); |
| 839 |
qemu_get_8s(f, &s->log_dest); |
| 840 |
qemu_get_8s(f, &s->dest_mode); |
| 841 |
for (i = 0; i < 8; i++) { |
| 842 |
qemu_get_be32s(f, &s->isr[i]); |
| 843 |
qemu_get_be32s(f, &s->tmr[i]); |
| 844 |
qemu_get_be32s(f, &s->irr[i]); |
| 845 |
} |
| 846 |
for (i = 0; i < APIC_LVT_NB; i++) { |
| 847 |
qemu_get_be32s(f, &s->lvt[i]); |
| 848 |
} |
| 849 |
qemu_get_be32s(f, &s->esr); |
| 850 |
qemu_get_be32s(f, &s->icr[0]);
|
| 851 |
qemu_get_be32s(f, &s->icr[1]);
|
| 852 |
qemu_get_be32s(f, &s->divide_conf); |
| 853 |
s->count_shift=qemu_get_be32(f); |
| 854 |
qemu_get_be32s(f, &s->initial_count); |
| 855 |
s->initial_count_load_time=qemu_get_be64(f); |
| 856 |
s->next_time=qemu_get_be64(f); |
| 857 |
|
| 858 |
if (version_id >= 2) |
| 859 |
qemu_get_timer(f, s->timer); |
| 860 |
return 0; |
| 861 |
} |
| 862 |
|
| 863 |
static void apic_reset(void *opaque) |
| 864 |
{
|
| 865 |
APICState *s = opaque; |
| 866 |
|
| 867 |
s->apicbase = 0xfee00000 |
|
| 868 |
(s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
|
| 869 |
|
| 870 |
apic_init_ipi(s); |
| 871 |
|
| 872 |
if (s->id == 0) { |
| 873 |
/*
|
| 874 |
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
| 875 |
* time typically by BIOS, so PIC interrupt can be delivered to the
|
| 876 |
* processor when local APIC is enabled.
|
| 877 |
*/
|
| 878 |
s->lvt[APIC_LVT_LINT0] = 0x700;
|
| 879 |
} |
| 880 |
} |
| 881 |
|
| 882 |
static CPUReadMemoryFunc *apic_mem_read[3] = { |
| 883 |
apic_mem_readb, |
| 884 |
apic_mem_readw, |
| 885 |
apic_mem_readl, |
| 886 |
}; |
| 887 |
|
| 888 |
static CPUWriteMemoryFunc *apic_mem_write[3] = { |
| 889 |
apic_mem_writeb, |
| 890 |
apic_mem_writew, |
| 891 |
apic_mem_writel, |
| 892 |
}; |
| 893 |
|
| 894 |
int apic_init(CPUState *env)
|
| 895 |
{
|
| 896 |
APICState *s; |
| 897 |
|
| 898 |
if (last_apic_id >= MAX_APICS)
|
| 899 |
return -1; |
| 900 |
s = qemu_mallocz(sizeof(APICState));
|
| 901 |
env->apic_state = s; |
| 902 |
s->id = last_apic_id++; |
| 903 |
env->cpuid_apic_id = s->id; |
| 904 |
s->cpu_env = env; |
| 905 |
|
| 906 |
apic_reset(s); |
| 907 |
|
| 908 |
/* XXX: mapping more APICs at the same memory location */
|
| 909 |
if (apic_io_memory == 0) { |
| 910 |
/* NOTE: the APIC is directly connected to the CPU - it is not
|
| 911 |
on the global memory bus. */
|
| 912 |
apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
|
| 913 |
apic_mem_write, NULL);
|
| 914 |
cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, |
| 915 |
apic_io_memory); |
| 916 |
} |
| 917 |
s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
| 918 |
|
| 919 |
register_savevm("apic", s->id, 2, apic_save, apic_load, s); |
| 920 |
qemu_register_reset(apic_reset, s); |
| 921 |
|
| 922 |
local_apics[s->id] = s; |
| 923 |
return 0; |
| 924 |
} |
| 925 |
|
| 926 |
static void ioapic_service(IOAPICState *s) |
| 927 |
{
|
| 928 |
uint8_t i; |
| 929 |
uint8_t trig_mode; |
| 930 |
uint8_t vector; |
| 931 |
uint8_t delivery_mode; |
| 932 |
uint32_t mask; |
| 933 |
uint64_t entry; |
| 934 |
uint8_t dest; |
| 935 |
uint8_t dest_mode; |
| 936 |
uint8_t polarity; |
| 937 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
| 938 |
|
| 939 |
for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
| 940 |
mask = 1 << i;
|
| 941 |
if (s->irr & mask) {
|
| 942 |
entry = s->ioredtbl[i]; |
| 943 |
if (!(entry & APIC_LVT_MASKED)) {
|
| 944 |
trig_mode = ((entry >> 15) & 1); |
| 945 |
dest = entry >> 56;
|
| 946 |
dest_mode = (entry >> 11) & 1; |
| 947 |
delivery_mode = (entry >> 8) & 7; |
| 948 |
polarity = (entry >> 13) & 1; |
| 949 |
if (trig_mode == APIC_TRIGGER_EDGE)
|
| 950 |
s->irr &= ~mask; |
| 951 |
if (delivery_mode == APIC_DM_EXTINT)
|
| 952 |
vector = pic_read_irq(isa_pic); |
| 953 |
else
|
| 954 |
vector = entry & 0xff;
|
| 955 |
|
| 956 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
| 957 |
apic_bus_deliver(deliver_bitmask, delivery_mode, |
| 958 |
vector, polarity, trig_mode); |
| 959 |
} |
| 960 |
} |
| 961 |
} |
| 962 |
} |
| 963 |
|
| 964 |
void ioapic_set_irq(void *opaque, int vector, int level) |
| 965 |
{
|
| 966 |
IOAPICState *s = opaque; |
| 967 |
|
| 968 |
/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
|
| 969 |
* to GSI 2. GSI maps to ioapic 1-1. This is not
|
| 970 |
* the cleanest way of doing it but it should work. */
|
| 971 |
|
| 972 |
if (vector == 0) |
| 973 |
vector = 2;
|
| 974 |
|
| 975 |
if (vector >= 0 && vector < IOAPIC_NUM_PINS) { |
| 976 |
uint32_t mask = 1 << vector;
|
| 977 |
uint64_t entry = s->ioredtbl[vector]; |
| 978 |
|
| 979 |
if ((entry >> 15) & 1) { |
| 980 |
/* level triggered */
|
| 981 |
if (level) {
|
| 982 |
s->irr |= mask; |
| 983 |
ioapic_service(s); |
| 984 |
} else {
|
| 985 |
s->irr &= ~mask; |
| 986 |
} |
| 987 |
} else {
|
| 988 |
/* edge triggered */
|
| 989 |
if (level) {
|
| 990 |
s->irr |= mask; |
| 991 |
ioapic_service(s); |
| 992 |
} |
| 993 |
} |
| 994 |
} |
| 995 |
} |
| 996 |
|
| 997 |
static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) |
| 998 |
{
|
| 999 |
IOAPICState *s = opaque; |
| 1000 |
int index;
|
| 1001 |
uint32_t val = 0;
|
| 1002 |
|
| 1003 |
addr &= 0xff;
|
| 1004 |
if (addr == 0x00) { |
| 1005 |
val = s->ioregsel; |
| 1006 |
} else if (addr == 0x10) { |
| 1007 |
switch (s->ioregsel) {
|
| 1008 |
case 0x00: |
| 1009 |
val = s->id << 24;
|
| 1010 |
break;
|
| 1011 |
case 0x01: |
| 1012 |
val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */ |
| 1013 |
break;
|
| 1014 |
case 0x02: |
| 1015 |
val = 0;
|
| 1016 |
break;
|
| 1017 |
default:
|
| 1018 |
index = (s->ioregsel - 0x10) >> 1; |
| 1019 |
if (index >= 0 && index < IOAPIC_NUM_PINS) { |
| 1020 |
if (s->ioregsel & 1) |
| 1021 |
val = s->ioredtbl[index] >> 32;
|
| 1022 |
else
|
| 1023 |
val = s->ioredtbl[index] & 0xffffffff;
|
| 1024 |
} |
| 1025 |
} |
| 1026 |
#ifdef DEBUG_IOAPIC
|
| 1027 |
printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
|
| 1028 |
#endif
|
| 1029 |
} |
| 1030 |
return val;
|
| 1031 |
} |
| 1032 |
|
| 1033 |
static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1034 |
{
|
| 1035 |
IOAPICState *s = opaque; |
| 1036 |
int index;
|
| 1037 |
|
| 1038 |
addr &= 0xff;
|
| 1039 |
if (addr == 0x00) { |
| 1040 |
s->ioregsel = val; |
| 1041 |
return;
|
| 1042 |
} else if (addr == 0x10) { |
| 1043 |
#ifdef DEBUG_IOAPIC
|
| 1044 |
printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
|
| 1045 |
#endif
|
| 1046 |
switch (s->ioregsel) {
|
| 1047 |
case 0x00: |
| 1048 |
s->id = (val >> 24) & 0xff; |
| 1049 |
return;
|
| 1050 |
case 0x01: |
| 1051 |
case 0x02: |
| 1052 |
return;
|
| 1053 |
default:
|
| 1054 |
index = (s->ioregsel - 0x10) >> 1; |
| 1055 |
if (index >= 0 && index < IOAPIC_NUM_PINS) { |
| 1056 |
if (s->ioregsel & 1) { |
| 1057 |
s->ioredtbl[index] &= 0xffffffff;
|
| 1058 |
s->ioredtbl[index] |= (uint64_t)val << 32;
|
| 1059 |
} else {
|
| 1060 |
s->ioredtbl[index] &= ~0xffffffffULL;
|
| 1061 |
s->ioredtbl[index] |= val; |
| 1062 |
} |
| 1063 |
ioapic_service(s); |
| 1064 |
} |
| 1065 |
} |
| 1066 |
} |
| 1067 |
} |
| 1068 |
|
| 1069 |
static void ioapic_save(QEMUFile *f, void *opaque) |
| 1070 |
{
|
| 1071 |
IOAPICState *s = opaque; |
| 1072 |
int i;
|
| 1073 |
|
| 1074 |
qemu_put_8s(f, &s->id); |
| 1075 |
qemu_put_8s(f, &s->ioregsel); |
| 1076 |
for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
| 1077 |
qemu_put_be64s(f, &s->ioredtbl[i]); |
| 1078 |
} |
| 1079 |
} |
| 1080 |
|
| 1081 |
static int ioapic_load(QEMUFile *f, void *opaque, int version_id) |
| 1082 |
{
|
| 1083 |
IOAPICState *s = opaque; |
| 1084 |
int i;
|
| 1085 |
|
| 1086 |
if (version_id != 1) |
| 1087 |
return -EINVAL;
|
| 1088 |
|
| 1089 |
qemu_get_8s(f, &s->id); |
| 1090 |
qemu_get_8s(f, &s->ioregsel); |
| 1091 |
for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
| 1092 |
qemu_get_be64s(f, &s->ioredtbl[i]); |
| 1093 |
} |
| 1094 |
return 0; |
| 1095 |
} |
| 1096 |
|
| 1097 |
static void ioapic_reset(void *opaque) |
| 1098 |
{
|
| 1099 |
IOAPICState *s = opaque; |
| 1100 |
int i;
|
| 1101 |
|
| 1102 |
memset(s, 0, sizeof(*s)); |
| 1103 |
for(i = 0; i < IOAPIC_NUM_PINS; i++) |
| 1104 |
s->ioredtbl[i] = 1 << 16; /* mask LVT */ |
| 1105 |
} |
| 1106 |
|
| 1107 |
static CPUReadMemoryFunc *ioapic_mem_read[3] = { |
| 1108 |
ioapic_mem_readl, |
| 1109 |
ioapic_mem_readl, |
| 1110 |
ioapic_mem_readl, |
| 1111 |
}; |
| 1112 |
|
| 1113 |
static CPUWriteMemoryFunc *ioapic_mem_write[3] = { |
| 1114 |
ioapic_mem_writel, |
| 1115 |
ioapic_mem_writel, |
| 1116 |
ioapic_mem_writel, |
| 1117 |
}; |
| 1118 |
|
| 1119 |
IOAPICState *ioapic_init(void)
|
| 1120 |
{
|
| 1121 |
IOAPICState *s; |
| 1122 |
int io_memory;
|
| 1123 |
|
| 1124 |
s = qemu_mallocz(sizeof(IOAPICState));
|
| 1125 |
ioapic_reset(s); |
| 1126 |
s->id = last_apic_id++; |
| 1127 |
|
| 1128 |
io_memory = cpu_register_io_memory(0, ioapic_mem_read,
|
| 1129 |
ioapic_mem_write, s); |
| 1130 |
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory); |
| 1131 |
|
| 1132 |
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s); |
| 1133 |
qemu_register_reset(ioapic_reset, s); |
| 1134 |
|
| 1135 |
return s;
|
| 1136 |
} |