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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "console.h" |
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#include "net.h" |
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#include "virtio-net.h" |
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|
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//#define DEBUG_PCI
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struct PCIBus {
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int bus_num;
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int devfn_min;
|
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pci_set_irq_fn set_irq; |
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pci_map_irq_fn map_irq; |
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uint32_t config_reg; /* XXX: suppress */
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/* low level pic */
|
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SetIRQFunc *low_set_irq; |
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qemu_irq *irq_opaque; |
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PCIDevice *devices[256];
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PCIDevice *parent_dev; |
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PCIBus *next; |
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int irq_count[];
|
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}; |
| 49 |
|
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static void pci_update_mappings(PCIDevice *d); |
| 51 |
static void pci_set_irq(void *opaque, int irq_num, int level); |
| 52 |
|
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target_phys_addr_t pci_mem_base; |
| 54 |
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
|
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
|
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static int pci_irq_index; |
| 57 |
static PCIBus *first_bus;
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|
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static void pcibus_save(QEMUFile *f, void *opaque) |
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{
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PCIBus *bus = (PCIBus *)opaque; |
| 62 |
int i;
|
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|
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qemu_put_be32(f, bus->nirq); |
| 65 |
for (i = 0; i < bus->nirq; i++) |
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qemu_put_be32(f, bus->irq_count[i]); |
| 67 |
} |
| 68 |
|
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static int pcibus_load(QEMUFile *f, void *opaque, int version_id) |
| 70 |
{
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PCIBus *bus = (PCIBus *)opaque; |
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int i, nirq;
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|
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if (version_id != 1) |
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return -EINVAL;
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|
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nirq = qemu_get_be32(f); |
| 78 |
if (bus->nirq != nirq) {
|
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fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
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nirq, bus->nirq); |
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return -EINVAL;
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} |
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|
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for (i = 0; i < nirq; i++) |
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bus->irq_count[i] = qemu_get_be32(f); |
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|
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return 0; |
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} |
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|
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PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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qemu_irq *pic, int devfn_min, int nirq) |
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{
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PCIBus *bus; |
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static int nbus = 0; |
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|
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bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int))); |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = pic; |
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bus->devfn_min = devfn_min; |
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bus->nirq = nirq; |
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first_bus = bus; |
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register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
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return bus;
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} |
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|
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static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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{
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(PCIBus));
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bus->map_irq = map_irq; |
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bus->parent_dev = dev; |
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bus->next = dev->bus->next; |
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dev->bus->next = bus; |
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return bus;
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} |
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int pci_bus_num(PCIBus *s)
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{
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return s->bus_num;
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} |
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{
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int i;
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qemu_put_be32(f, 2); /* PCI device version */ |
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qemu_put_buffer(f, s->config, 256);
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for (i = 0; i < 4; i++) |
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qemu_put_be32(f, s->irq_state[i]); |
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} |
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{
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uint32_t version_id; |
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int i;
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version_id = qemu_get_be32(f); |
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if (version_id > 2) |
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return -EINVAL;
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qemu_get_buffer(f, s->config, 256);
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pci_update_mappings(s); |
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|
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if (version_id >= 2) |
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for (i = 0; i < 4; i ++) |
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s->irq_state[i] = qemu_get_be32(f); |
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return 0; |
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} |
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|
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
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{
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uint16_t *id; |
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id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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id[1] = cpu_to_le16(pci_default_sub_device_id);
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return 0; |
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} |
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/* -1 for devfn means auto assign */
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PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
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int instance_size, int devfn, |
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PCIConfigReadFunc *config_read, |
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PCIConfigWriteFunc *config_write) |
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{
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PCIDevice *pci_dev; |
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|
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if (pci_irq_index >= PCI_DEVICES_MAX)
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return NULL; |
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|
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if (devfn < 0) { |
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for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
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if (!bus->devices[devfn])
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goto found;
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} |
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return NULL; |
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found: ;
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} |
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pci_dev = qemu_mallocz(instance_size); |
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pci_dev->bus = bus; |
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pci_dev->devfn = devfn; |
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
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pci_set_default_subsystem_id(pci_dev); |
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if (!config_read)
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config_read = pci_default_read_config; |
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if (!config_write)
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config_write = pci_default_write_config; |
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pci_dev->config_read = config_read; |
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pci_dev->config_write = config_write; |
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pci_dev->irq_index = pci_irq_index++; |
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bus->devices[devfn] = pci_dev; |
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pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
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return pci_dev;
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} |
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|
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void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func) |
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{
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PCIIORegion *r; |
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uint32_t addr; |
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if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
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return;
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r = &pci_dev->io_regions[region_num]; |
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r->addr = -1;
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r->size = size; |
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r->type = type; |
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r->map_func = map_func; |
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if (region_num == PCI_ROM_SLOT) {
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addr = 0x30;
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} else {
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addr = 0x10 + region_num * 4; |
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} |
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*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
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} |
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|
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static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
|
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{
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return addr + pci_mem_base;
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} |
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|
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static void pci_update_mappings(PCIDevice *d) |
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{
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PCIIORegion *r; |
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int cmd, i;
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uint32_t last_addr, new_addr, config_ofs; |
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|
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
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for(i = 0; i < PCI_NUM_REGIONS; i++) { |
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r = &d->io_regions[i]; |
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if (i == PCI_ROM_SLOT) {
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config_ofs = 0x30;
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} else {
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config_ofs = 0x10 + i * 4; |
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} |
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if (r->size != 0) { |
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
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config_ofs)); |
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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if (last_addr <= new_addr || new_addr == 0 || |
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last_addr >= 0x10000) {
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new_addr = -1;
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} |
| 252 |
} else {
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new_addr = -1;
|
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} |
| 255 |
} else {
|
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
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config_ofs)); |
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/* the ROM slot has a specific enable bit */
|
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if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
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goto no_mem_map;
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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/* XXX: as we cannot support really dynamic
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mappings, we handle specific values as invalid
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mappings. */
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if (last_addr <= new_addr || new_addr == 0 || |
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last_addr == -1) {
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new_addr = -1;
|
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} |
| 272 |
} else {
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no_mem_map:
|
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new_addr = -1;
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} |
| 276 |
} |
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/* now do the real mapping */
|
| 278 |
if (new_addr != r->addr) {
|
| 279 |
if (r->addr != -1) { |
| 280 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
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int class;
|
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/* NOTE: specific hack for IDE in PC case:
|
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only one byte must be mapped. */
|
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class = d->config[0x0a] | (d->config[0x0b] << 8); |
| 285 |
if (class == 0x0101 && r->size == 4) { |
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isa_unassign_ioport(r->addr + 2, 1); |
| 287 |
} else {
|
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isa_unassign_ioport(r->addr, r->size); |
| 289 |
} |
| 290 |
} else {
|
| 291 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
| 292 |
r->size, |
| 293 |
IO_MEM_UNASSIGNED); |
| 294 |
qemu_unregister_coalesced_mmio(r->addr, r->size); |
| 295 |
} |
| 296 |
} |
| 297 |
r->addr = new_addr; |
| 298 |
if (r->addr != -1) { |
| 299 |
r->map_func(d, i, r->addr, r->size, r->type); |
| 300 |
} |
| 301 |
} |
| 302 |
} |
| 303 |
} |
| 304 |
} |
| 305 |
|
| 306 |
uint32_t pci_default_read_config(PCIDevice *d, |
| 307 |
uint32_t address, int len)
|
| 308 |
{
|
| 309 |
uint32_t val; |
| 310 |
|
| 311 |
switch(len) {
|
| 312 |
default:
|
| 313 |
case 4: |
| 314 |
if (address <= 0xfc) { |
| 315 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
| 316 |
break;
|
| 317 |
} |
| 318 |
/* fall through */
|
| 319 |
case 2: |
| 320 |
if (address <= 0xfe) { |
| 321 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
| 322 |
break;
|
| 323 |
} |
| 324 |
/* fall through */
|
| 325 |
case 1: |
| 326 |
val = d->config[address]; |
| 327 |
break;
|
| 328 |
} |
| 329 |
return val;
|
| 330 |
} |
| 331 |
|
| 332 |
void pci_default_write_config(PCIDevice *d,
|
| 333 |
uint32_t address, uint32_t val, int len)
|
| 334 |
{
|
| 335 |
int can_write, i;
|
| 336 |
uint32_t end, addr; |
| 337 |
|
| 338 |
if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
| 339 |
(address >= 0x30 && address < 0x34))) { |
| 340 |
PCIIORegion *r; |
| 341 |
int reg;
|
| 342 |
|
| 343 |
if ( address >= 0x30 ) { |
| 344 |
reg = PCI_ROM_SLOT; |
| 345 |
}else{
|
| 346 |
reg = (address - 0x10) >> 2; |
| 347 |
} |
| 348 |
r = &d->io_regions[reg]; |
| 349 |
if (r->size == 0) |
| 350 |
goto default_config;
|
| 351 |
/* compute the stored value */
|
| 352 |
if (reg == PCI_ROM_SLOT) {
|
| 353 |
/* keep ROM enable bit */
|
| 354 |
val &= (~(r->size - 1)) | 1; |
| 355 |
} else {
|
| 356 |
val &= ~(r->size - 1);
|
| 357 |
val |= r->type; |
| 358 |
} |
| 359 |
*(uint32_t *)(d->config + address) = cpu_to_le32(val); |
| 360 |
pci_update_mappings(d); |
| 361 |
return;
|
| 362 |
} |
| 363 |
default_config:
|
| 364 |
/* not efficient, but simple */
|
| 365 |
addr = address; |
| 366 |
for(i = 0; i < len; i++) { |
| 367 |
/* default read/write accesses */
|
| 368 |
switch(d->config[0x0e]) { |
| 369 |
case 0x00: |
| 370 |
case 0x80: |
| 371 |
switch(addr) {
|
| 372 |
case 0x00: |
| 373 |
case 0x01: |
| 374 |
case 0x02: |
| 375 |
case 0x03: |
| 376 |
case 0x08: |
| 377 |
case 0x09: |
| 378 |
case 0x0a: |
| 379 |
case 0x0b: |
| 380 |
case 0x0e: |
| 381 |
case 0x10 ... 0x27: /* base */ |
| 382 |
case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
| 383 |
case 0x30 ... 0x33: /* rom */ |
| 384 |
case 0x3d: |
| 385 |
can_write = 0;
|
| 386 |
break;
|
| 387 |
default:
|
| 388 |
can_write = 1;
|
| 389 |
break;
|
| 390 |
} |
| 391 |
break;
|
| 392 |
default:
|
| 393 |
case 0x01: |
| 394 |
switch(addr) {
|
| 395 |
case 0x00: |
| 396 |
case 0x01: |
| 397 |
case 0x02: |
| 398 |
case 0x03: |
| 399 |
case 0x08: |
| 400 |
case 0x09: |
| 401 |
case 0x0a: |
| 402 |
case 0x0b: |
| 403 |
case 0x0e: |
| 404 |
case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
| 405 |
case 0x38 ... 0x3b: /* rom */ |
| 406 |
case 0x3d: |
| 407 |
can_write = 0;
|
| 408 |
break;
|
| 409 |
default:
|
| 410 |
can_write = 1;
|
| 411 |
break;
|
| 412 |
} |
| 413 |
break;
|
| 414 |
} |
| 415 |
if (can_write) {
|
| 416 |
/* Mask out writes to reserved bits in registers */
|
| 417 |
switch (addr) {
|
| 418 |
case 0x05: |
| 419 |
val &= ~PCI_COMMAND_RESERVED_MASK_HI; |
| 420 |
break;
|
| 421 |
case 0x06: |
| 422 |
val &= ~PCI_STATUS_RESERVED_MASK_LO; |
| 423 |
break;
|
| 424 |
case 0x07: |
| 425 |
val &= ~PCI_STATUS_RESERVED_MASK_HI; |
| 426 |
break;
|
| 427 |
} |
| 428 |
d->config[addr] = val; |
| 429 |
} |
| 430 |
if (++addr > 0xff) |
| 431 |
break;
|
| 432 |
val >>= 8;
|
| 433 |
} |
| 434 |
|
| 435 |
end = address + len; |
| 436 |
if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
| 437 |
/* if the command register is modified, we must modify the mappings */
|
| 438 |
pci_update_mappings(d); |
| 439 |
} |
| 440 |
} |
| 441 |
|
| 442 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
| 443 |
{
|
| 444 |
PCIBus *s = opaque; |
| 445 |
PCIDevice *pci_dev; |
| 446 |
int config_addr, bus_num;
|
| 447 |
|
| 448 |
#if defined(DEBUG_PCI) && 0 |
| 449 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
| 450 |
addr, val, len); |
| 451 |
#endif
|
| 452 |
bus_num = (addr >> 16) & 0xff; |
| 453 |
while (s && s->bus_num != bus_num)
|
| 454 |
s = s->next; |
| 455 |
if (!s)
|
| 456 |
return;
|
| 457 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
| 458 |
if (!pci_dev)
|
| 459 |
return;
|
| 460 |
config_addr = addr & 0xff;
|
| 461 |
#if defined(DEBUG_PCI)
|
| 462 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
| 463 |
pci_dev->name, config_addr, val, len); |
| 464 |
#endif
|
| 465 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
| 466 |
} |
| 467 |
|
| 468 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
| 469 |
{
|
| 470 |
PCIBus *s = opaque; |
| 471 |
PCIDevice *pci_dev; |
| 472 |
int config_addr, bus_num;
|
| 473 |
uint32_t val; |
| 474 |
|
| 475 |
bus_num = (addr >> 16) & 0xff; |
| 476 |
while (s && s->bus_num != bus_num)
|
| 477 |
s= s->next; |
| 478 |
if (!s)
|
| 479 |
goto fail;
|
| 480 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
| 481 |
if (!pci_dev) {
|
| 482 |
fail:
|
| 483 |
switch(len) {
|
| 484 |
case 1: |
| 485 |
val = 0xff;
|
| 486 |
break;
|
| 487 |
case 2: |
| 488 |
val = 0xffff;
|
| 489 |
break;
|
| 490 |
default:
|
| 491 |
case 4: |
| 492 |
val = 0xffffffff;
|
| 493 |
break;
|
| 494 |
} |
| 495 |
goto the_end;
|
| 496 |
} |
| 497 |
config_addr = addr & 0xff;
|
| 498 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
| 499 |
#if defined(DEBUG_PCI)
|
| 500 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
| 501 |
pci_dev->name, config_addr, val, len); |
| 502 |
#endif
|
| 503 |
the_end:
|
| 504 |
#if defined(DEBUG_PCI) && 0 |
| 505 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
| 506 |
addr, val, len); |
| 507 |
#endif
|
| 508 |
return val;
|
| 509 |
} |
| 510 |
|
| 511 |
/***********************************************************/
|
| 512 |
/* generic PCI irq support */
|
| 513 |
|
| 514 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
| 515 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
| 516 |
{
|
| 517 |
PCIDevice *pci_dev = (PCIDevice *)opaque; |
| 518 |
PCIBus *bus; |
| 519 |
int change;
|
| 520 |
|
| 521 |
change = level - pci_dev->irq_state[irq_num]; |
| 522 |
if (!change)
|
| 523 |
return;
|
| 524 |
|
| 525 |
pci_dev->irq_state[irq_num] = level; |
| 526 |
for (;;) {
|
| 527 |
bus = pci_dev->bus; |
| 528 |
irq_num = bus->map_irq(pci_dev, irq_num); |
| 529 |
if (bus->set_irq)
|
| 530 |
break;
|
| 531 |
pci_dev = bus->parent_dev; |
| 532 |
} |
| 533 |
bus->irq_count[irq_num] += change; |
| 534 |
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
| 535 |
} |
| 536 |
|
| 537 |
/***********************************************************/
|
| 538 |
/* monitor info on PCI */
|
| 539 |
|
| 540 |
typedef struct { |
| 541 |
uint16_t class; |
| 542 |
const char *desc; |
| 543 |
} pci_class_desc; |
| 544 |
|
| 545 |
static const pci_class_desc pci_class_descriptions[] = |
| 546 |
{
|
| 547 |
{ 0x0100, "SCSI controller"},
|
| 548 |
{ 0x0101, "IDE controller"},
|
| 549 |
{ 0x0102, "Floppy controller"},
|
| 550 |
{ 0x0103, "IPI controller"},
|
| 551 |
{ 0x0104, "RAID controller"},
|
| 552 |
{ 0x0106, "SATA controller"},
|
| 553 |
{ 0x0107, "SAS controller"},
|
| 554 |
{ 0x0180, "Storage controller"},
|
| 555 |
{ 0x0200, "Ethernet controller"},
|
| 556 |
{ 0x0201, "Token Ring controller"},
|
| 557 |
{ 0x0202, "FDDI controller"},
|
| 558 |
{ 0x0203, "ATM controller"},
|
| 559 |
{ 0x0280, "Network controller"},
|
| 560 |
{ 0x0300, "VGA controller"},
|
| 561 |
{ 0x0301, "XGA controller"},
|
| 562 |
{ 0x0302, "3D controller"},
|
| 563 |
{ 0x0380, "Display controller"},
|
| 564 |
{ 0x0400, "Video controller"},
|
| 565 |
{ 0x0401, "Audio controller"},
|
| 566 |
{ 0x0402, "Phone"},
|
| 567 |
{ 0x0480, "Multimedia controller"},
|
| 568 |
{ 0x0500, "RAM controller"},
|
| 569 |
{ 0x0501, "Flash controller"},
|
| 570 |
{ 0x0580, "Memory controller"},
|
| 571 |
{ 0x0600, "Host bridge"},
|
| 572 |
{ 0x0601, "ISA bridge"},
|
| 573 |
{ 0x0602, "EISA bridge"},
|
| 574 |
{ 0x0603, "MC bridge"},
|
| 575 |
{ 0x0604, "PCI bridge"},
|
| 576 |
{ 0x0605, "PCMCIA bridge"},
|
| 577 |
{ 0x0606, "NUBUS bridge"},
|
| 578 |
{ 0x0607, "CARDBUS bridge"},
|
| 579 |
{ 0x0608, "RACEWAY bridge"},
|
| 580 |
{ 0x0680, "Bridge"},
|
| 581 |
{ 0x0c03, "USB controller"},
|
| 582 |
{ 0, NULL}
|
| 583 |
}; |
| 584 |
|
| 585 |
static void pci_info_device(PCIDevice *d) |
| 586 |
{
|
| 587 |
int i, class;
|
| 588 |
PCIIORegion *r; |
| 589 |
const pci_class_desc *desc;
|
| 590 |
|
| 591 |
term_printf(" Bus %2d, device %3d, function %d:\n",
|
| 592 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
| 593 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
| 594 |
term_printf(" ");
|
| 595 |
desc = pci_class_descriptions; |
| 596 |
while (desc->desc && class != desc->class)
|
| 597 |
desc++; |
| 598 |
if (desc->desc) {
|
| 599 |
term_printf("%s", desc->desc);
|
| 600 |
} else {
|
| 601 |
term_printf("Class %04x", class);
|
| 602 |
} |
| 603 |
term_printf(": PCI device %04x:%04x\n",
|
| 604 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
| 605 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
| 606 |
|
| 607 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
| 608 |
term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
| 609 |
} |
| 610 |
if (class == 0x0604) { |
| 611 |
term_printf(" BUS %d.\n", d->config[0x19]); |
| 612 |
} |
| 613 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
| 614 |
r = &d->io_regions[i]; |
| 615 |
if (r->size != 0) { |
| 616 |
term_printf(" BAR%d: ", i);
|
| 617 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 618 |
term_printf("I/O at 0x%04x [0x%04x].\n",
|
| 619 |
r->addr, r->addr + r->size - 1);
|
| 620 |
} else {
|
| 621 |
term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
| 622 |
r->addr, r->addr + r->size - 1);
|
| 623 |
} |
| 624 |
} |
| 625 |
} |
| 626 |
if (class == 0x0604 && d->config[0x19] != 0) { |
| 627 |
pci_for_each_device(d->config[0x19], pci_info_device);
|
| 628 |
} |
| 629 |
} |
| 630 |
|
| 631 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
| 632 |
{
|
| 633 |
PCIBus *bus = first_bus; |
| 634 |
PCIDevice *d; |
| 635 |
int devfn;
|
| 636 |
|
| 637 |
while (bus && bus->bus_num != bus_num)
|
| 638 |
bus = bus->next; |
| 639 |
if (bus) {
|
| 640 |
for(devfn = 0; devfn < 256; devfn++) { |
| 641 |
d = bus->devices[devfn]; |
| 642 |
if (d)
|
| 643 |
fn(d); |
| 644 |
} |
| 645 |
} |
| 646 |
} |
| 647 |
|
| 648 |
void pci_info(void) |
| 649 |
{
|
| 650 |
pci_for_each_device(0, pci_info_device);
|
| 651 |
} |
| 652 |
|
| 653 |
static const char * const pci_nic_models[] = { |
| 654 |
"ne2k_pci",
|
| 655 |
"i82551",
|
| 656 |
"i82557b",
|
| 657 |
"i82559er",
|
| 658 |
"rtl8139",
|
| 659 |
"e1000",
|
| 660 |
"pcnet",
|
| 661 |
"virtio",
|
| 662 |
NULL
|
| 663 |
}; |
| 664 |
|
| 665 |
typedef void (*PCINICInitFn)(PCIBus *, NICInfo *, int); |
| 666 |
|
| 667 |
static PCINICInitFn pci_nic_init_fns[] = {
|
| 668 |
pci_ne2000_init, |
| 669 |
pci_i82551_init, |
| 670 |
pci_i82557b_init, |
| 671 |
pci_i82559er_init, |
| 672 |
pci_rtl8139_init, |
| 673 |
pci_e1000_init, |
| 674 |
pci_pcnet_init, |
| 675 |
virtio_net_init, |
| 676 |
NULL
|
| 677 |
}; |
| 678 |
|
| 679 |
/* Initialize a PCI NIC. */
|
| 680 |
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn, |
| 681 |
const char *default_model) |
| 682 |
{
|
| 683 |
int i;
|
| 684 |
|
| 685 |
qemu_check_nic_model_list(nd, pci_nic_models, default_model); |
| 686 |
|
| 687 |
for (i = 0; pci_nic_models[i]; i++) |
| 688 |
if (strcmp(nd->model, pci_nic_models[i]) == 0) |
| 689 |
pci_nic_init_fns[i](bus, nd, devfn); |
| 690 |
} |
| 691 |
|
| 692 |
typedef struct { |
| 693 |
PCIDevice dev; |
| 694 |
PCIBus *bus; |
| 695 |
} PCIBridge; |
| 696 |
|
| 697 |
static void pci_bridge_write_config(PCIDevice *d, |
| 698 |
uint32_t address, uint32_t val, int len)
|
| 699 |
{
|
| 700 |
PCIBridge *s = (PCIBridge *)d; |
| 701 |
|
| 702 |
if (address == 0x19 || (address == 0x18 && len > 1)) { |
| 703 |
if (address == 0x19) |
| 704 |
s->bus->bus_num = val & 0xff;
|
| 705 |
else
|
| 706 |
s->bus->bus_num = (val >> 8) & 0xff; |
| 707 |
#if defined(DEBUG_PCI)
|
| 708 |
printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
|
| 709 |
#endif
|
| 710 |
} |
| 711 |
pci_default_write_config(d, address, val, len); |
| 712 |
} |
| 713 |
|
| 714 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
| 715 |
pci_map_irq_fn map_irq, const char *name) |
| 716 |
{
|
| 717 |
PCIBridge *s; |
| 718 |
s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
| 719 |
devfn, NULL, pci_bridge_write_config);
|
| 720 |
|
| 721 |
pci_config_set_vendor_id(s->dev.config, vid); |
| 722 |
pci_config_set_device_id(s->dev.config, did); |
| 723 |
|
| 724 |
s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
| 725 |
s->dev.config[0x05] = 0x00; |
| 726 |
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
| 727 |
s->dev.config[0x07] = 0x00; // status = fast devsel |
| 728 |
s->dev.config[0x08] = 0x00; // revision |
| 729 |
s->dev.config[0x09] = 0x00; // programming i/f |
| 730 |
pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
| 731 |
s->dev.config[0x0D] = 0x10; // latency_timer |
| 732 |
s->dev.config[0x0E] = 0x81; // header_type |
| 733 |
s->dev.config[0x1E] = 0xa0; // secondary status |
| 734 |
|
| 735 |
s->bus = pci_register_secondary_bus(&s->dev, map_irq); |
| 736 |
return s->bus;
|
| 737 |
} |