root / hw / etraxfs_dma.c @ 492c30af
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/*
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* QEMU ETRAX DMA Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include <sys/time.h> |
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#include "hw.h" |
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "etraxfs_dma.h" |
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#define D(x)
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#define RW_DATA 0x0 |
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#define RW_SAVED_DATA 0x58 |
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#define RW_SAVED_DATA_BUF 0x5c |
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#define RW_GROUP 0x60 |
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#define RW_GROUP_DOWN 0x7c |
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#define RW_CMD 0x80 |
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#define RW_CFG 0x84 |
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#define RW_STAT 0x88 |
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#define RW_INTR_MASK 0x8c |
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#define RW_ACK_INTR 0x90 |
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#define R_INTR 0x94 |
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#define R_MASKED_INTR 0x98 |
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#define RW_STREAM_CMD 0x9c |
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#define DMA_REG_MAX 0x100 |
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/* descriptors */
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// ------------------------------------------------------------ dma_descr_group
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typedef struct dma_descr_group { |
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struct dma_descr_group *next;
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unsigned eol : 1; |
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unsigned tol : 1; |
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unsigned bol : 1; |
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unsigned : 1; |
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unsigned intr : 1; |
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unsigned : 2; |
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unsigned en : 1; |
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unsigned : 7; |
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unsigned dis : 1; |
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unsigned md : 16; |
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struct dma_descr_group *up;
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union {
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struct dma_descr_context *context;
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struct dma_descr_group *group;
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} down; |
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} dma_descr_group; |
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// ---------------------------------------------------------- dma_descr_context
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typedef struct dma_descr_context { |
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struct dma_descr_context *next;
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unsigned eol : 1; |
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unsigned : 3; |
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unsigned intr : 1; |
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unsigned : 1; |
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unsigned store_mode : 1; |
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unsigned en : 1; |
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unsigned : 7; |
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unsigned dis : 1; |
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unsigned md0 : 16; |
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unsigned md1;
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unsigned md2;
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unsigned md3;
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unsigned md4;
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struct dma_descr_data *saved_data;
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char *saved_data_buf;
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} dma_descr_context; |
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// ------------------------------------------------------------- dma_descr_data
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typedef struct dma_descr_data { |
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struct dma_descr_data *next;
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char *buf;
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unsigned eol : 1; |
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unsigned : 2; |
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unsigned out_eop : 1; |
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unsigned intr : 1; |
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unsigned wait : 1; |
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unsigned : 2; |
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unsigned : 3; |
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unsigned in_eop : 1; |
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unsigned : 4; |
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unsigned md : 16; |
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char *after;
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} dma_descr_data; |
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/* Constants */
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enum {
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regk_dma_ack_pkt = 0x00000100,
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regk_dma_anytime = 0x00000001,
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regk_dma_array = 0x00000008,
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regk_dma_burst = 0x00000020,
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regk_dma_client = 0x00000002,
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regk_dma_copy_next = 0x00000010,
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regk_dma_copy_up = 0x00000020,
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regk_dma_data_at_eol = 0x00000001,
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regk_dma_dis_c = 0x00000010,
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regk_dma_dis_g = 0x00000020,
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regk_dma_idle = 0x00000001,
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regk_dma_intern = 0x00000004,
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regk_dma_load_c = 0x00000200,
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regk_dma_load_c_n = 0x00000280,
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regk_dma_load_c_next = 0x00000240,
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regk_dma_load_d = 0x00000140,
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regk_dma_load_g = 0x00000300,
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regk_dma_load_g_down = 0x000003c0,
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regk_dma_load_g_next = 0x00000340,
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regk_dma_load_g_up = 0x00000380,
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regk_dma_next_en = 0x00000010,
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regk_dma_next_pkt = 0x00000010,
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regk_dma_no = 0x00000000,
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regk_dma_only_at_wait = 0x00000000,
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regk_dma_restore = 0x00000020,
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regk_dma_rst = 0x00000001,
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regk_dma_running = 0x00000004,
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regk_dma_rw_cfg_default = 0x00000000,
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regk_dma_rw_cmd_default = 0x00000000,
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regk_dma_rw_intr_mask_default = 0x00000000,
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regk_dma_rw_stat_default = 0x00000101,
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regk_dma_rw_stream_cmd_default = 0x00000000,
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regk_dma_save_down = 0x00000020,
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regk_dma_save_up = 0x00000020,
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regk_dma_set_reg = 0x00000050,
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regk_dma_set_w_size1 = 0x00000190,
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regk_dma_set_w_size2 = 0x000001a0,
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regk_dma_set_w_size4 = 0x000001c0,
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regk_dma_stopped = 0x00000002,
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regk_dma_store_c = 0x00000002,
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regk_dma_store_descr = 0x00000000,
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regk_dma_store_g = 0x00000004,
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regk_dma_store_md = 0x00000001,
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regk_dma_sw = 0x00000008,
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regk_dma_update_down = 0x00000020,
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regk_dma_yes = 0x00000001
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}; |
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enum dma_ch_state
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{
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RST = 1,
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STOPPED = 2,
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RUNNING = 4
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}; |
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struct fs_dma_channel
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{
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int regmap;
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qemu_irq *irq; |
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struct etraxfs_dma_client *client;
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/* Internal status. */
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int stream_cmd_src;
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enum dma_ch_state state;
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unsigned int input : 1; |
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unsigned int eol : 1; |
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struct dma_descr_group current_g;
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struct dma_descr_context current_c;
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struct dma_descr_data current_d;
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/* Controll registers. */
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uint32_t regs[DMA_REG_MAX]; |
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}; |
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struct fs_dma_ctrl
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{
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CPUState *env; |
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target_phys_addr_t base; |
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int nr_channels;
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struct fs_dma_channel *channels;
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QEMUBH *bh; |
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}; |
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static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) |
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{
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return ctrl->channels[c].regs[reg];
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} |
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static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) |
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{
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return channel_reg(ctrl, c, RW_CFG) & 2; |
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} |
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static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) |
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{
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return (channel_reg(ctrl, c, RW_CFG) & 1) |
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&& ctrl->channels[c].client; |
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} |
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static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr) |
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{
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/* Every channel has a 0x2000 ctrl register map. */
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return (addr - base) >> 13; |
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); |
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_g,
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sizeof ctrl->channels[c].current_g);
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} |
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static void dump_c(int ch, struct dma_descr_context *c) |
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{
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%p\n", c->next);
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printf("saved_data=%p\n", c->saved_data);
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printf("saved_data_buf=%p\n", c->saved_data_buf);
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printf("eol=%x\n", (uint32_t) c->eol);
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} |
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static void dump_d(int ch, struct dma_descr_data *d) |
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{
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%p\n", d->next);
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printf("buf=%p\n", d->buf);
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printf("after=%p\n", d->after);
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printf("intr=%x\n", (uint32_t) d->intr);
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printf("out_eop=%x\n", (uint32_t) d->out_eop);
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printf("in_eop=%x\n", (uint32_t) d->in_eop);
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printf("eol=%x\n", (uint32_t) d->eol);
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} |
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#endif
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static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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D(dump_c(c, &ctrl->channels[c].current_c)); |
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/* I guess this should update the current pos. */
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ctrl->channels[c].regs[RW_SAVED_DATA] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
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} |
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static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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ctrl->channels[c].regs[RW_DATA] = addr; |
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} |
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static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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cpu_physical_memory_write (addr, |
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
|
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} |
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_write (addr, |
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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} |
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static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) |
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{
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/* FIXME: */
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} |
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static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) |
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{
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if (ctrl->channels[c].client)
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{
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ctrl->channels[c].eol = 0;
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ctrl->channels[c].state = RUNNING; |
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} else
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printf("WARNING: starting DMA ch %d with no client\n", c);
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} |
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|
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static void channel_continue(struct fs_dma_ctrl *ctrl, int c) |
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{
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if (!channel_en(ctrl, c)
|
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|| channel_stopped(ctrl, c) |
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|| ctrl->channels[c].state != RUNNING |
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/* Only reload the current data descriptor if it has eol set. */
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|| !ctrl->channels[c].current_d.eol) {
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D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
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c, ctrl->channels[c].state, |
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channel_stopped(ctrl, c), |
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channel_en(ctrl,c), |
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ctrl->channels[c].eol)); |
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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return;
|
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} |
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|
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/* Reload the current descriptor. */
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channel_load_d(ctrl, c); |
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|
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/* If the current descriptor cleared the eol flag and we had already
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reached eol state, do the continue. */
|
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if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
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D(printf("continue %d ok %p\n", c,
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ctrl->channels[c].current_d.next)); |
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ctrl->channels[c].regs[RW_SAVED_DATA] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
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channel_load_d(ctrl, c); |
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channel_start(ctrl, c); |
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} |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
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} |
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|
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static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) |
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{
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unsigned int cmd = v & ((1 << 10) - 1); |
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|
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D(printf("%s ch=%d cmd=%x\n",
|
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__func__, c, cmd)); |
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if (cmd & regk_dma_load_d) {
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channel_load_d(ctrl, c); |
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if (cmd & regk_dma_burst)
|
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channel_start(ctrl, c); |
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} |
| 367 |
|
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if (cmd & regk_dma_load_c) {
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channel_load_c(ctrl, c); |
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channel_start(ctrl, c); |
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} |
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} |
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|
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static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) |
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{
|
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D(printf("%s %d\n", __func__, c));
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ctrl->channels[c].regs[R_INTR] &= |
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~(ctrl->channels[c].regs[RW_ACK_INTR]); |
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|
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ctrl->channels[c].regs[R_MASKED_INTR] = |
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ctrl->channels[c].regs[R_INTR] |
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& ctrl->channels[c].regs[RW_INTR_MASK]; |
| 383 |
|
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D(printf("%s: chan=%d masked_intr=%x\n", __func__,
|
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c, |
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ctrl->channels[c].regs[R_MASKED_INTR])); |
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|
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if (ctrl->channels[c].regs[R_MASKED_INTR])
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qemu_irq_raise(ctrl->channels[c].irq[0]);
|
| 390 |
else
|
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qemu_irq_lower(ctrl->channels[c].irq[0]);
|
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} |
| 393 |
|
| 394 |
static void channel_out_run(struct fs_dma_ctrl *ctrl, int c) |
| 395 |
{
|
| 396 |
uint32_t len; |
| 397 |
uint32_t saved_data_buf; |
| 398 |
unsigned char buf[2 * 1024]; |
| 399 |
|
| 400 |
while (ctrl->channels[c].eol != 1) { |
| 401 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
| 402 |
|
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D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
|
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c, |
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(uint32_t)ctrl->channels[c].current_d.buf, |
| 406 |
(uint32_t)ctrl->channels[c].current_d.after, |
| 407 |
saved_data_buf)); |
| 408 |
|
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len = (uint32_t)ctrl->channels[c].current_d.after; |
| 410 |
len -= saved_data_buf; |
| 411 |
|
| 412 |
if (len > sizeof buf) |
| 413 |
len = sizeof buf;
|
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cpu_physical_memory_read (saved_data_buf, buf, len); |
| 415 |
|
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D(printf("channel %d pushes %x %u bytes\n", c,
|
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saved_data_buf, len)); |
| 418 |
|
| 419 |
if (ctrl->channels[c].client->client.push)
|
| 420 |
ctrl->channels[c].client->client.push( |
| 421 |
ctrl->channels[c].client->client.opaque, |
| 422 |
buf, len); |
| 423 |
else
|
| 424 |
printf("WARNING: DMA ch%d dataloss,"
|
| 425 |
" no attached client.\n", c);
|
| 426 |
|
| 427 |
saved_data_buf += len; |
| 428 |
|
| 429 |
if (saved_data_buf ==
|
| 430 |
(uint32_t)ctrl->channels[c].current_d.after) {
|
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/* Done. Step to next. */
|
| 432 |
if (ctrl->channels[c].current_d.out_eop) {
|
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/* TODO: signal eop to the client. */
|
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D(printf("signal eop\n"));
|
| 435 |
} |
| 436 |
if (ctrl->channels[c].current_d.intr) {
|
| 437 |
/* TODO: signal eop to the client. */
|
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/* data intr. */
|
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D(printf("signal intr\n"));
|
| 440 |
ctrl->channels[c].regs[R_INTR] |= (1 << 2); |
| 441 |
channel_update_irq(ctrl, c); |
| 442 |
} |
| 443 |
if (ctrl->channels[c].current_d.eol) {
|
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D(printf("channel %d EOL\n", c));
|
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ctrl->channels[c].eol = 1;
|
| 446 |
|
| 447 |
/* Mark the context as disabled. */
|
| 448 |
ctrl->channels[c].current_c.dis = 1;
|
| 449 |
channel_store_c(ctrl, c); |
| 450 |
|
| 451 |
channel_stop(ctrl, c); |
| 452 |
} else {
|
| 453 |
ctrl->channels[c].regs[RW_SAVED_DATA] = |
| 454 |
(uint32_t)ctrl->channels[c].current_d.next; |
| 455 |
/* Load new descriptor. */
|
| 456 |
channel_load_d(ctrl, c); |
| 457 |
saved_data_buf = (uint32_t)(unsigned long) |
| 458 |
ctrl->channels[c].current_d.buf; |
| 459 |
} |
| 460 |
|
| 461 |
channel_store_d(ctrl, c); |
| 462 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
| 463 |
saved_data_buf; |
| 464 |
D(dump_d(c, &ctrl->channels[c].current_d)); |
| 465 |
} |
| 466 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
| 467 |
} |
| 468 |
} |
| 469 |
|
| 470 |
static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, |
| 471 |
unsigned char *buf, int buflen, int eop) |
| 472 |
{
|
| 473 |
uint32_t len; |
| 474 |
uint32_t saved_data_buf; |
| 475 |
|
| 476 |
if (ctrl->channels[c].eol == 1) |
| 477 |
return 0; |
| 478 |
|
| 479 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
| 480 |
len = (uint32_t)ctrl->channels[c].current_d.after; |
| 481 |
len -= saved_data_buf; |
| 482 |
|
| 483 |
if (len > buflen)
|
| 484 |
len = buflen; |
| 485 |
|
| 486 |
cpu_physical_memory_write (saved_data_buf, buf, len); |
| 487 |
saved_data_buf += len; |
| 488 |
|
| 489 |
if (saved_data_buf ==
|
| 490 |
(uint32_t)ctrl->channels[c].current_d.after |
| 491 |
|| eop) {
|
| 492 |
uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; |
| 493 |
|
| 494 |
D(printf("in dscr end len=%d\n",
|
| 495 |
ctrl->channels[c].current_d.after |
| 496 |
- ctrl->channels[c].current_d.buf)); |
| 497 |
ctrl->channels[c].current_d.after = |
| 498 |
(void *)(unsigned long) saved_data_buf; |
| 499 |
|
| 500 |
/* Done. Step to next. */
|
| 501 |
if (ctrl->channels[c].current_d.intr) {
|
| 502 |
/* TODO: signal eop to the client. */
|
| 503 |
/* data intr. */
|
| 504 |
ctrl->channels[c].regs[R_INTR] |= 3;
|
| 505 |
} |
| 506 |
if (eop) {
|
| 507 |
ctrl->channels[c].current_d.in_eop = 1;
|
| 508 |
ctrl->channels[c].regs[R_INTR] |= 8;
|
| 509 |
} |
| 510 |
if (r_intr != ctrl->channels[c].regs[R_INTR])
|
| 511 |
channel_update_irq(ctrl, c); |
| 512 |
|
| 513 |
channel_store_d(ctrl, c); |
| 514 |
D(dump_d(c, &ctrl->channels[c].current_d)); |
| 515 |
|
| 516 |
if (ctrl->channels[c].current_d.eol) {
|
| 517 |
D(printf("channel %d EOL\n", c));
|
| 518 |
ctrl->channels[c].eol = 1;
|
| 519 |
|
| 520 |
/* Mark the context as disabled. */
|
| 521 |
ctrl->channels[c].current_c.dis = 1;
|
| 522 |
channel_store_c(ctrl, c); |
| 523 |
|
| 524 |
channel_stop(ctrl, c); |
| 525 |
} else {
|
| 526 |
ctrl->channels[c].regs[RW_SAVED_DATA] = |
| 527 |
(uint32_t)ctrl->channels[c].current_d.next; |
| 528 |
/* Load new descriptor. */
|
| 529 |
channel_load_d(ctrl, c); |
| 530 |
saved_data_buf = (uint32_t) |
| 531 |
ctrl->channels[c].current_d.buf; |
| 532 |
} |
| 533 |
} |
| 534 |
|
| 535 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
| 536 |
return len;
|
| 537 |
} |
| 538 |
|
| 539 |
static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c) |
| 540 |
{
|
| 541 |
if (ctrl->channels[c].client->client.pull)
|
| 542 |
ctrl->channels[c].client->client.pull( |
| 543 |
ctrl->channels[c].client->client.opaque); |
| 544 |
} |
| 545 |
|
| 546 |
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) |
| 547 |
{
|
| 548 |
struct fs_dma_ctrl *ctrl = opaque;
|
| 549 |
CPUState *env = ctrl->env; |
| 550 |
cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
| 551 |
addr); |
| 552 |
return 0; |
| 553 |
} |
| 554 |
|
| 555 |
static uint32_t
|
| 556 |
dma_readl (void *opaque, target_phys_addr_t addr)
|
| 557 |
{
|
| 558 |
struct fs_dma_ctrl *ctrl = opaque;
|
| 559 |
int c;
|
| 560 |
uint32_t r = 0;
|
| 561 |
|
| 562 |
/* Make addr relative to this instances base. */
|
| 563 |
c = fs_channel(ctrl->base, addr); |
| 564 |
addr &= 0x1fff;
|
| 565 |
switch (addr)
|
| 566 |
{
|
| 567 |
case RW_STAT:
|
| 568 |
r = ctrl->channels[c].state & 7;
|
| 569 |
r |= ctrl->channels[c].eol << 5;
|
| 570 |
r |= ctrl->channels[c].stream_cmd_src << 8;
|
| 571 |
break;
|
| 572 |
|
| 573 |
default:
|
| 574 |
r = ctrl->channels[c].regs[addr]; |
| 575 |
D(printf ("%s c=%d addr=%x\n",
|
| 576 |
__func__, c, addr)); |
| 577 |
break;
|
| 578 |
} |
| 579 |
return r;
|
| 580 |
} |
| 581 |
|
| 582 |
static void |
| 583 |
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
| 584 |
{
|
| 585 |
struct fs_dma_ctrl *ctrl = opaque;
|
| 586 |
CPUState *env = ctrl->env; |
| 587 |
cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
| 588 |
addr); |
| 589 |
} |
| 590 |
|
| 591 |
static void |
| 592 |
dma_update_state(struct fs_dma_ctrl *ctrl, int c) |
| 593 |
{
|
| 594 |
if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) { |
| 595 |
if (ctrl->channels[c].regs[RW_CFG] & 2) |
| 596 |
ctrl->channels[c].state = STOPPED; |
| 597 |
if (!(ctrl->channels[c].regs[RW_CFG] & 1)) |
| 598 |
ctrl->channels[c].state = RST; |
| 599 |
} |
| 600 |
} |
| 601 |
|
| 602 |
static void |
| 603 |
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
| 604 |
{
|
| 605 |
struct fs_dma_ctrl *ctrl = opaque;
|
| 606 |
int c;
|
| 607 |
|
| 608 |
/* Make addr relative to this instances base. */
|
| 609 |
c = fs_channel(ctrl->base, addr); |
| 610 |
addr &= 0x1fff;
|
| 611 |
switch (addr)
|
| 612 |
{
|
| 613 |
case RW_DATA:
|
| 614 |
ctrl->channels[c].regs[addr] = value; |
| 615 |
break;
|
| 616 |
|
| 617 |
case RW_CFG:
|
| 618 |
ctrl->channels[c].regs[addr] = value; |
| 619 |
dma_update_state(ctrl, c); |
| 620 |
break;
|
| 621 |
case RW_CMD:
|
| 622 |
/* continue. */
|
| 623 |
if (value & ~1) |
| 624 |
printf("Invalid store to ch=%d RW_CMD %x\n",
|
| 625 |
c, value); |
| 626 |
ctrl->channels[c].regs[addr] = value; |
| 627 |
channel_continue(ctrl, c); |
| 628 |
break;
|
| 629 |
|
| 630 |
case RW_SAVED_DATA:
|
| 631 |
case RW_SAVED_DATA_BUF:
|
| 632 |
case RW_GROUP:
|
| 633 |
case RW_GROUP_DOWN:
|
| 634 |
ctrl->channels[c].regs[addr] = value; |
| 635 |
break;
|
| 636 |
|
| 637 |
case RW_ACK_INTR:
|
| 638 |
case RW_INTR_MASK:
|
| 639 |
ctrl->channels[c].regs[addr] = value; |
| 640 |
channel_update_irq(ctrl, c); |
| 641 |
if (addr == RW_ACK_INTR)
|
| 642 |
ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
| 643 |
break;
|
| 644 |
|
| 645 |
case RW_STREAM_CMD:
|
| 646 |
if (value & ~1023) |
| 647 |
printf("Invalid store to ch=%d "
|
| 648 |
"RW_STREAMCMD %x\n",
|
| 649 |
c, value); |
| 650 |
ctrl->channels[c].regs[addr] = value; |
| 651 |
D(printf("stream_cmd ch=%d\n", c));
|
| 652 |
channel_stream_cmd(ctrl, c, value); |
| 653 |
break;
|
| 654 |
|
| 655 |
default:
|
| 656 |
D(printf ("%s c=%d %x %x\n", __func__, c, addr));
|
| 657 |
break;
|
| 658 |
} |
| 659 |
} |
| 660 |
|
| 661 |
static CPUReadMemoryFunc *dma_read[] = {
|
| 662 |
&dma_rinvalid, |
| 663 |
&dma_rinvalid, |
| 664 |
&dma_readl, |
| 665 |
}; |
| 666 |
|
| 667 |
static CPUWriteMemoryFunc *dma_write[] = {
|
| 668 |
&dma_winvalid, |
| 669 |
&dma_winvalid, |
| 670 |
&dma_writel, |
| 671 |
}; |
| 672 |
|
| 673 |
void etraxfs_dmac_run(void *opaque) |
| 674 |
{
|
| 675 |
struct fs_dma_ctrl *ctrl = opaque;
|
| 676 |
int i;
|
| 677 |
int p = 0; |
| 678 |
|
| 679 |
for (i = 0; |
| 680 |
i < ctrl->nr_channels; |
| 681 |
i++) |
| 682 |
{
|
| 683 |
if (ctrl->channels[i].state == RUNNING)
|
| 684 |
{
|
| 685 |
p++; |
| 686 |
if (ctrl->channels[i].input)
|
| 687 |
channel_in_run(ctrl, i); |
| 688 |
else
|
| 689 |
channel_out_run(ctrl, i); |
| 690 |
} |
| 691 |
} |
| 692 |
} |
| 693 |
|
| 694 |
int etraxfs_dmac_input(struct etraxfs_dma_client *client, |
| 695 |
void *buf, int len, int eop) |
| 696 |
{
|
| 697 |
return channel_in_process(client->ctrl, client->channel,
|
| 698 |
buf, len, eop); |
| 699 |
} |
| 700 |
|
| 701 |
/* Connect an IRQ line with a channel. */
|
| 702 |
void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) |
| 703 |
{
|
| 704 |
struct fs_dma_ctrl *ctrl = opaque;
|
| 705 |
ctrl->channels[c].irq = line; |
| 706 |
ctrl->channels[c].input = input; |
| 707 |
} |
| 708 |
|
| 709 |
void etraxfs_dmac_connect_client(void *opaque, int c, |
| 710 |
struct etraxfs_dma_client *cl)
|
| 711 |
{
|
| 712 |
struct fs_dma_ctrl *ctrl = opaque;
|
| 713 |
cl->ctrl = ctrl; |
| 714 |
cl->channel = c; |
| 715 |
ctrl->channels[c].client = cl; |
| 716 |
} |
| 717 |
|
| 718 |
|
| 719 |
static void DMA_run(void *opaque) |
| 720 |
{
|
| 721 |
struct fs_dma_ctrl *etraxfs_dmac = opaque;
|
| 722 |
if (vm_running)
|
| 723 |
etraxfs_dmac_run(etraxfs_dmac); |
| 724 |
qemu_bh_schedule_idle(etraxfs_dmac->bh); |
| 725 |
} |
| 726 |
|
| 727 |
void *etraxfs_dmac_init(CPUState *env,
|
| 728 |
target_phys_addr_t base, int nr_channels)
|
| 729 |
{
|
| 730 |
struct fs_dma_ctrl *ctrl = NULL; |
| 731 |
int i;
|
| 732 |
|
| 733 |
ctrl = qemu_mallocz(sizeof *ctrl);
|
| 734 |
if (!ctrl)
|
| 735 |
return NULL; |
| 736 |
|
| 737 |
ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
| 738 |
qemu_bh_schedule_idle(ctrl->bh); |
| 739 |
|
| 740 |
ctrl->base = base; |
| 741 |
ctrl->env = env; |
| 742 |
ctrl->nr_channels = nr_channels; |
| 743 |
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); |
| 744 |
if (!ctrl->channels)
|
| 745 |
goto err;
|
| 746 |
|
| 747 |
for (i = 0; i < nr_channels; i++) |
| 748 |
{
|
| 749 |
ctrl->channels[i].regmap = cpu_register_io_memory(0,
|
| 750 |
dma_read, |
| 751 |
dma_write, |
| 752 |
ctrl); |
| 753 |
cpu_register_physical_memory (base + i * 0x2000,
|
| 754 |
sizeof ctrl->channels[i].regs,
|
| 755 |
ctrl->channels[i].regmap); |
| 756 |
} |
| 757 |
|
| 758 |
return ctrl;
|
| 759 |
err:
|
| 760 |
qemu_free(ctrl->channels); |
| 761 |
qemu_free(ctrl); |
| 762 |
return NULL; |
| 763 |
} |