25 |
25 |
#include "cpu.h"
|
26 |
26 |
#include "exec-all.h"
|
27 |
27 |
#include "disas.h"
|
|
28 |
#include "helper.h"
|
28 |
29 |
#include "tcg-op.h"
|
29 |
30 |
#include "qemu-common.h"
|
30 |
31 |
|
... | ... | |
44 |
45 |
};
|
45 |
46 |
|
46 |
47 |
static TCGv cpu_env;
|
|
48 |
static TCGv cpu_ir[31];
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|
49 |
static TCGv cpu_pc;
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|
50 |
|
|
51 |
static char cpu_reg_names[5*31];
|
47 |
52 |
|
48 |
53 |
#include "gen-icount.h"
|
49 |
54 |
|
50 |
55 |
static void alpha_translate_init(void)
|
51 |
56 |
{
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|
57 |
int i;
|
|
58 |
char *p;
|
52 |
59 |
static int done_init = 0;
|
|
60 |
|
53 |
61 |
if (done_init)
|
54 |
62 |
return;
|
|
63 |
|
55 |
64 |
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
|
65 |
|
|
66 |
p = cpu_reg_names;
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|
67 |
for (i = 0; i < 31; i++) {
|
|
68 |
sprintf(p, "ir%d", i);
|
|
69 |
cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
|
70 |
offsetof(CPUState, ir[i]), p);
|
|
71 |
p += 4;
|
|
72 |
}
|
|
73 |
|
|
74 |
cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
|
75 |
offsetof(CPUState, pc), "pc");
|
|
76 |
|
|
77 |
/* register helpers */
|
|
78 |
#undef DEF_HELPER
|
|
79 |
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
|
|
80 |
#include "helper.h"
|
|
81 |
|
56 |
82 |
done_init = 1;
|
57 |
83 |
}
|
58 |
84 |
|
... | ... | |
126 |
152 |
}
|
127 |
153 |
}
|
128 |
154 |
|
|
155 |
static inline void get_ir (TCGv t, int reg)
|
|
156 |
{
|
|
157 |
if (reg == 31)
|
|
158 |
tcg_gen_movi_i64(t, 0);
|
|
159 |
else
|
|
160 |
tcg_gen_mov_i64(t, cpu_ir[reg]);
|
|
161 |
}
|
|
162 |
|
|
163 |
static inline void set_ir (TCGv t, int reg)
|
|
164 |
{
|
|
165 |
if (reg != 31)
|
|
166 |
tcg_gen_mov_i64(cpu_ir[reg], t);
|
|
167 |
}
|
|
168 |
|
129 |
169 |
/* FIR moves */
|
130 |
170 |
/* Special hacks for fir31 */
|
131 |
171 |
#define gen_op_load_FT0_fir31 gen_op_reset_FT0
|
... | ... | |
354 |
394 |
}
|
355 |
395 |
}
|
356 |
396 |
|
357 |
|
static always_inline void gen_update_pc (DisasContext *ctx)
|
358 |
|
{
|
359 |
|
if (!(ctx->pc >> 32)) {
|
360 |
|
gen_op_update_pc32(ctx->pc);
|
361 |
|
} else {
|
362 |
|
#if 0 // Qemu does not know how to do this...
|
363 |
|
gen_op_update_pc(ctx->pc);
|
364 |
|
#else
|
365 |
|
gen_op_update_pc(ctx->pc >> 32, ctx->pc);
|
366 |
|
#endif
|
367 |
|
}
|
368 |
|
}
|
369 |
|
|
370 |
397 |
static always_inline void _gen_op_bcond (DisasContext *ctx)
|
371 |
398 |
{
|
372 |
399 |
#if 0 // Qemu does not know how to do this...
|
... | ... | |
379 |
406 |
static always_inline void gen_excp (DisasContext *ctx,
|
380 |
407 |
int exception, int error_code)
|
381 |
408 |
{
|
382 |
|
gen_update_pc(ctx);
|
|
409 |
tcg_gen_movi_i64(cpu_pc, ctx->pc);
|
383 |
410 |
gen_op_excp(exception, error_code);
|
384 |
411 |
}
|
385 |
412 |
|
... | ... | |
700 |
727 |
goto invalid_opc;
|
701 |
728 |
case 0x08:
|
702 |
729 |
/* LDA */
|
703 |
|
gen_load_ir(ctx, rb, 0);
|
704 |
|
gen_set_sT1(ctx, disp16);
|
705 |
|
gen_op_addq();
|
706 |
|
gen_store_ir(ctx, ra, 0);
|
|
730 |
{
|
|
731 |
TCGv v = tcg_const_i64(disp16);
|
|
732 |
if (rb != 31)
|
|
733 |
tcg_gen_add_i64(v, cpu_ir[rb], v);
|
|
734 |
set_ir(v, ra);
|
|
735 |
tcg_temp_free(v);
|
|
736 |
}
|
707 |
737 |
break;
|
708 |
738 |
case 0x09:
|
709 |
739 |
/* LDAH */
|
710 |
|
gen_load_ir(ctx, rb, 0);
|
711 |
|
gen_set_sT1(ctx, disp16 << 16);
|
712 |
|
gen_op_addq();
|
713 |
|
gen_store_ir(ctx, ra, 0);
|
|
740 |
{
|
|
741 |
TCGv v = tcg_const_i64(disp16 << 16);
|
|
742 |
if (rb != 31)
|
|
743 |
tcg_gen_add_i64(v, cpu_ir[rb], v);
|
|
744 |
set_ir(v, ra);
|
|
745 |
tcg_temp_free(v);
|
|
746 |
}
|
714 |
747 |
break;
|
715 |
748 |
case 0x0A:
|
716 |
749 |
/* LDBU */
|
... | ... | |
1871 |
1904 |
break;
|
1872 |
1905 |
case 0x30:
|
1873 |
1906 |
/* BR */
|
1874 |
|
gen_set_uT0(ctx, ctx->pc);
|
1875 |
|
gen_store_ir(ctx, ra, 0);
|
1876 |
|
if (disp21 != 0) {
|
1877 |
|
gen_set_sT1(ctx, disp21 << 2);
|
1878 |
|
gen_op_addq();
|
|
1907 |
if (ra != 31) {
|
|
1908 |
TCGv t = tcg_const_i64(ctx->pc);
|
|
1909 |
set_ir(t, ra);
|
|
1910 |
tcg_temp_free(t);
|
1879 |
1911 |
}
|
1880 |
|
gen_op_branch();
|
|
1912 |
tcg_gen_movi_i64(cpu_pc, ctx->pc + (disp21 << 2));
|
1881 |
1913 |
ret = 1;
|
1882 |
1914 |
break;
|
1883 |
1915 |
case 0x31:
|
... | ... | |
2056 |
2088 |
#endif
|
2057 |
2089 |
}
|
2058 |
2090 |
if (ret != 1 && ret != 3) {
|
2059 |
|
gen_update_pc(&ctx);
|
|
2091 |
tcg_gen_movi_i64(cpu_pc, ctx.pc);
|
2060 |
2092 |
}
|
2061 |
2093 |
#if defined (DO_TB_FLUSH)
|
2062 |
|
gen_op_tb_flush();
|
|
2094 |
tcg_gen_helper_0_0(helper_tb_flush);
|
2063 |
2095 |
#endif
|
2064 |
2096 |
if (tb->cflags & CF_LAST_IO)
|
2065 |
2097 |
gen_io_end();
|