Revision 496cb5b9 target-alpha/translate.c

b/target-alpha/translate.c
25 25
#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "helper.h"
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#include "tcg-op.h"
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#include "qemu-common.h"
30 31

  
......
44 45
};
45 46

  
46 47
static TCGv cpu_env;
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static TCGv cpu_ir[31];
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static TCGv cpu_pc;
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51
static char cpu_reg_names[5*31];
47 52

  
48 53
#include "gen-icount.h"
49 54

  
50 55
static void alpha_translate_init(void)
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{
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    int i;
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    char *p;
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    static int done_init = 0;
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53 61
    if (done_init)
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        return;
63

  
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    cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
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    p = cpu_reg_names;
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    for (i = 0; i < 31; i++) {
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        sprintf(p, "ir%d", i);
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        cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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                                       offsetof(CPUState, ir[i]), p);
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        p += 4;
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    }
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    cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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                                offsetof(CPUState, pc), "pc");
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    /* register helpers */
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#undef DEF_HELPER
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#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
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#include "helper.h"
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56 82
    done_init = 1;
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}
58 84

  
......
126 152
    }
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}
128 154

  
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static inline void get_ir (TCGv t, int reg)
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{
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    if (reg == 31)
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        tcg_gen_movi_i64(t, 0);
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    else
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        tcg_gen_mov_i64(t, cpu_ir[reg]);
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}
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static inline void set_ir (TCGv t, int reg)
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{
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    if (reg != 31)
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        tcg_gen_mov_i64(cpu_ir[reg], t);
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}
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129 169
/* FIR moves */
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/* Special hacks for fir31 */
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#define gen_op_load_FT0_fir31 gen_op_reset_FT0
......
354 394
    }
355 395
}
356 396

  
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static always_inline void gen_update_pc (DisasContext *ctx)
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{
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    if (!(ctx->pc >> 32)) {
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        gen_op_update_pc32(ctx->pc);
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    } else {
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#if 0 // Qemu does not know how to do this...
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        gen_op_update_pc(ctx->pc);
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#else
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        gen_op_update_pc(ctx->pc >> 32, ctx->pc);
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#endif
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    }
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}
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370 397
static always_inline void _gen_op_bcond (DisasContext *ctx)
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{
372 399
#if 0 // Qemu does not know how to do this...
......
379 406
static always_inline void gen_excp (DisasContext *ctx,
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                                    int exception, int error_code)
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{
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    gen_update_pc(ctx);
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    tcg_gen_movi_i64(cpu_pc, ctx->pc);
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    gen_op_excp(exception, error_code);
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}
385 412

  
......
700 727
        goto invalid_opc;
701 728
    case 0x08:
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        /* LDA */
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        gen_load_ir(ctx, rb, 0);
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        gen_set_sT1(ctx, disp16);
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        gen_op_addq();
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        gen_store_ir(ctx, ra, 0);
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        {
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            TCGv v = tcg_const_i64(disp16);
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            if (rb != 31)
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                tcg_gen_add_i64(v, cpu_ir[rb], v);
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            set_ir(v, ra);
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            tcg_temp_free(v);
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        }
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        break;
708 738
    case 0x09:
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        /* LDAH */
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        gen_load_ir(ctx, rb, 0);
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        gen_set_sT1(ctx, disp16 << 16);
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        gen_op_addq();
713
        gen_store_ir(ctx, ra, 0);
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        {
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            TCGv v = tcg_const_i64(disp16 << 16);
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            if (rb != 31)
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                tcg_gen_add_i64(v, cpu_ir[rb], v);
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            set_ir(v, ra);
745
            tcg_temp_free(v);
746
        }
714 747
        break;
715 748
    case 0x0A:
716 749
        /* LDBU */
......
1871 1904
        break;
1872 1905
    case 0x30:
1873 1906
        /* BR */
1874
        gen_set_uT0(ctx, ctx->pc);
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        gen_store_ir(ctx, ra, 0);
1876
        if (disp21 != 0) {
1877
            gen_set_sT1(ctx, disp21 << 2);
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            gen_op_addq();
1907
        if (ra != 31) {
1908
            TCGv t = tcg_const_i64(ctx->pc);
1909
            set_ir(t, ra);
1910
            tcg_temp_free(t);
1879 1911
        }
1880
        gen_op_branch();
1912
        tcg_gen_movi_i64(cpu_pc, ctx->pc + (disp21 << 2));
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        ret = 1;
1882 1914
        break;
1883 1915
    case 0x31:
......
2056 2088
#endif
2057 2089
    }
2058 2090
    if (ret != 1 && ret != 3) {
2059
        gen_update_pc(&ctx);
2091
        tcg_gen_movi_i64(cpu_pc, ctx.pc);
2060 2092
    }
2061 2093
#if defined (DO_TB_FLUSH)
2062
    gen_op_tb_flush();
2094
    tcg_gen_helper_0_0(helper_tb_flush);
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#endif
2064 2096
    if (tb->cflags & CF_LAST_IO)
2065 2097
        gen_io_end();

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