Statistics
| Branch: | Revision:

root / hw / pci.c @ 49823868

History | View | Annotate | Download (56.5 kB)

1
/*
2
 * QEMU PCI bus manager
3
 *
4
 * Copyright (c) 2004 Fabrice Bellard
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "pci.h"
26
#include "monitor.h"
27
#include "net.h"
28
#include "sysemu.h"
29
#include "loader.h"
30
#include "qemu-objects.h"
31

    
32
//#define DEBUG_PCI
33
#ifdef DEBUG_PCI
34
# define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
35
#else
36
# define PCI_DPRINTF(format, ...)       do { } while (0)
37
#endif
38

    
39
struct PCIBus {
40
    BusState qbus;
41
    int devfn_min;
42
    pci_set_irq_fn set_irq;
43
    pci_map_irq_fn map_irq;
44
    pci_hotplug_fn hotplug;
45
    DeviceState *hotplug_qdev;
46
    void *irq_opaque;
47
    PCIDevice *devices[256];
48
    PCIDevice *parent_dev;
49
    target_phys_addr_t mem_base;
50

    
51
    QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
52
    QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
53

    
54
    /* The bus IRQ state is the logical OR of the connected devices.
55
       Keep a count of the number of devices with raised IRQs.  */
56
    int nirq;
57
    int *irq_count;
58
};
59

    
60
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
61
static char *pcibus_get_dev_path(DeviceState *dev);
62

    
63
static struct BusInfo pci_bus_info = {
64
    .name       = "PCI",
65
    .size       = sizeof(PCIBus),
66
    .print_dev  = pcibus_dev_print,
67
    .get_dev_path = pcibus_get_dev_path,
68
    .props      = (Property[]) {
69
        DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
70
        DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
71
        DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
72
        DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
73
                        QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
74
        DEFINE_PROP_END_OF_LIST()
75
    }
76
};
77

    
78
static void pci_update_mappings(PCIDevice *d);
79
static void pci_set_irq(void *opaque, int irq_num, int level);
80
static int pci_add_option_rom(PCIDevice *pdev);
81
static void pci_del_option_rom(PCIDevice *pdev);
82

    
83
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
84
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
85

    
86
struct PCIHostBus {
87
    int domain;
88
    struct PCIBus *bus;
89
    QLIST_ENTRY(PCIHostBus) next;
90
};
91
static QLIST_HEAD(, PCIHostBus) host_buses;
92

    
93
static const VMStateDescription vmstate_pcibus = {
94
    .name = "PCIBUS",
95
    .version_id = 1,
96
    .minimum_version_id = 1,
97
    .minimum_version_id_old = 1,
98
    .fields      = (VMStateField []) {
99
        VMSTATE_INT32_EQUAL(nirq, PCIBus),
100
        VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
101
        VMSTATE_END_OF_LIST()
102
    }
103
};
104

    
105
static int pci_bar(PCIDevice *d, int reg)
106
{
107
    uint8_t type;
108

    
109
    if (reg != PCI_ROM_SLOT)
110
        return PCI_BASE_ADDRESS_0 + reg * 4;
111

    
112
    type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
113
    return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
114
}
115

    
116
static inline int pci_irq_state(PCIDevice *d, int irq_num)
117
{
118
        return (d->irq_state >> irq_num) & 0x1;
119
}
120

    
121
static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
122
{
123
        d->irq_state &= ~(0x1 << irq_num);
124
        d->irq_state |= level << irq_num;
125
}
126

    
127
static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
128
{
129
    PCIBus *bus;
130
    for (;;) {
131
        bus = pci_dev->bus;
132
        irq_num = bus->map_irq(pci_dev, irq_num);
133
        if (bus->set_irq)
134
            break;
135
        pci_dev = bus->parent_dev;
136
    }
137
    bus->irq_count[irq_num] += change;
138
    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
139
}
140

    
141
/* Update interrupt status bit in config space on interrupt
142
 * state change. */
143
static void pci_update_irq_status(PCIDevice *dev)
144
{
145
    if (dev->irq_state) {
146
        dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
147
    } else {
148
        dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
149
    }
150
}
151

    
152
static void pci_device_reset(PCIDevice *dev)
153
{
154
    int r;
155

    
156
    dev->irq_state = 0;
157
    pci_update_irq_status(dev);
158
    dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
159
                                  PCI_COMMAND_MASTER);
160
    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
161
    dev->config[PCI_INTERRUPT_LINE] = 0x0;
162
    for (r = 0; r < PCI_NUM_REGIONS; ++r) {
163
        if (!dev->io_regions[r].size) {
164
            continue;
165
        }
166
        pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
167
    }
168
    pci_update_mappings(dev);
169
}
170

    
171
static void pci_bus_reset(void *opaque)
172
{
173
    PCIBus *bus = opaque;
174
    int i;
175

    
176
    for (i = 0; i < bus->nirq; i++) {
177
        bus->irq_count[i] = 0;
178
    }
179
    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
180
        if (bus->devices[i]) {
181
            pci_device_reset(bus->devices[i]);
182
        }
183
    }
184
}
185

    
186
static void pci_host_bus_register(int domain, PCIBus *bus)
187
{
188
    struct PCIHostBus *host;
189
    host = qemu_mallocz(sizeof(*host));
190
    host->domain = domain;
191
    host->bus = bus;
192
    QLIST_INSERT_HEAD(&host_buses, host, next);
193
}
194

    
195
PCIBus *pci_find_root_bus(int domain)
196
{
197
    struct PCIHostBus *host;
198

    
199
    QLIST_FOREACH(host, &host_buses, next) {
200
        if (host->domain == domain) {
201
            return host->bus;
202
        }
203
    }
204

    
205
    return NULL;
206
}
207

    
208
int pci_find_domain(const PCIBus *bus)
209
{
210
    PCIDevice *d;
211
    struct PCIHostBus *host;
212

    
213
    /* obtain root bus */
214
    while ((d = bus->parent_dev) != NULL) {
215
        bus = d->bus;
216
    }
217

    
218
    QLIST_FOREACH(host, &host_buses, next) {
219
        if (host->bus == bus) {
220
            return host->domain;
221
        }
222
    }
223

    
224
    abort();    /* should not be reached */
225
    return -1;
226
}
227

    
228
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
229
                         const char *name, int devfn_min)
230
{
231
    qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
232
    assert(PCI_FUNC(devfn_min) == 0);
233
    bus->devfn_min = devfn_min;
234

    
235
    /* host bridge */
236
    QLIST_INIT(&bus->child);
237
    pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
238

    
239
    vmstate_register(NULL, -1, &vmstate_pcibus, bus);
240
    qemu_register_reset(pci_bus_reset, bus);
241
}
242

    
243
PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
244
{
245
    PCIBus *bus;
246

    
247
    bus = qemu_mallocz(sizeof(*bus));
248
    bus->qbus.qdev_allocated = 1;
249
    pci_bus_new_inplace(bus, parent, name, devfn_min);
250
    return bus;
251
}
252

    
253
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
254
                  void *irq_opaque, int nirq)
255
{
256
    bus->set_irq = set_irq;
257
    bus->map_irq = map_irq;
258
    bus->irq_opaque = irq_opaque;
259
    bus->nirq = nirq;
260
    bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
261
}
262

    
263
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
264
{
265
    bus->qbus.allow_hotplug = 1;
266
    bus->hotplug = hotplug;
267
    bus->hotplug_qdev = qdev;
268
}
269

    
270
void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
271
{
272
    bus->mem_base = base;
273
}
274

    
275
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
276
                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
277
                         void *irq_opaque, int devfn_min, int nirq)
278
{
279
    PCIBus *bus;
280

    
281
    bus = pci_bus_new(parent, name, devfn_min);
282
    pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
283
    return bus;
284
}
285

    
286
static void pci_register_secondary_bus(PCIBus *parent,
287
                                       PCIBus *bus,
288
                                       PCIDevice *dev,
289
                                       pci_map_irq_fn map_irq,
290
                                       const char *name)
291
{
292
    qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
293
    bus->map_irq = map_irq;
294
    bus->parent_dev = dev;
295

    
296
    QLIST_INIT(&bus->child);
297
    QLIST_INSERT_HEAD(&parent->child, bus, sibling);
298
}
299

    
300
static void pci_unregister_secondary_bus(PCIBus *bus)
301
{
302
    assert(QLIST_EMPTY(&bus->child));
303
    QLIST_REMOVE(bus, sibling);
304
}
305

    
306
int pci_bus_num(PCIBus *s)
307
{
308
    if (!s->parent_dev)
309
        return 0;       /* pci host bridge */
310
    return s->parent_dev->config[PCI_SECONDARY_BUS];
311
}
312

    
313
static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
314
{
315
    PCIDevice *s = container_of(pv, PCIDevice, config);
316
    uint8_t *config;
317
    int i;
318

    
319
    assert(size == pci_config_size(s));
320
    config = qemu_malloc(size);
321

    
322
    qemu_get_buffer(f, config, size);
323
    for (i = 0; i < size; ++i) {
324
        if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
325
            qemu_free(config);
326
            return -EINVAL;
327
        }
328
    }
329
    memcpy(s->config, config, size);
330

    
331
    pci_update_mappings(s);
332

    
333
    qemu_free(config);
334
    return 0;
335
}
336

    
337
/* just put buffer */
338
static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
339
{
340
    const uint8_t **v = pv;
341
    assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
342
    qemu_put_buffer(f, *v, size);
343
}
344

    
345
static VMStateInfo vmstate_info_pci_config = {
346
    .name = "pci config",
347
    .get  = get_pci_config_device,
348
    .put  = put_pci_config_device,
349
};
350

    
351
static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
352
{
353
    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
354
    uint32_t irq_state[PCI_NUM_PINS];
355
    int i;
356
    for (i = 0; i < PCI_NUM_PINS; ++i) {
357
        irq_state[i] = qemu_get_be32(f);
358
        if (irq_state[i] != 0x1 && irq_state[i] != 0) {
359
            fprintf(stderr, "irq state %d: must be 0 or 1.\n",
360
                    irq_state[i]);
361
            return -EINVAL;
362
        }
363
    }
364

    
365
    for (i = 0; i < PCI_NUM_PINS; ++i) {
366
        pci_set_irq_state(s, i, irq_state[i]);
367
    }
368

    
369
    return 0;
370
}
371

    
372
static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
373
{
374
    int i;
375
    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
376

    
377
    for (i = 0; i < PCI_NUM_PINS; ++i) {
378
        qemu_put_be32(f, pci_irq_state(s, i));
379
    }
380
}
381

    
382
static VMStateInfo vmstate_info_pci_irq_state = {
383
    .name = "pci irq state",
384
    .get  = get_pci_irq_state,
385
    .put  = put_pci_irq_state,
386
};
387

    
388
const VMStateDescription vmstate_pci_device = {
389
    .name = "PCIDevice",
390
    .version_id = 2,
391
    .minimum_version_id = 1,
392
    .minimum_version_id_old = 1,
393
    .fields      = (VMStateField []) {
394
        VMSTATE_INT32_LE(version_id, PCIDevice),
395
        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
396
                                   vmstate_info_pci_config,
397
                                   PCI_CONFIG_SPACE_SIZE),
398
        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
399
                                   vmstate_info_pci_irq_state,
400
                                   PCI_NUM_PINS * sizeof(int32_t)),
401
        VMSTATE_END_OF_LIST()
402
    }
403
};
404

    
405
const VMStateDescription vmstate_pcie_device = {
406
    .name = "PCIDevice",
407
    .version_id = 2,
408
    .minimum_version_id = 1,
409
    .minimum_version_id_old = 1,
410
    .fields      = (VMStateField []) {
411
        VMSTATE_INT32_LE(version_id, PCIDevice),
412
        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
413
                                   vmstate_info_pci_config,
414
                                   PCIE_CONFIG_SPACE_SIZE),
415
        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
416
                                   vmstate_info_pci_irq_state,
417
                                   PCI_NUM_PINS * sizeof(int32_t)),
418
        VMSTATE_END_OF_LIST()
419
    }
420
};
421

    
422
static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
423
{
424
    return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
425
}
426

    
427
void pci_device_save(PCIDevice *s, QEMUFile *f)
428
{
429
    /* Clear interrupt status bit: it is implicit
430
     * in irq_state which we are saving.
431
     * This makes us compatible with old devices
432
     * which never set or clear this bit. */
433
    s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
434
    vmstate_save_state(f, pci_get_vmstate(s), s);
435
    /* Restore the interrupt status bit. */
436
    pci_update_irq_status(s);
437
}
438

    
439
int pci_device_load(PCIDevice *s, QEMUFile *f)
440
{
441
    int ret;
442
    ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
443
    /* Restore the interrupt status bit. */
444
    pci_update_irq_status(s);
445
    return ret;
446
}
447

    
448
static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
449
{
450
    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
451
                 pci_default_sub_vendor_id);
452
    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
453
                 pci_default_sub_device_id);
454
}
455

    
456
/*
457
 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
458
 */
459
static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
460
{
461
    const char *p;
462
    char *e;
463
    unsigned long val;
464
    unsigned long dom = 0, bus = 0;
465
    unsigned slot = 0;
466

    
467
    p = addr;
468
    val = strtoul(p, &e, 16);
469
    if (e == p)
470
        return -1;
471
    if (*e == ':') {
472
        bus = val;
473
        p = e + 1;
474
        val = strtoul(p, &e, 16);
475
        if (e == p)
476
            return -1;
477
        if (*e == ':') {
478
            dom = bus;
479
            bus = val;
480
            p = e + 1;
481
            val = strtoul(p, &e, 16);
482
            if (e == p)
483
                return -1;
484
        }
485
    }
486

    
487
    if (dom > 0xffff || bus > 0xff || val > 0x1f)
488
        return -1;
489

    
490
    slot = val;
491

    
492
    if (*e)
493
        return -1;
494

    
495
    /* Note: QEMU doesn't implement domains other than 0 */
496
    if (!pci_find_bus(pci_find_root_bus(dom), bus))
497
        return -1;
498

    
499
    *domp = dom;
500
    *busp = bus;
501
    *slotp = slot;
502
    return 0;
503
}
504

    
505
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
506
                     unsigned *slotp)
507
{
508
    /* strip legacy tag */
509
    if (!strncmp(addr, "pci_addr=", 9)) {
510
        addr += 9;
511
    }
512
    if (pci_parse_devaddr(addr, domp, busp, slotp)) {
513
        monitor_printf(mon, "Invalid pci address\n");
514
        return -1;
515
    }
516
    return 0;
517
}
518

    
519
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
520
{
521
    int dom, bus;
522
    unsigned slot;
523

    
524
    if (!devaddr) {
525
        *devfnp = -1;
526
        return pci_find_bus(pci_find_root_bus(0), 0);
527
    }
528

    
529
    if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
530
        return NULL;
531
    }
532

    
533
    *devfnp = slot << 3;
534
    return pci_find_bus(pci_find_root_bus(dom), bus);
535
}
536

    
537
static void pci_init_cmask(PCIDevice *dev)
538
{
539
    pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
540
    pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
541
    dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
542
    dev->cmask[PCI_REVISION_ID] = 0xff;
543
    dev->cmask[PCI_CLASS_PROG] = 0xff;
544
    pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
545
    dev->cmask[PCI_HEADER_TYPE] = 0xff;
546
    dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
547
}
548

    
549
static void pci_init_wmask(PCIDevice *dev)
550
{
551
    int config_size = pci_config_size(dev);
552

    
553
    dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
554
    dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
555
    pci_set_word(dev->wmask + PCI_COMMAND,
556
                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
557
                 PCI_COMMAND_INTX_DISABLE);
558

    
559
    memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
560
           config_size - PCI_CONFIG_HEADER_SIZE);
561
}
562

    
563
static void pci_init_wmask_bridge(PCIDevice *d)
564
{
565
    /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
566
       PCI_SEC_LETENCY_TIMER */
567
    memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
568

    
569
    /* base and limit */
570
    d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
571
    d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
572
    pci_set_word(d->wmask + PCI_MEMORY_BASE,
573
                 PCI_MEMORY_RANGE_MASK & 0xffff);
574
    pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
575
                 PCI_MEMORY_RANGE_MASK & 0xffff);
576
    pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
577
                 PCI_PREF_RANGE_MASK & 0xffff);
578
    pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
579
                 PCI_PREF_RANGE_MASK & 0xffff);
580

    
581
    /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
582
    memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
583

    
584
    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
585
}
586

    
587
static void pci_config_alloc(PCIDevice *pci_dev)
588
{
589
    int config_size = pci_config_size(pci_dev);
590

    
591
    pci_dev->config = qemu_mallocz(config_size);
592
    pci_dev->cmask = qemu_mallocz(config_size);
593
    pci_dev->wmask = qemu_mallocz(config_size);
594
    pci_dev->used = qemu_mallocz(config_size);
595
}
596

    
597
static void pci_config_free(PCIDevice *pci_dev)
598
{
599
    qemu_free(pci_dev->config);
600
    qemu_free(pci_dev->cmask);
601
    qemu_free(pci_dev->wmask);
602
    qemu_free(pci_dev->used);
603
}
604

    
605
/* -1 for devfn means auto assign */
606
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
607
                                         const char *name, int devfn,
608
                                         PCIConfigReadFunc *config_read,
609
                                         PCIConfigWriteFunc *config_write,
610
                                         bool is_bridge)
611
{
612
    if (devfn < 0) {
613
        for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
614
            devfn += PCI_FUNC_MAX) {
615
            if (!bus->devices[devfn])
616
                goto found;
617
        }
618
        error_report("PCI: no slot/function available for %s, all in use", name);
619
        return NULL;
620
    found: ;
621
    } else if (bus->devices[devfn]) {
622
        error_report("PCI: slot %d function %d not available for %s, in use by %s",
623
                     PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
624
        return NULL;
625
    }
626
    pci_dev->bus = bus;
627
    pci_dev->devfn = devfn;
628
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
629
    pci_dev->irq_state = 0;
630
    pci_config_alloc(pci_dev);
631

    
632
    if (!is_bridge) {
633
        pci_set_default_subsystem_id(pci_dev);
634
    }
635
    pci_init_cmask(pci_dev);
636
    pci_init_wmask(pci_dev);
637
    if (is_bridge) {
638
        pci_init_wmask_bridge(pci_dev);
639
    }
640

    
641
    if (!config_read)
642
        config_read = pci_default_read_config;
643
    if (!config_write)
644
        config_write = pci_default_write_config;
645
    pci_dev->config_read = config_read;
646
    pci_dev->config_write = config_write;
647
    bus->devices[devfn] = pci_dev;
648
    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
649
    pci_dev->version_id = 2; /* Current pci device vmstate version */
650
    return pci_dev;
651
}
652

    
653
static void do_pci_unregister_device(PCIDevice *pci_dev)
654
{
655
    qemu_free_irqs(pci_dev->irq);
656
    pci_dev->bus->devices[pci_dev->devfn] = NULL;
657
    pci_config_free(pci_dev);
658
}
659

    
660
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
661
                               int instance_size, int devfn,
662
                               PCIConfigReadFunc *config_read,
663
                               PCIConfigWriteFunc *config_write)
664
{
665
    PCIDevice *pci_dev;
666

    
667
    pci_dev = qemu_mallocz(instance_size);
668
    pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
669
                                     config_read, config_write,
670
                                     PCI_HEADER_TYPE_NORMAL);
671
    if (pci_dev == NULL) {
672
        hw_error("PCI: can't register device\n");
673
    }
674
    return pci_dev;
675
}
676

    
677
static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
678
                                          target_phys_addr_t addr)
679
{
680
    return addr + bus->mem_base;
681
}
682

    
683
static void pci_unregister_io_regions(PCIDevice *pci_dev)
684
{
685
    PCIIORegion *r;
686
    int i;
687

    
688
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
689
        r = &pci_dev->io_regions[i];
690
        if (!r->size || r->addr == PCI_BAR_UNMAPPED)
691
            continue;
692
        if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
693
            isa_unassign_ioport(r->addr, r->filtered_size);
694
        } else {
695
            cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
696
                                                         r->addr),
697
                                         r->filtered_size,
698
                                         IO_MEM_UNASSIGNED);
699
        }
700
    }
701
}
702

    
703
static int pci_unregister_device(DeviceState *dev)
704
{
705
    PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
706
    PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
707
    int ret = 0;
708

    
709
    if (info->exit)
710
        ret = info->exit(pci_dev);
711
    if (ret)
712
        return ret;
713

    
714
    pci_unregister_io_regions(pci_dev);
715
    pci_del_option_rom(pci_dev);
716
    do_pci_unregister_device(pci_dev);
717
    return 0;
718
}
719

    
720
void pci_register_bar(PCIDevice *pci_dev, int region_num,
721
                            pcibus_t size, int type,
722
                            PCIMapIORegionFunc *map_func)
723
{
724
    PCIIORegion *r;
725
    uint32_t addr;
726
    pcibus_t wmask;
727

    
728
    if ((unsigned int)region_num >= PCI_NUM_REGIONS)
729
        return;
730

    
731
    if (size & (size-1)) {
732
        fprintf(stderr, "ERROR: PCI region size must be pow2 "
733
                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
734
        exit(1);
735
    }
736

    
737
    r = &pci_dev->io_regions[region_num];
738
    r->addr = PCI_BAR_UNMAPPED;
739
    r->size = size;
740
    r->filtered_size = size;
741
    r->type = type;
742
    r->map_func = map_func;
743

    
744
    wmask = ~(size - 1);
745
    addr = pci_bar(pci_dev, region_num);
746
    if (region_num == PCI_ROM_SLOT) {
747
        /* ROM enable bit is writeable */
748
        wmask |= PCI_ROM_ADDRESS_ENABLE;
749
    }
750
    pci_set_long(pci_dev->config + addr, type);
751
    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
752
        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
753
        pci_set_quad(pci_dev->wmask + addr, wmask);
754
        pci_set_quad(pci_dev->cmask + addr, ~0ULL);
755
    } else {
756
        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
757
        pci_set_long(pci_dev->cmask + addr, 0xffffffff);
758
    }
759
}
760

    
761
static uint32_t pci_config_get_io_base(PCIDevice *d,
762
                                       uint32_t base, uint32_t base_upper16)
763
{
764
    uint32_t val;
765

    
766
    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
767
    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
768
        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
769
    }
770
    return val;
771
}
772

    
773
static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
774
{
775
    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
776
        << 16;
777
}
778

    
779
static pcibus_t pci_config_get_pref_base(PCIDevice *d,
780
                                         uint32_t base, uint32_t upper)
781
{
782
    pcibus_t tmp;
783
    pcibus_t val;
784

    
785
    tmp = (pcibus_t)pci_get_word(d->config + base);
786
    val = (tmp & PCI_PREF_RANGE_MASK) << 16;
787
    if (tmp & PCI_PREF_RANGE_TYPE_64) {
788
        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
789
    }
790
    return val;
791
}
792

    
793
static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
794
{
795
    pcibus_t base;
796
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
797
        base = pci_config_get_io_base(bridge,
798
                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);
799
    } else {
800
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
801
            base = pci_config_get_pref_base(
802
                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
803
        } else {
804
            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
805
        }
806
    }
807

    
808
    return base;
809
}
810

    
811
static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
812
{
813
    pcibus_t limit;
814
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
815
        limit = pci_config_get_io_base(bridge,
816
                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
817
        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
818
    } else {
819
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
820
            limit = pci_config_get_pref_base(
821
                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
822
        } else {
823
            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
824
        }
825
        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
826
    }
827
    return limit;
828
}
829

    
830
static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
831
                              uint8_t type)
832
{
833
    pcibus_t base = *addr;
834
    pcibus_t limit = *addr + *size - 1;
835
    PCIDevice *br;
836

    
837
    for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
838
        uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
839

    
840
        if (type & PCI_BASE_ADDRESS_SPACE_IO) {
841
            if (!(cmd & PCI_COMMAND_IO)) {
842
                goto no_map;
843
            }
844
        } else {
845
            if (!(cmd & PCI_COMMAND_MEMORY)) {
846
                goto no_map;
847
            }
848
        }
849

    
850
        base = MAX(base, pci_bridge_get_base(br, type));
851
        limit = MIN(limit, pci_bridge_get_limit(br, type));
852
    }
853

    
854
    if (base > limit) {
855
        goto no_map;
856
    }
857
    *addr = base;
858
    *size = limit - base + 1;
859
    return;
860
no_map:
861
    *addr = PCI_BAR_UNMAPPED;
862
    *size = 0;
863
}
864

    
865
static pcibus_t pci_bar_address(PCIDevice *d,
866
                                int reg, uint8_t type, pcibus_t size)
867
{
868
    pcibus_t new_addr, last_addr;
869
    int bar = pci_bar(d, reg);
870
    uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
871

    
872
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
873
        if (!(cmd & PCI_COMMAND_IO)) {
874
            return PCI_BAR_UNMAPPED;
875
        }
876
        new_addr = pci_get_long(d->config + bar) & ~(size - 1);
877
        last_addr = new_addr + size - 1;
878
        /* NOTE: we have only 64K ioports on PC */
879
        if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
880
            return PCI_BAR_UNMAPPED;
881
        }
882
        return new_addr;
883
    }
884

    
885
    if (!(cmd & PCI_COMMAND_MEMORY)) {
886
        return PCI_BAR_UNMAPPED;
887
    }
888
    if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
889
        new_addr = pci_get_quad(d->config + bar);
890
    } else {
891
        new_addr = pci_get_long(d->config + bar);
892
    }
893
    /* the ROM slot has a specific enable bit */
894
    if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
895
        return PCI_BAR_UNMAPPED;
896
    }
897
    new_addr &= ~(size - 1);
898
    last_addr = new_addr + size - 1;
899
    /* NOTE: we do not support wrapping */
900
    /* XXX: as we cannot support really dynamic
901
       mappings, we handle specific values as invalid
902
       mappings. */
903
    if (last_addr <= new_addr || new_addr == 0 ||
904
        last_addr == PCI_BAR_UNMAPPED) {
905
        return PCI_BAR_UNMAPPED;
906
    }
907

    
908
    /* Now pcibus_t is 64bit.
909
     * Check if 32 bit BAR wraps around explicitly.
910
     * Without this, PC ide doesn't work well.
911
     * TODO: remove this work around.
912
     */
913
    if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
914
        return PCI_BAR_UNMAPPED;
915
    }
916

    
917
    /*
918
     * OS is allowed to set BAR beyond its addressable
919
     * bits. For example, 32 bit OS can set 64bit bar
920
     * to >4G. Check it. TODO: we might need to support
921
     * it in the future for e.g. PAE.
922
     */
923
    if (last_addr >= TARGET_PHYS_ADDR_MAX) {
924
        return PCI_BAR_UNMAPPED;
925
    }
926

    
927
    return new_addr;
928
}
929

    
930
static void pci_update_mappings(PCIDevice *d)
931
{
932
    PCIIORegion *r;
933
    int i;
934
    pcibus_t new_addr, filtered_size;
935

    
936
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
937
        r = &d->io_regions[i];
938

    
939
        /* this region isn't registered */
940
        if (!r->size)
941
            continue;
942

    
943
        new_addr = pci_bar_address(d, i, r->type, r->size);
944

    
945
        /* bridge filtering */
946
        filtered_size = r->size;
947
        if (new_addr != PCI_BAR_UNMAPPED) {
948
            pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
949
        }
950

    
951
        /* This bar isn't changed */
952
        if (new_addr == r->addr && filtered_size == r->filtered_size)
953
            continue;
954

    
955
        /* now do the real mapping */
956
        if (r->addr != PCI_BAR_UNMAPPED) {
957
            if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
958
                int class;
959
                /* NOTE: specific hack for IDE in PC case:
960
                   only one byte must be mapped. */
961
                class = pci_get_word(d->config + PCI_CLASS_DEVICE);
962
                if (class == 0x0101 && r->size == 4) {
963
                    isa_unassign_ioport(r->addr + 2, 1);
964
                } else {
965
                    isa_unassign_ioport(r->addr, r->filtered_size);
966
                }
967
            } else {
968
                cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
969
                                             r->filtered_size,
970
                                             IO_MEM_UNASSIGNED);
971
                qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
972
            }
973
        }
974
        r->addr = new_addr;
975
        r->filtered_size = filtered_size;
976
        if (r->addr != PCI_BAR_UNMAPPED) {
977
            /*
978
             * TODO: currently almost all the map funcions assumes
979
             * filtered_size == size and addr & ~(size - 1) == addr.
980
             * However with bridge filtering, they aren't always true.
981
             * Teach them such cases, such that filtered_size < size and
982
             * addr & (size - 1) != 0.
983
             */
984
            if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
985
                r->map_func(d, i, r->addr, r->filtered_size, r->type);
986
            } else {
987
                r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
988
                            r->filtered_size, r->type);
989
            }
990
        }
991
    }
992
}
993

    
994
static inline int pci_irq_disabled(PCIDevice *d)
995
{
996
    return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
997
}
998

    
999
/* Called after interrupt disabled field update in config space,
1000
 * assert/deassert interrupts if necessary.
1001
 * Gets original interrupt disable bit value (before update). */
1002
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1003
{
1004
    int i, disabled = pci_irq_disabled(d);
1005
    if (disabled == was_irq_disabled)
1006
        return;
1007
    for (i = 0; i < PCI_NUM_PINS; ++i) {
1008
        int state = pci_irq_state(d, i);
1009
        pci_change_irq_level(d, i, disabled ? -state : state);
1010
    }
1011
}
1012

    
1013
uint32_t pci_default_read_config(PCIDevice *d,
1014
                                 uint32_t address, int len)
1015
{
1016
    uint32_t val = 0;
1017
    assert(len == 1 || len == 2 || len == 4);
1018
    len = MIN(len, pci_config_size(d) - address);
1019
    memcpy(&val, d->config + address, len);
1020
    return le32_to_cpu(val);
1021
}
1022

    
1023
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1024
{
1025
    int i, was_irq_disabled = pci_irq_disabled(d);
1026
    uint32_t config_size = pci_config_size(d);
1027

    
1028
    for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1029
        uint8_t wmask = d->wmask[addr + i];
1030
        d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1031
    }
1032
    if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1033
        ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1034
        ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1035
        range_covers_byte(addr, l, PCI_COMMAND))
1036
        pci_update_mappings(d);
1037

    
1038
    if (range_covers_byte(addr, l, PCI_COMMAND))
1039
        pci_update_irq_disabled(d, was_irq_disabled);
1040
}
1041

    
1042
/***********************************************************/
1043
/* generic PCI irq support */
1044

    
1045
/* 0 <= irq_num <= 3. level must be 0 or 1 */
1046
static void pci_set_irq(void *opaque, int irq_num, int level)
1047
{
1048
    PCIDevice *pci_dev = opaque;
1049
    int change;
1050

    
1051
    change = level - pci_irq_state(pci_dev, irq_num);
1052
    if (!change)
1053
        return;
1054

    
1055
    pci_set_irq_state(pci_dev, irq_num, level);
1056
    pci_update_irq_status(pci_dev);
1057
    if (pci_irq_disabled(pci_dev))
1058
        return;
1059
    pci_change_irq_level(pci_dev, irq_num, change);
1060
}
1061

    
1062
/***********************************************************/
1063
/* monitor info on PCI */
1064

    
1065
typedef struct {
1066
    uint16_t class;
1067
    const char *desc;
1068
} pci_class_desc;
1069

    
1070
static const pci_class_desc pci_class_descriptions[] =
1071
{
1072
    { 0x0100, "SCSI controller"},
1073
    { 0x0101, "IDE controller"},
1074
    { 0x0102, "Floppy controller"},
1075
    { 0x0103, "IPI controller"},
1076
    { 0x0104, "RAID controller"},
1077
    { 0x0106, "SATA controller"},
1078
    { 0x0107, "SAS controller"},
1079
    { 0x0180, "Storage controller"},
1080
    { 0x0200, "Ethernet controller"},
1081
    { 0x0201, "Token Ring controller"},
1082
    { 0x0202, "FDDI controller"},
1083
    { 0x0203, "ATM controller"},
1084
    { 0x0280, "Network controller"},
1085
    { 0x0300, "VGA controller"},
1086
    { 0x0301, "XGA controller"},
1087
    { 0x0302, "3D controller"},
1088
    { 0x0380, "Display controller"},
1089
    { 0x0400, "Video controller"},
1090
    { 0x0401, "Audio controller"},
1091
    { 0x0402, "Phone"},
1092
    { 0x0480, "Multimedia controller"},
1093
    { 0x0500, "RAM controller"},
1094
    { 0x0501, "Flash controller"},
1095
    { 0x0580, "Memory controller"},
1096
    { 0x0600, "Host bridge"},
1097
    { 0x0601, "ISA bridge"},
1098
    { 0x0602, "EISA bridge"},
1099
    { 0x0603, "MC bridge"},
1100
    { 0x0604, "PCI bridge"},
1101
    { 0x0605, "PCMCIA bridge"},
1102
    { 0x0606, "NUBUS bridge"},
1103
    { 0x0607, "CARDBUS bridge"},
1104
    { 0x0608, "RACEWAY bridge"},
1105
    { 0x0680, "Bridge"},
1106
    { 0x0c03, "USB controller"},
1107
    { 0, NULL}
1108
};
1109

    
1110
static void pci_for_each_device_under_bus(PCIBus *bus,
1111
                                          void (*fn)(PCIBus *b, PCIDevice *d))
1112
{
1113
    PCIDevice *d;
1114
    int devfn;
1115

    
1116
    for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1117
        d = bus->devices[devfn];
1118
        if (d) {
1119
            fn(bus, d);
1120
        }
1121
    }
1122
}
1123

    
1124
void pci_for_each_device(PCIBus *bus, int bus_num,
1125
                         void (*fn)(PCIBus *b, PCIDevice *d))
1126
{
1127
    bus = pci_find_bus(bus, bus_num);
1128

    
1129
    if (bus) {
1130
        pci_for_each_device_under_bus(bus, fn);
1131
    }
1132
}
1133

    
1134
static void pci_device_print(Monitor *mon, QDict *device)
1135
{
1136
    QDict *qdict;
1137
    QListEntry *entry;
1138
    uint64_t addr, size;
1139

    
1140
    monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1141
    monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1142
                        qdict_get_int(device, "slot"),
1143
                        qdict_get_int(device, "function"));
1144
    monitor_printf(mon, "    ");
1145

    
1146
    qdict = qdict_get_qdict(device, "class_info");
1147
    if (qdict_haskey(qdict, "desc")) {
1148
        monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1149
    } else {
1150
        monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1151
    }
1152

    
1153
    qdict = qdict_get_qdict(device, "id");
1154
    monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1155
                        qdict_get_int(qdict, "device"),
1156
                        qdict_get_int(qdict, "vendor"));
1157

    
1158
    if (qdict_haskey(device, "irq")) {
1159
        monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1160
                            qdict_get_int(device, "irq"));
1161
    }
1162

    
1163
    if (qdict_haskey(device, "pci_bridge")) {
1164
        QDict *info;
1165

    
1166
        qdict = qdict_get_qdict(device, "pci_bridge");
1167

    
1168
        info = qdict_get_qdict(qdict, "bus");
1169
        monitor_printf(mon, "      BUS %" PRId64 ".\n",
1170
                            qdict_get_int(info, "number"));
1171
        monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1172
                            qdict_get_int(info, "secondary"));
1173
        monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1174
                            qdict_get_int(info, "subordinate"));
1175

    
1176
        info = qdict_get_qdict(qdict, "io_range");
1177
        monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1178
                       qdict_get_int(info, "base"),
1179
                       qdict_get_int(info, "limit"));
1180

    
1181
        info = qdict_get_qdict(qdict, "memory_range");
1182
        monitor_printf(mon,
1183
                       "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1184
                       qdict_get_int(info, "base"),
1185
                       qdict_get_int(info, "limit"));
1186

    
1187
        info = qdict_get_qdict(qdict, "prefetchable_range");
1188
        monitor_printf(mon, "      prefetchable memory range "
1189
                       "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1190
                       qdict_get_int(info, "base"),
1191
        qdict_get_int(info, "limit"));
1192
    }
1193

    
1194
    QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1195
        qdict = qobject_to_qdict(qlist_entry_obj(entry));
1196
        monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1197

    
1198
        addr = qdict_get_int(qdict, "address");
1199
        size = qdict_get_int(qdict, "size");
1200

    
1201
        if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1202
            monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1203
                                " [0x%04"FMT_PCIBUS"].\n",
1204
                                addr, addr + size - 1);
1205
        } else {
1206
            monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1207
                               " [0x%08"FMT_PCIBUS"].\n",
1208
                                qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1209
                                qdict_get_bool(qdict, "prefetch") ?
1210
                                " prefetchable" : "", addr, addr + size - 1);
1211
        }
1212
    }
1213

    
1214
    monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1215

    
1216
    if (qdict_haskey(device, "pci_bridge")) {
1217
        qdict = qdict_get_qdict(device, "pci_bridge");
1218
        if (qdict_haskey(qdict, "devices")) {
1219
            QListEntry *dev;
1220
            QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1221
                pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1222
            }
1223
        }
1224
    }
1225
}
1226

    
1227
void do_pci_info_print(Monitor *mon, const QObject *data)
1228
{
1229
    QListEntry *bus, *dev;
1230

    
1231
    QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1232
        QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1233
        QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1234
            pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1235
        }
1236
    }
1237
}
1238

    
1239
static QObject *pci_get_dev_class(const PCIDevice *dev)
1240
{
1241
    int class;
1242
    const pci_class_desc *desc;
1243

    
1244
    class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1245
    desc = pci_class_descriptions;
1246
    while (desc->desc && class != desc->class)
1247
        desc++;
1248

    
1249
    if (desc->desc) {
1250
        return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1251
                                  desc->desc, class);
1252
    } else {
1253
        return qobject_from_jsonf("{ 'class': %d }", class);
1254
    }
1255
}
1256

    
1257
static QObject *pci_get_dev_id(const PCIDevice *dev)
1258
{
1259
    return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1260
                              pci_get_word(dev->config + PCI_VENDOR_ID),
1261
                              pci_get_word(dev->config + PCI_DEVICE_ID));
1262
}
1263

    
1264
static QObject *pci_get_regions_list(const PCIDevice *dev)
1265
{
1266
    int i;
1267
    QList *regions_list;
1268

    
1269
    regions_list = qlist_new();
1270

    
1271
    for (i = 0; i < PCI_NUM_REGIONS; i++) {
1272
        QObject *obj;
1273
        const PCIIORegion *r = &dev->io_regions[i];
1274

    
1275
        if (!r->size) {
1276
            continue;
1277
        }
1278

    
1279
        if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1280
            obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1281
                                     "'address': %" PRId64 ", "
1282
                                     "'size': %" PRId64 " }",
1283
                                     i, r->addr, r->size);
1284
        } else {
1285
            int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1286

    
1287
            obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1288
                                     "'mem_type_64': %i, 'prefetch': %i, "
1289
                                     "'address': %" PRId64 ", "
1290
                                     "'size': %" PRId64 " }",
1291
                                     i, mem_type_64,
1292
                                     r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1293
                                     r->addr, r->size);
1294
        }
1295

    
1296
        qlist_append_obj(regions_list, obj);
1297
    }
1298

    
1299
    return QOBJECT(regions_list);
1300
}
1301

    
1302
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1303

    
1304
static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1305
{
1306
    uint8_t type;
1307
    QObject *obj;
1308

    
1309
    obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1310
                              " 'qdev_id': %s }",
1311
                              bus_num,
1312
                              PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1313
                              pci_get_dev_class(dev), pci_get_dev_id(dev),
1314
                              pci_get_regions_list(dev),
1315
                              dev->qdev.id ? dev->qdev.id : "");
1316

    
1317
    if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1318
        QDict *qdict = qobject_to_qdict(obj);
1319
        qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1320
    }
1321

    
1322
    type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1323
    if (type == PCI_HEADER_TYPE_BRIDGE) {
1324
        QDict *qdict;
1325
        QObject *pci_bridge;
1326

    
1327
        pci_bridge = qobject_from_jsonf("{ 'bus': "
1328
        "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1329
        "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1330
        "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1331
        "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1332
        dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1333
        dev->config[PCI_SUBORDINATE_BUS],
1334
        pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1335
        pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1336
        pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1337
        pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1338
        pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1339
                               PCI_BASE_ADDRESS_MEM_PREFETCH),
1340
        pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1341
                                PCI_BASE_ADDRESS_MEM_PREFETCH));
1342

    
1343
        if (dev->config[PCI_SECONDARY_BUS] != 0) {
1344
            PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1345

    
1346
            if (child_bus) {
1347
                qdict = qobject_to_qdict(pci_bridge);
1348
                qdict_put_obj(qdict, "devices",
1349
                              pci_get_devices_list(child_bus,
1350
                                                   dev->config[PCI_SECONDARY_BUS]));
1351
            }
1352
        }
1353
        qdict = qobject_to_qdict(obj);
1354
        qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1355
    }
1356

    
1357
    return obj;
1358
}
1359

    
1360
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1361
{
1362
    int devfn;
1363
    PCIDevice *dev;
1364
    QList *dev_list;
1365

    
1366
    dev_list = qlist_new();
1367

    
1368
    for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1369
        dev = bus->devices[devfn];
1370
        if (dev) {
1371
            qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1372
        }
1373
    }
1374

    
1375
    return QOBJECT(dev_list);
1376
}
1377

    
1378
static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1379
{
1380
    bus = pci_find_bus(bus, bus_num);
1381
    if (bus) {
1382
        return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1383
                                  bus_num, pci_get_devices_list(bus, bus_num));
1384
    }
1385

    
1386
    return NULL;
1387
}
1388

    
1389
void do_pci_info(Monitor *mon, QObject **ret_data)
1390
{
1391
    QList *bus_list;
1392
    struct PCIHostBus *host;
1393

    
1394
    bus_list = qlist_new();
1395

    
1396
    QLIST_FOREACH(host, &host_buses, next) {
1397
        QObject *obj = pci_get_bus_dict(host->bus, 0);
1398
        if (obj) {
1399
            qlist_append_obj(bus_list, obj);
1400
        }
1401
    }
1402

    
1403
    *ret_data = QOBJECT(bus_list);
1404
}
1405

    
1406
static const char * const pci_nic_models[] = {
1407
    "ne2k_pci",
1408
    "i82551",
1409
    "i82557b",
1410
    "i82559er",
1411
    "rtl8139",
1412
    "e1000",
1413
    "pcnet",
1414
    "virtio",
1415
    NULL
1416
};
1417

    
1418
static const char * const pci_nic_names[] = {
1419
    "ne2k_pci",
1420
    "i82551",
1421
    "i82557b",
1422
    "i82559er",
1423
    "rtl8139",
1424
    "e1000",
1425
    "pcnet",
1426
    "virtio-net-pci",
1427
    NULL
1428
};
1429

    
1430
/* Initialize a PCI NIC.  */
1431
/* FIXME callers should check for failure, but don't */
1432
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1433
                        const char *default_devaddr)
1434
{
1435
    const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1436
    PCIBus *bus;
1437
    int devfn;
1438
    PCIDevice *pci_dev;
1439
    DeviceState *dev;
1440
    int i;
1441

    
1442
    i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1443
    if (i < 0)
1444
        return NULL;
1445

    
1446
    bus = pci_get_bus_devfn(&devfn, devaddr);
1447
    if (!bus) {
1448
        error_report("Invalid PCI device address %s for device %s",
1449
                     devaddr, pci_nic_names[i]);
1450
        return NULL;
1451
    }
1452

    
1453
    pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1454
    dev = &pci_dev->qdev;
1455
    qdev_set_nic_properties(dev, nd);
1456
    if (qdev_init(dev) < 0)
1457
        return NULL;
1458
    return pci_dev;
1459
}
1460

    
1461
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1462
                               const char *default_devaddr)
1463
{
1464
    PCIDevice *res;
1465

    
1466
    if (qemu_show_nic_models(nd->model, pci_nic_models))
1467
        exit(0);
1468

    
1469
    res = pci_nic_init(nd, default_model, default_devaddr);
1470
    if (!res)
1471
        exit(1);
1472
    return res;
1473
}
1474

    
1475
typedef struct {
1476
    PCIDevice dev;
1477
    PCIBus bus;
1478
    uint32_t vid;
1479
    uint32_t did;
1480
} PCIBridge;
1481

    
1482

    
1483
static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1484
{
1485
    pci_update_mappings(d);
1486
}
1487

    
1488
static void pci_bridge_update_mappings(PCIBus *b)
1489
{
1490
    PCIBus *child;
1491

    
1492
    pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1493

    
1494
    QLIST_FOREACH(child, &b->child, sibling) {
1495
        pci_bridge_update_mappings(child);
1496
    }
1497
}
1498

    
1499
static void pci_bridge_write_config(PCIDevice *d,
1500
                             uint32_t address, uint32_t val, int len)
1501
{
1502
    pci_default_write_config(d, address, val, len);
1503

    
1504
    if (/* io base/limit */
1505
        ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1506

    
1507
        /* memory base/limit, prefetchable base/limit and
1508
           io base/limit upper 16 */
1509
        ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1510
        pci_bridge_update_mappings(d->bus);
1511
    }
1512
}
1513

    
1514
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1515
{
1516
    PCIBus *sec;
1517

    
1518
    if (!bus) {
1519
        return NULL;
1520
    }
1521

    
1522
    if (pci_bus_num(bus) == bus_num) {
1523
        return bus;
1524
    }
1525

    
1526
    /* try child bus */
1527
    if (!bus->parent_dev /* host pci bridge */ ||
1528
        (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1529
         bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1530
        for (; bus; bus = sec) {
1531
            QLIST_FOREACH(sec, &bus->child, sibling) {
1532
                assert(sec->parent_dev);
1533
                if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1534
                    return sec;
1535
                }
1536
                if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1537
                    bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1538
                    break;
1539
                }
1540
            }
1541
        }
1542
    }
1543

    
1544
    return NULL;
1545
}
1546

    
1547
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1548
{
1549
    bus = pci_find_bus(bus, bus_num);
1550

    
1551
    if (!bus)
1552
        return NULL;
1553

    
1554
    return bus->devices[PCI_DEVFN(slot, function)];
1555
}
1556

    
1557
static int pci_bridge_initfn(PCIDevice *dev)
1558
{
1559
    PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1560

    
1561
    pci_config_set_vendor_id(s->dev.config, s->vid);
1562
    pci_config_set_device_id(s->dev.config, s->did);
1563

    
1564
    pci_set_word(dev->config + PCI_STATUS,
1565
                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1566
    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1567
    dev->config[PCI_HEADER_TYPE] =
1568
        (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
1569
        PCI_HEADER_TYPE_BRIDGE;
1570
    pci_set_word(dev->config + PCI_SEC_STATUS,
1571
                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1572
    return 0;
1573
}
1574

    
1575
static int pci_bridge_exitfn(PCIDevice *pci_dev)
1576
{
1577
    PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1578
    PCIBus *bus = &s->bus;
1579
    pci_unregister_secondary_bus(bus);
1580
    return 0;
1581
}
1582

    
1583
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1584
                        pci_map_irq_fn map_irq, const char *name)
1585
{
1586
    PCIDevice *dev;
1587
    PCIBridge *s;
1588

    
1589
    dev = pci_create(bus, devfn, "pci-bridge");
1590
    qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1591
    qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1592
    qdev_init_nofail(&dev->qdev);
1593

    
1594
    s = DO_UPCAST(PCIBridge, dev, dev);
1595
    pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1596
    return &s->bus;
1597
}
1598

    
1599
PCIDevice *pci_bridge_get_device(PCIBus *bus)
1600
{
1601
    return bus->parent_dev;
1602
}
1603

    
1604
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1605
{
1606
    PCIDevice *pci_dev = (PCIDevice *)qdev;
1607
    PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1608
    PCIBus *bus;
1609
    int devfn, rc;
1610

    
1611
    /* initialize cap_present for pci_is_express() and pci_config_size() */
1612
    if (info->is_express) {
1613
        pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1614
    }
1615

    
1616
    bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1617
    devfn = pci_dev->devfn;
1618
    pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1619
                                     info->config_read, info->config_write,
1620
                                     info->is_bridge);
1621
    if (pci_dev == NULL)
1622
        return -1;
1623
    rc = info->init(pci_dev);
1624
    if (rc != 0) {
1625
        do_pci_unregister_device(pci_dev);
1626
        return rc;
1627
    }
1628

    
1629
    /* rom loading */
1630
    if (pci_dev->romfile == NULL && info->romfile != NULL)
1631
        pci_dev->romfile = qemu_strdup(info->romfile);
1632
    pci_add_option_rom(pci_dev);
1633

    
1634
    if (qdev->hotplugged)
1635
        bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1636
    return 0;
1637
}
1638

    
1639
static int pci_unplug_device(DeviceState *qdev)
1640
{
1641
    PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1642

    
1643
    dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1644
    return 0;
1645
}
1646

    
1647
void pci_qdev_register(PCIDeviceInfo *info)
1648
{
1649
    info->qdev.init = pci_qdev_init;
1650
    info->qdev.unplug = pci_unplug_device;
1651
    info->qdev.exit = pci_unregister_device;
1652
    info->qdev.bus_info = &pci_bus_info;
1653
    qdev_register(&info->qdev);
1654
}
1655

    
1656
void pci_qdev_register_many(PCIDeviceInfo *info)
1657
{
1658
    while (info->qdev.name) {
1659
        pci_qdev_register(info);
1660
        info++;
1661
    }
1662
}
1663

    
1664
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1665
                                    const char *name)
1666
{
1667
    DeviceState *dev;
1668

    
1669
    dev = qdev_create(&bus->qbus, name);
1670
    qdev_prop_set_uint32(dev, "addr", devfn);
1671
    qdev_prop_set_bit(dev, "multifunction", multifunction);
1672
    return DO_UPCAST(PCIDevice, qdev, dev);
1673
}
1674

    
1675
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1676
                                           bool multifunction,
1677
                                           const char *name)
1678
{
1679
    PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1680
    qdev_init_nofail(&dev->qdev);
1681
    return dev;
1682
}
1683

    
1684
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1685
{
1686
    return pci_create_multifunction(bus, devfn, false, name);
1687
}
1688

    
1689
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1690
{
1691
    return pci_create_simple_multifunction(bus, devfn, false, name);
1692
}
1693

    
1694
static int pci_find_space(PCIDevice *pdev, uint8_t size)
1695
{
1696
    int config_size = pci_config_size(pdev);
1697
    int offset = PCI_CONFIG_HEADER_SIZE;
1698
    int i;
1699
    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1700
        if (pdev->used[i])
1701
            offset = i + 1;
1702
        else if (i - offset + 1 == size)
1703
            return offset;
1704
    return 0;
1705
}
1706

    
1707
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1708
                                        uint8_t *prev_p)
1709
{
1710
    uint8_t next, prev;
1711

    
1712
    if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1713
        return 0;
1714

    
1715
    for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1716
         prev = next + PCI_CAP_LIST_NEXT)
1717
        if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1718
            break;
1719

    
1720
    if (prev_p)
1721
        *prev_p = prev;
1722
    return next;
1723
}
1724

    
1725
static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1726
{
1727
    cpu_register_physical_memory(addr, size, pdev->rom_offset);
1728
}
1729

    
1730
/* Add an option rom for the device */
1731
static int pci_add_option_rom(PCIDevice *pdev)
1732
{
1733
    int size;
1734
    char *path;
1735
    void *ptr;
1736
    char name[32];
1737

    
1738
    if (!pdev->romfile)
1739
        return 0;
1740
    if (strlen(pdev->romfile) == 0)
1741
        return 0;
1742

    
1743
    if (!pdev->rom_bar) {
1744
        /*
1745
         * Load rom via fw_cfg instead of creating a rom bar,
1746
         * for 0.11 compatibility.
1747
         */
1748
        int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1749
        if (class == 0x0300) {
1750
            rom_add_vga(pdev->romfile);
1751
        } else {
1752
            rom_add_option(pdev->romfile);
1753
        }
1754
        return 0;
1755
    }
1756

    
1757
    path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1758
    if (path == NULL) {
1759
        path = qemu_strdup(pdev->romfile);
1760
    }
1761

    
1762
    size = get_image_size(path);
1763
    if (size < 0) {
1764
        error_report("%s: failed to find romfile \"%s\"",
1765
                     __FUNCTION__, pdev->romfile);
1766
        return -1;
1767
    }
1768
    if (size & (size - 1)) {
1769
        size = 1 << qemu_fls(size);
1770
    }
1771

    
1772
    if (pdev->qdev.info->vmsd)
1773
        snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1774
    else
1775
        snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1776
    pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1777

    
1778
    ptr = qemu_get_ram_ptr(pdev->rom_offset);
1779
    load_image(path, ptr);
1780
    qemu_free(path);
1781

    
1782
    pci_register_bar(pdev, PCI_ROM_SLOT, size,
1783
                     0, pci_map_option_rom);
1784

    
1785
    return 0;
1786
}
1787

    
1788
static void pci_del_option_rom(PCIDevice *pdev)
1789
{
1790
    if (!pdev->rom_offset)
1791
        return;
1792

    
1793
    qemu_ram_free(pdev->rom_offset);
1794
    pdev->rom_offset = 0;
1795
}
1796

    
1797
/* Reserve space and add capability to the linked list in pci config space */
1798
int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
1799
                                 uint8_t offset, uint8_t size)
1800
{
1801
    uint8_t *config = pdev->config + offset;
1802
    config[PCI_CAP_LIST_ID] = cap_id;
1803
    config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1804
    pdev->config[PCI_CAPABILITY_LIST] = offset;
1805
    pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1806
    memset(pdev->used + offset, 0xFF, size);
1807
    /* Make capability read-only by default */
1808
    memset(pdev->wmask + offset, 0, size);
1809
    /* Check capability by default */
1810
    memset(pdev->cmask + offset, 0xFF, size);
1811
    return offset;
1812
}
1813

    
1814
/* Find and reserve space and add capability to the linked list
1815
 * in pci config space */
1816
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1817
{
1818
    uint8_t offset = pci_find_space(pdev, size);
1819
    if (!offset) {
1820
        return -ENOSPC;
1821
    }
1822
    return pci_add_capability_at_offset(pdev, cap_id, offset, size);
1823
}
1824

    
1825
/* Unlink capability from the pci config space. */
1826
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1827
{
1828
    uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1829
    if (!offset)
1830
        return;
1831
    pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1832
    /* Make capability writeable again */
1833
    memset(pdev->wmask + offset, 0xff, size);
1834
    /* Clear cmask as device-specific registers can't be checked */
1835
    memset(pdev->cmask + offset, 0, size);
1836
    memset(pdev->used + offset, 0, size);
1837

    
1838
    if (!pdev->config[PCI_CAPABILITY_LIST])
1839
        pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1840
}
1841

    
1842
/* Reserve space for capability at a known offset (to call after load). */
1843
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1844
{
1845
    memset(pdev->used + offset, 0xff, size);
1846
}
1847

    
1848
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1849
{
1850
    return pci_find_capability_list(pdev, cap_id, NULL);
1851
}
1852

    
1853
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1854
{
1855
    PCIDevice *d = (PCIDevice *)dev;
1856
    const pci_class_desc *desc;
1857
    char ctxt[64];
1858
    PCIIORegion *r;
1859
    int i, class;
1860

    
1861
    class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1862
    desc = pci_class_descriptions;
1863
    while (desc->desc && class != desc->class)
1864
        desc++;
1865
    if (desc->desc) {
1866
        snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1867
    } else {
1868
        snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1869
    }
1870

    
1871
    monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1872
                   "pci id %04x:%04x (sub %04x:%04x)\n",
1873
                   indent, "", ctxt,
1874
                   d->config[PCI_SECONDARY_BUS],
1875
                   PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1876
                   pci_get_word(d->config + PCI_VENDOR_ID),
1877
                   pci_get_word(d->config + PCI_DEVICE_ID),
1878
                   pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1879
                   pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1880
    for (i = 0; i < PCI_NUM_REGIONS; i++) {
1881
        r = &d->io_regions[i];
1882
        if (!r->size)
1883
            continue;
1884
        monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1885
                       " [0x%"FMT_PCIBUS"]\n",
1886
                       indent, "",
1887
                       i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1888
                       r->addr, r->addr + r->size - 1);
1889
    }
1890
}
1891

    
1892
static char *pcibus_get_dev_path(DeviceState *dev)
1893
{
1894
    PCIDevice *d = (PCIDevice *)dev;
1895
    char path[16];
1896

    
1897
    snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1898
             pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1899
             PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1900

    
1901
    return strdup(path);
1902
}
1903

    
1904
static PCIDeviceInfo bridge_info = {
1905
    .qdev.name    = "pci-bridge",
1906
    .qdev.size    = sizeof(PCIBridge),
1907
    .init         = pci_bridge_initfn,
1908
    .exit         = pci_bridge_exitfn,
1909
    .config_write = pci_bridge_write_config,
1910
    .is_bridge    = 1,
1911
    .qdev.props   = (Property[]) {
1912
        DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1913
        DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1914
        DEFINE_PROP_END_OF_LIST(),
1915
    }
1916
};
1917

    
1918
static void pci_register_devices(void)
1919
{
1920
    pci_qdev_register(&bridge_info);
1921
}
1922

    
1923
device_init(pci_register_devices)