Revision 49a2942d
| b/hw/mips_fulong2e.c | ||
|---|---|---|
| 265 | 265 |
qemu_irq *cpu_exit_irq; |
| 266 | 266 |
int via_devfn; |
| 267 | 267 |
PCIBus *pci_bus; |
| 268 |
ISADevice *isa_dev; |
|
| 269 | 268 |
uint8_t *eeprom_buf; |
| 270 | 269 |
i2c_bus *smbus; |
| 271 | 270 |
int i; |
| 272 | 271 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
| 273 | 272 |
DeviceState *eeprom; |
| 274 |
ISADevice *rtc_state; |
|
| 275 | 273 |
CPUState *env; |
| 276 | 274 |
|
| 277 | 275 |
/* init CPUs */ |
| ... | ... | |
| 378 | 376 |
DMA_init(0, cpu_exit_irq); |
| 379 | 377 |
|
| 380 | 378 |
/* Super I/O */ |
| 381 |
isa_dev = isa_create_simple("i8042");
|
|
| 379 |
isa_create_simple("i8042");
|
|
| 382 | 380 |
|
| 383 |
rtc_state = rtc_init(2000, NULL);
|
|
| 381 |
rtc_init(2000, NULL); |
|
| 384 | 382 |
|
| 385 | 383 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
|
| 386 | 384 |
if (serial_hds[i]) {
|
| b/hw/mips_malta.c | ||
|---|---|---|
| 784 | 784 |
target_long bios_size; |
| 785 | 785 |
int64_t kernel_entry; |
| 786 | 786 |
PCIBus *pci_bus; |
| 787 |
ISADevice *isa_dev; |
|
| 788 | 787 |
CPUState *env; |
| 789 |
ISADevice *rtc_state; |
|
| 790 |
FDCtrl *floppy_controller; |
|
| 791 |
MaltaFPGAState *malta_fpga; |
|
| 792 | 788 |
qemu_irq *i8259; |
| 793 | 789 |
qemu_irq *cpu_exit_irq; |
| 794 | 790 |
int piix4_devfn; |
| ... | ... | |
| 851 | 847 |
be = 0; |
| 852 | 848 |
#endif |
| 853 | 849 |
/* FPGA */ |
| 854 |
malta_fpga = malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
|
|
| 850 |
malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]); |
|
| 855 | 851 |
|
| 856 | 852 |
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */ |
| 857 | 853 |
if (kernel_filename) {
|
| ... | ... | |
| 957 | 953 |
DMA_init(0, cpu_exit_irq); |
| 958 | 954 |
|
| 959 | 955 |
/* Super I/O */ |
| 960 |
isa_dev = isa_create_simple("i8042");
|
|
| 961 |
|
|
| 962 |
rtc_state = rtc_init(2000, NULL);
|
|
| 956 |
isa_create_simple("i8042");
|
|
| 957 |
|
|
| 958 |
rtc_init(2000, NULL); |
|
| 963 | 959 |
serial_isa_init(0, serial_hds[0]); |
| 964 | 960 |
serial_isa_init(1, serial_hds[1]); |
| 965 | 961 |
if (parallel_hds[0]) |
| ... | ... | |
| 967 | 963 |
for(i = 0; i < MAX_FD; i++) {
|
| 968 | 964 |
fd[i] = drive_get(IF_FLOPPY, 0, i); |
| 969 | 965 |
} |
| 970 |
floppy_controller = fdctrl_init_isa(fd);
|
|
| 966 |
fdctrl_init_isa(fd); |
|
| 971 | 967 |
|
| 972 | 968 |
/* Sound card */ |
| 973 | 969 |
audio_init(pci_bus); |
| b/hw/mips_r4k.c | ||
|---|---|---|
| 167 | 167 |
int bios_size; |
| 168 | 168 |
CPUState *env; |
| 169 | 169 |
ResetData *reset_info; |
| 170 |
ISADevice *rtc_state; |
|
| 171 | 170 |
int i; |
| 172 | 171 |
qemu_irq *i8259; |
| 173 | 172 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
| ... | ... | |
| 268 | 267 |
isa_bus_new(NULL); |
| 269 | 268 |
isa_bus_irqs(i8259); |
| 270 | 269 |
|
| 271 |
rtc_state = rtc_init(2000, NULL);
|
|
| 270 |
rtc_init(2000, NULL); |
|
| 272 | 271 |
|
| 273 | 272 |
/* Register 64 KB of ISA IO space at 0x14000000 */ |
| 274 | 273 |
#ifdef TARGET_WORDS_BIGENDIAN |
| b/hw/ppc405_boards.c | ||
|---|---|---|
| 501 | 501 |
const char *cpu_model) |
| 502 | 502 |
{
|
| 503 | 503 |
char *filename; |
| 504 |
CPUPPCState *env; |
|
| 505 | 504 |
qemu_irq *pic; |
| 506 | 505 |
ram_addr_t bios_offset; |
| 507 | 506 |
target_phys_addr_t ram_bases[2], ram_sizes[2]; |
| ... | ... | |
| 521 | 520 |
#ifdef DEBUG_BOARD_INIT |
| 522 | 521 |
printf("%s: register cpu\n", __func__);
|
| 523 | 522 |
#endif |
| 524 |
env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
|
|
| 525 |
kernel_filename == NULL ? 0 : 1);
|
|
| 523 |
ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, |
|
| 524 |
kernel_filename == NULL ? 0 : 1); |
|
| 526 | 525 |
/* allocate and load BIOS */ |
| 527 | 526 |
#ifdef DEBUG_BOARD_INIT |
| 528 | 527 |
printf("%s: register BIOS\n", __func__);
|
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 630 | 630 |
|
| 631 | 631 |
static uint32_t dcr_read_dma (void *opaque, int dcrn) |
| 632 | 632 |
{
|
| 633 |
ppc405_dma_t *dma; |
|
| 634 |
|
|
| 635 |
dma = opaque; |
|
| 636 |
|
|
| 637 | 633 |
return 0; |
| 638 | 634 |
} |
| 639 | 635 |
|
| 640 | 636 |
static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) |
| 641 | 637 |
{
|
| 642 |
ppc405_dma_t *dma; |
|
| 643 |
|
|
| 644 |
dma = opaque; |
|
| 645 | 638 |
} |
| 646 | 639 |
|
| 647 | 640 |
static void ppc405_dma_reset (void *opaque) |
| ... | ... | |
| 739 | 732 |
|
| 740 | 733 |
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
| 741 | 734 |
{
|
| 742 |
ppc405_gpio_t *gpio; |
|
| 743 |
|
|
| 744 |
gpio = opaque; |
|
| 745 | 735 |
#ifdef DEBUG_GPIO |
| 746 | 736 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
| 747 | 737 |
#endif |
| ... | ... | |
| 752 | 742 |
static void ppc405_gpio_writeb (void *opaque, |
| 753 | 743 |
target_phys_addr_t addr, uint32_t value) |
| 754 | 744 |
{
|
| 755 |
ppc405_gpio_t *gpio; |
|
| 756 |
|
|
| 757 |
gpio = opaque; |
|
| 758 | 745 |
#ifdef DEBUG_GPIO |
| 759 | 746 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
|
| 760 | 747 |
value); |
| ... | ... | |
| 763 | 750 |
|
| 764 | 751 |
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
| 765 | 752 |
{
|
| 766 |
ppc405_gpio_t *gpio; |
|
| 767 |
|
|
| 768 |
gpio = opaque; |
|
| 769 | 753 |
#ifdef DEBUG_GPIO |
| 770 | 754 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
| 771 | 755 |
#endif |
| ... | ... | |
| 776 | 760 |
static void ppc405_gpio_writew (void *opaque, |
| 777 | 761 |
target_phys_addr_t addr, uint32_t value) |
| 778 | 762 |
{
|
| 779 |
ppc405_gpio_t *gpio; |
|
| 780 |
|
|
| 781 |
gpio = opaque; |
|
| 782 | 763 |
#ifdef DEBUG_GPIO |
| 783 | 764 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
|
| 784 | 765 |
value); |
| ... | ... | |
| 787 | 768 |
|
| 788 | 769 |
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
| 789 | 770 |
{
|
| 790 |
ppc405_gpio_t *gpio; |
|
| 791 |
|
|
| 792 |
gpio = opaque; |
|
| 793 | 771 |
#ifdef DEBUG_GPIO |
| 794 | 772 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
| 795 | 773 |
#endif |
| ... | ... | |
| 800 | 778 |
static void ppc405_gpio_writel (void *opaque, |
| 801 | 779 |
target_phys_addr_t addr, uint32_t value) |
| 802 | 780 |
{
|
| 803 |
ppc405_gpio_t *gpio; |
|
| 804 |
|
|
| 805 |
gpio = opaque; |
|
| 806 | 781 |
#ifdef DEBUG_GPIO |
| 807 | 782 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
|
| 808 | 783 |
value); |
| ... | ... | |
| 823 | 798 |
|
| 824 | 799 |
static void ppc405_gpio_reset (void *opaque) |
| 825 | 800 |
{
|
| 826 |
ppc405_gpio_t *gpio; |
|
| 827 |
|
|
| 828 |
gpio = opaque; |
|
| 829 | 801 |
} |
| 830 | 802 |
|
| 831 | 803 |
static void ppc405_gpio_init(target_phys_addr_t base) |
| b/hw/ppc_newworld.c | ||
|---|---|---|
| 128 | 128 |
const char *initrd_filename, |
| 129 | 129 |
const char *cpu_model) |
| 130 | 130 |
{
|
| 131 |
CPUState *env = NULL, *envs[MAX_CPUS];
|
|
| 131 |
CPUState *env = NULL; |
|
| 132 | 132 |
char *filename; |
| 133 | 133 |
qemu_irq *pic, **openpic_irqs; |
| 134 | 134 |
int unin_memory; |
| ... | ... | |
| 166 | 166 |
/* Set time-base frequency to 100 Mhz */ |
| 167 | 167 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
| 168 | 168 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
| 169 |
envs[i] = env; |
|
| 170 | 169 |
} |
| 171 | 170 |
|
| 172 | 171 |
/* allocate RAM */ |
| b/hw/ppc_oldworld.c | ||
|---|---|---|
| 66 | 66 |
const char *initrd_filename, |
| 67 | 67 |
const char *cpu_model) |
| 68 | 68 |
{
|
| 69 |
CPUState *env = NULL, *envs[MAX_CPUS];
|
|
| 69 |
CPUState *env = NULL; |
|
| 70 | 70 |
char *filename; |
| 71 | 71 |
qemu_irq *pic, **heathrow_irqs; |
| 72 | 72 |
int linux_boot, i; |
| ... | ... | |
| 97 | 97 |
/* Set time-base frequency to 16.6 Mhz */ |
| 98 | 98 |
cpu_ppc_tb_init(env, 16600000UL); |
| 99 | 99 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
| 100 |
envs[i] = env; |
|
| 101 | 100 |
} |
| 102 | 101 |
|
| 103 | 102 |
/* allocate RAM */ |
| b/hw/ppc_prep.c | ||
|---|---|---|
| 565 | 565 |
const char *initrd_filename, |
| 566 | 566 |
const char *cpu_model) |
| 567 | 567 |
{
|
| 568 |
CPUState *env = NULL, *envs[MAX_CPUS];
|
|
| 568 |
CPUState *env = NULL; |
|
| 569 | 569 |
char *filename; |
| 570 | 570 |
nvram_t nvram; |
| 571 | 571 |
M48t59State *m48t59; |
| ... | ... | |
| 602 | 602 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
| 603 | 603 |
} |
| 604 | 604 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
| 605 |
envs[i] = env; |
|
| 606 | 605 |
} |
| 607 | 606 |
|
| 608 | 607 |
/* allocate RAM */ |
| b/hw/ppce500_mpc8544ds.c | ||
|---|---|---|
| 176 | 176 |
int i=0; |
| 177 | 177 |
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
|
| 178 | 178 |
qemu_irq *irqs, *mpic, *pci_irqs; |
| 179 |
SerialState * serial[2]; |
|
| 180 | 179 |
|
| 181 | 180 |
/* Setup CPU */ |
| 182 | 181 |
env = cpu_ppc_init("e500v2_v30");
|
| ... | ... | |
| 200 | 199 |
|
| 201 | 200 |
/* Serial */ |
| 202 | 201 |
if (serial_hds[0]) {
|
| 203 |
serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
|
|
| 204 |
0, mpic[12+26], 399193,
|
|
| 205 |
serial_hds[0], 1, 1);
|
|
| 202 |
serial_mm_init(MPC8544_SERIAL0_REGS_BASE, |
|
| 203 |
0, mpic[12+26], 399193, |
|
| 204 |
serial_hds[0], 1, 1); |
|
| 206 | 205 |
} |
| 207 | 206 |
|
| 208 | 207 |
if (serial_hds[1]) {
|
| 209 |
serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
|
|
| 210 |
0, mpic[12+26], 399193,
|
|
| 211 |
serial_hds[0], 1, 1);
|
|
| 208 |
serial_mm_init(MPC8544_SERIAL1_REGS_BASE, |
|
| 209 |
0, mpic[12+26], 399193, |
|
| 210 |
serial_hds[0], 1, 1); |
|
| 212 | 211 |
} |
| 213 | 212 |
|
| 214 | 213 |
/* PCI */ |
| b/hw/tc6393xb_template.h | ||
|---|---|---|
| 38 | 38 |
static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s) |
| 39 | 39 |
{
|
| 40 | 40 |
int i; |
| 41 |
int w_display; |
|
| 42 | 41 |
uint16_t *data_buffer; |
| 43 | 42 |
uint8_t *data_display; |
| 44 | 43 |
|
| 45 | 44 |
data_buffer = s->vram_ptr; |
| 46 |
w_display = s->scr_width * BITS / 8; |
|
| 47 | 45 |
data_display = ds_get_data(s->ds); |
| 48 | 46 |
for(i = 0; i < s->scr_height; i++) {
|
| 49 | 47 |
#if (BITS == 16) |
| b/hw/virtex_ml507.c | ||
|---|---|---|
| 85 | 85 |
uint32_t sysclk) |
| 86 | 86 |
{
|
| 87 | 87 |
CPUState *env; |
| 88 |
qemu_irq *pic; |
|
| 89 | 88 |
qemu_irq *irqs; |
| 90 | 89 |
|
| 91 | 90 |
env = cpu_init(cpu_model); |
| ... | ... | |
| 106 | 105 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); |
| 107 | 106 |
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
| 108 | 107 |
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
| 109 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
|
|
| 108 |
ppcuic_init(env, irqs, 0x0C0, 0, 1); |
|
| 110 | 109 |
return env; |
| 111 | 110 |
} |
| 112 | 111 |
|
| ... | ... | |
| 236 | 235 |
|
| 237 | 236 |
if (kernel_filename) {
|
| 238 | 237 |
uint64_t entry, low, high; |
| 239 |
uint32_t base32; |
|
| 240 | 238 |
target_phys_addr_t boot_offset; |
| 241 | 239 |
|
| 242 | 240 |
/* Boots a kernel elf binary. */ |
| 243 | 241 |
kernel_size = load_elf(kernel_filename, NULL, NULL, |
| 244 | 242 |
&entry, &low, &high, 1, ELF_MACHINE, 0); |
| 245 |
base32 = entry; |
|
| 246 | 243 |
boot_info.bootstrap_pc = entry & 0x00ffffff; |
| 247 | 244 |
|
| 248 | 245 |
if (kernel_size < 0) {
|
| b/hw/wm8750.c | ||
|---|---|---|
| 171 | 171 |
int i; |
| 172 | 172 |
struct audsettings in_fmt; |
| 173 | 173 |
struct audsettings out_fmt; |
| 174 |
struct audsettings monoout_fmt; |
|
| 175 | 174 |
|
| 176 | 175 |
wm8750_out_flush(s); |
| 177 | 176 |
|
| ... | ... | |
| 212 | 211 |
out_fmt.nchannels = 2; |
| 213 | 212 |
out_fmt.freq = s->dac_hz; |
| 214 | 213 |
out_fmt.fmt = AUD_FMT_S16; |
| 215 |
monoout_fmt.endianness = 0; |
|
| 216 |
monoout_fmt.nchannels = 1; |
|
| 217 |
monoout_fmt.freq = s->rate->dac_hz; |
|
| 218 |
monoout_fmt.fmt = AUD_FMT_S16; |
|
| 219 | 214 |
|
| 220 | 215 |
s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0], |
| 221 | 216 |
CODEC ".speaker", s, wm8750_audio_out_cb, &out_fmt); |
| b/net/tap-win32.c | ||
|---|---|---|
| 579 | 579 |
} version; |
| 580 | 580 |
DWORD version_len; |
| 581 | 581 |
DWORD idThread; |
| 582 |
HANDLE hThread; |
|
| 583 | 582 |
|
| 584 | 583 |
if (prefered_name != NULL) |
| 585 | 584 |
snprintf(name_buffer, sizeof(name_buffer), "%s", prefered_name); |
| ... | ... | |
| 623 | 622 |
|
| 624 | 623 |
*phandle = &tap_overlapped; |
| 625 | 624 |
|
| 626 |
hThread = CreateThread(NULL, 0, tap_win32_thread_entry,
|
|
| 627 |
(LPVOID)&tap_overlapped, 0, &idThread);
|
|
| 625 |
CreateThread(NULL, 0, tap_win32_thread_entry, |
|
| 626 |
(LPVOID)&tap_overlapped, 0, &idThread); |
|
| 628 | 627 |
return 0; |
| 629 | 628 |
} |
| 630 | 629 |
|
| b/savevm.c | ||
|---|---|---|
| 1615 | 1615 |
while (qemu_peek_byte(f) == QEMU_VM_SUBSECTION) {
|
| 1616 | 1616 |
char idstr[256]; |
| 1617 | 1617 |
int ret; |
| 1618 |
uint8_t version_id, subsection, len;
|
|
| 1618 |
uint8_t version_id, len; |
|
| 1619 | 1619 |
const VMStateDescription *sub_vmsd; |
| 1620 | 1620 |
|
| 1621 |
subsection = qemu_get_byte(f);
|
|
| 1621 |
qemu_get_byte(f); /* subsection */
|
|
| 1622 | 1622 |
len = qemu_get_byte(f); |
| 1623 | 1623 |
qemu_get_buffer(f, (uint8_t *)idstr, len); |
| 1624 | 1624 |
idstr[len] = 0; |
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