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/*
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 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
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 *
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 * Copyright (c) 2004-2007 Fabrice Bellard
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 * Copyright (c) 2007 Jocelyn Mayer
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "ppc.h"
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#include "ppc_mac.h"
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#include "mac_dbdma.h"
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#include "nvram.h"
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#include "pc.h"
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#include "sysemu.h"
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#include "net.h"
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#include "isa.h"
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#include "pci.h"
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#include "usb-ohci.h"
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#include "boards.h"
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#include "fw_cfg.h"
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#include "escc.h"
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#include "ide.h"
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#include "loader.h"
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#include "elf.h"
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#include "kvm.h"
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#include "kvm_ppc.h"
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#include "blockdev.h"
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#define MAX_IDE_BUS 2
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#define CFG_ADDR 0xf0000510
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static int fw_cfg_boot_set(void *opaque, const char *boot_device)
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{
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    fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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    return 0;
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}
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
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{
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    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
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}
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static void ppc_heathrow_init (ram_addr_t ram_size,
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                               const char *boot_device,
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                               const char *kernel_filename,
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                               const char *kernel_cmdline,
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                               const char *initrd_filename,
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                               const char *cpu_model)
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{
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    CPUState *env = NULL;
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    char *filename;
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    qemu_irq *pic, **heathrow_irqs;
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    int linux_boot, i;
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    ram_addr_t ram_offset, bios_offset;
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    uint32_t kernel_base, initrd_base;
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    int32_t kernel_size, initrd_size;
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    PCIBus *pci_bus;
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    MacIONVRAMState *nvr;
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    int bios_size;
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    int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
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    int escc_mem_index, ide_mem_index[2];
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    uint16_t ppc_boot_device;
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    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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    void *fw_cfg;
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    void *dbdma;
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    linux_boot = (kernel_filename != NULL);
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    /* init CPUs */
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    if (cpu_model == NULL)
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        cpu_model = "G3";
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    for (i = 0; i < smp_cpus; i++) {
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        env = cpu_init(cpu_model);
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        if (!env) {
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            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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            exit(1);
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        }
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        /* Set time-base frequency to 16.6 Mhz */
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        cpu_ppc_tb_init(env,  16600000UL);
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        qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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    }
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    /* allocate RAM */
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    if (ram_size > (2047 << 20)) {
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        fprintf(stderr,
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                "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
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                ((unsigned int)ram_size / (1 << 20)));
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        exit(1);
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    }
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    ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", ram_size);
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    cpu_register_physical_memory(0, ram_size, ram_offset);
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    /* allocate and load BIOS */
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    bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE);
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    if (bios_name == NULL)
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        bios_name = PROM_FILENAME;
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    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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    cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
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    /* Load OpenBIOS (ELF) */
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    if (filename) {
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        bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
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                             1, ELF_MACHINE, 0);
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        qemu_free(filename);
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    } else {
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        bios_size = -1;
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    }
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    if (bios_size < 0 || bios_size > BIOS_SIZE) {
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        hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
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        exit(1);
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    }
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    if (linux_boot) {
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        uint64_t lowaddr = 0;
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        int bswap_needed;
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#ifdef BSWAP_NEEDED
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        bswap_needed = 1;
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#else
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        bswap_needed = 0;
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#endif
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        kernel_base = KERNEL_LOAD_ADDR;
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        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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                               NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
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        if (kernel_size < 0)
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            kernel_size = load_aout(kernel_filename, kernel_base,
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                                    ram_size - kernel_base, bswap_needed,
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                                    TARGET_PAGE_SIZE);
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        if (kernel_size < 0)
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            kernel_size = load_image_targphys(kernel_filename,
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                                              kernel_base,
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                                              ram_size - kernel_base);
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        if (kernel_size < 0) {
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            hw_error("qemu: could not load kernel '%s'\n",
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                      kernel_filename);
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            exit(1);
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        }
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        /* load initrd */
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        if (initrd_filename) {
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            initrd_base = INITRD_LOAD_ADDR;
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            initrd_size = load_image_targphys(initrd_filename, initrd_base,
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                                              ram_size - initrd_base);
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            if (initrd_size < 0) {
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                hw_error("qemu: could not load initial ram disk '%s'\n",
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                         initrd_filename);
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                exit(1);
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            }
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        } else {
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            initrd_base = 0;
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            initrd_size = 0;
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        }
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        ppc_boot_device = 'm';
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    } else {
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        kernel_base = 0;
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        kernel_size = 0;
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        initrd_base = 0;
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        initrd_size = 0;
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        ppc_boot_device = '\0';
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        for (i = 0; boot_device[i] != '\0'; i++) {
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            /* TOFIX: for now, the second IDE channel is not properly
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             *        used by OHW. The Mac floppy disk are not emulated.
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             *        For now, OHW cannot boot from the network.
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             */
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#if 0
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            if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
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                ppc_boot_device = boot_device[i];
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                break;
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            }
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#else
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            if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
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                ppc_boot_device = boot_device[i];
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                break;
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            }
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#endif
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        }
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        if (ppc_boot_device == '\0') {
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            fprintf(stderr, "No valid boot device for G3 Beige machine\n");
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            exit(1);
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        }
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    }
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    isa_mem_base = 0x80000000;
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    /* Register 2 MB of ISA IO space */
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    isa_mmio_init(0xfe000000, 0x00200000, 1);
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    /* XXX: we register only 1 output pin for heathrow PIC */
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    heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
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    heathrow_irqs[0] =
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        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
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    /* Connect the heathrow PIC outputs to the 6xx bus */
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    for (i = 0; i < smp_cpus; i++) {
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        switch (PPC_INPUT(env)) {
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        case PPC_FLAGS_INPUT_6xx:
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            heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
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            heathrow_irqs[i][0] =
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                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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            break;
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        default:
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            hw_error("Bus model not supported on OldWorld Mac machine\n");
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        }
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    }
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    /* init basic PC hardware */
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    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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        hw_error("Only 6xx bus is supported on heathrow machine\n");
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    }
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    pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
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    pci_bus = pci_grackle_init(0xfec00000, pic);
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    pci_vga_init(pci_bus, 0, 0);
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    escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
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                               serial_hds[1], ESCC_CLOCK, 4);
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    for(i = 0; i < nb_nics; i++)
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        pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
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    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
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        fprintf(stderr, "qemu: too many IDE bus\n");
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        exit(1);
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    }
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    /* First IDE channel is a MAC IDE on the MacIO bus */
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    hd[0] = drive_get(IF_IDE, 0, 0);
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    hd[1] = drive_get(IF_IDE, 0, 1);
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    dbdma = DBDMA_init(&dbdma_mem_index);
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    ide_mem_index[0] = -1;
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    ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
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    /* Second IDE channel is a CMD646 on the PCI bus */
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    hd[0] = drive_get(IF_IDE, 1, 0);
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    hd[1] = drive_get(IF_IDE, 1, 1);
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    hd[3] = hd[2] = NULL;
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    pci_cmd646_ide_init(pci_bus, hd, 0);
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    /* cuda also initialize ADB */
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    cuda_init(&cuda_mem_index, pic[0x12]);
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    adb_kbd_init(&adb_bus);
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    adb_mouse_init(&adb_bus);
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    nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
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    pmac_format_nvram_partition(nvr, 0x2000);
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    macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
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               dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
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               escc_mem_index);
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    if (usb_enabled) {
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        usb_ohci_init_pci(pci_bus, -1);
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    }
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    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
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        graphic_depth = 15;
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    /* No PCI init: the BIOS will do it */
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    fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
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    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
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    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
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    if (kernel_cmdline) {
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        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
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        pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
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    } else {
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        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
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    }
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    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
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    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
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    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
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    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
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    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
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    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
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    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
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    if (kvm_enabled()) {
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#ifdef CONFIG_KVM
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        uint8_t *hypercall;
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        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
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        hypercall = qemu_malloc(16);
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        kvmppc_get_hypercall(env, hypercall, 16);
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        fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
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        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
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#endif
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    } else {
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        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
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    }
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    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
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}
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static QEMUMachine heathrow_machine = {
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    .name = "g3beige",
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    .desc = "Heathrow based PowerMAC",
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    .init = ppc_heathrow_init,
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    .max_cpus = MAX_CPUS,
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#ifndef TARGET_PPC64
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    .is_default = 1,
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#endif
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};
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static void heathrow_machine_init(void)
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{
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    qemu_register_machine(&heathrow_machine);
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}
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machine_init(heathrow_machine_init);