root / hw / char / cadence_uart.c @ 49ab747f
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/*
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* Device model for Cadence UART
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*
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* Copyright (c) 2010 Xilinx Inc.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Written by Haibing Ma
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* M.Habib
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/sysbus.h" |
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#include "char/char.h" |
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#include "qemu/timer.h" |
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|
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#ifdef CADENCE_UART_ERR_DEBUG
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#define DB_PRINT(...) do { \ |
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \ |
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} while (0); |
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#else
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#define DB_PRINT(...)
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#endif
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|
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#define UART_SR_INTR_RTRIG 0x00000001 |
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#define UART_SR_INTR_REMPTY 0x00000002 |
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#define UART_SR_INTR_RFUL 0x00000004 |
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#define UART_SR_INTR_TEMPTY 0x00000008 |
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#define UART_SR_INTR_TFUL 0x00000010 |
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/* bits fields in CSR that correlate to CISR. If any of these bits are set in
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* SR, then the same bit in CISR is set high too */
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#define UART_SR_TO_CISR_MASK 0x0000001F |
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|
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#define UART_INTR_ROVR 0x00000020 |
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#define UART_INTR_FRAME 0x00000040 |
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#define UART_INTR_PARE 0x00000080 |
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#define UART_INTR_TIMEOUT 0x00000100 |
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#define UART_INTR_DMSI 0x00000200 |
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|
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#define UART_SR_RACTIVE 0x00000400 |
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#define UART_SR_TACTIVE 0x00000800 |
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#define UART_SR_FDELT 0x00001000 |
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|
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#define UART_CR_RXRST 0x00000001 |
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#define UART_CR_TXRST 0x00000002 |
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#define UART_CR_RX_EN 0x00000004 |
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#define UART_CR_RX_DIS 0x00000008 |
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#define UART_CR_TX_EN 0x00000010 |
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#define UART_CR_TX_DIS 0x00000020 |
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#define UART_CR_RST_TO 0x00000040 |
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#define UART_CR_STARTBRK 0x00000080 |
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#define UART_CR_STOPBRK 0x00000100 |
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|
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#define UART_MR_CLKS 0x00000001 |
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#define UART_MR_CHRL 0x00000006 |
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#define UART_MR_CHRL_SH 1 |
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#define UART_MR_PAR 0x00000038 |
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#define UART_MR_PAR_SH 3 |
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#define UART_MR_NBSTOP 0x000000C0 |
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#define UART_MR_NBSTOP_SH 6 |
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#define UART_MR_CHMODE 0x00000300 |
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#define UART_MR_CHMODE_SH 8 |
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#define UART_MR_UCLKEN 0x00000400 |
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#define UART_MR_IRMODE 0x00000800 |
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|
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#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) |
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#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) |
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#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) |
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#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) |
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#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) |
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#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) |
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#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) |
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#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) |
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#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) |
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#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) |
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|
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#define RX_FIFO_SIZE 16 |
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#define TX_FIFO_SIZE 16 |
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#define UART_INPUT_CLK 50000000 |
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#define R_CR (0x00/4) |
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#define R_MR (0x04/4) |
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#define R_IER (0x08/4) |
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#define R_IDR (0x0C/4) |
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#define R_IMR (0x10/4) |
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#define R_CISR (0x14/4) |
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#define R_BRGR (0x18/4) |
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#define R_RTOR (0x1C/4) |
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#define R_RTRIG (0x20/4) |
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#define R_MCR (0x24/4) |
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#define R_MSR (0x28/4) |
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#define R_SR (0x2C/4) |
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#define R_TX_RX (0x30/4) |
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#define R_BDIV (0x34/4) |
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#define R_FDEL (0x38/4) |
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#define R_PMIN (0x3C/4) |
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#define R_PWID (0x40/4) |
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#define R_TTRIG (0x44/4) |
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#define R_MAX (R_TTRIG + 1) |
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typedef struct { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint32_t r[R_MAX]; |
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uint8_t r_fifo[RX_FIFO_SIZE]; |
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uint32_t rx_wpos; |
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uint32_t rx_count; |
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uint64_t char_tx_time; |
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CharDriverState *chr; |
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qemu_irq irq; |
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struct QEMUTimer *fifo_trigger_handle;
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struct QEMUTimer *tx_time_handle;
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} UartState; |
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static void uart_update_status(UartState *s) |
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{ |
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s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; |
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qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); |
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} |
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static void fifo_trigger_update(void *opaque) |
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{ |
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UartState *s = (UartState *)opaque; |
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s->r[R_CISR] |= UART_INTR_TIMEOUT; |
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uart_update_status(s); |
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} |
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static void uart_tx_redo(UartState *s) |
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{ |
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uint64_t new_tx_time = qemu_get_clock_ns(vm_clock); |
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qemu_mod_timer(s->tx_time_handle, new_tx_time + s->char_tx_time); |
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s->r[R_SR] |= UART_SR_INTR_TEMPTY; |
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uart_update_status(s); |
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} |
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static void uart_tx_write(void *opaque) |
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{ |
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UartState *s = (UartState *)opaque; |
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uart_tx_redo(s); |
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} |
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static void uart_rx_reset(UartState *s) |
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{ |
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s->rx_wpos = 0;
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s->rx_count = 0;
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qemu_chr_accept_input(s->chr); |
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s->r[R_SR] |= UART_SR_INTR_REMPTY; |
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s->r[R_SR] &= ~UART_SR_INTR_RFUL; |
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} |
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static void uart_tx_reset(UartState *s) |
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{ |
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s->r[R_SR] |= UART_SR_INTR_TEMPTY; |
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s->r[R_SR] &= ~UART_SR_INTR_TFUL; |
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} |
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static void uart_send_breaks(UartState *s) |
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{ |
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int break_enabled = 1; |
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
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&break_enabled); |
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} |
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static void uart_parameters_setup(UartState *s) |
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{ |
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QEMUSerialSetParams ssp; |
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unsigned int baud_rate, packet_size; |
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baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? |
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UART_INPUT_CLK / 8 : UART_INPUT_CLK;
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ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
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packet_size = 1;
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switch (s->r[R_MR] & UART_MR_PAR) {
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case UART_PARITY_EVEN:
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ssp.parity = 'E';
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packet_size++; |
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break;
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case UART_PARITY_ODD:
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ssp.parity = 'O';
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packet_size++; |
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break;
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default:
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ssp.parity = 'N';
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break;
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} |
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switch (s->r[R_MR] & UART_MR_CHRL) {
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case UART_DATA_BITS_6:
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ssp.data_bits = 6;
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break;
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case UART_DATA_BITS_7:
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ssp.data_bits = 7;
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break;
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default:
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ssp.data_bits = 8;
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break;
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} |
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switch (s->r[R_MR] & UART_MR_NBSTOP) {
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case UART_STOP_BITS_1:
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ssp.stop_bits = 1;
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break;
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default:
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ssp.stop_bits = 2;
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break;
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} |
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packet_size += ssp.data_bits + ssp.stop_bits; |
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s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size; |
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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} |
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static int uart_can_receive(void *opaque) |
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{ |
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UartState *s = (UartState *)opaque; |
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return RX_FIFO_SIZE - s->rx_count;
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} |
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static void uart_ctrl_update(UartState *s) |
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{ |
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if (s->r[R_CR] & UART_CR_TXRST) {
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uart_tx_reset(s); |
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} |
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if (s->r[R_CR] & UART_CR_RXRST) {
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uart_rx_reset(s); |
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} |
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s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); |
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if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) {
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uart_tx_redo(s); |
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} |
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if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
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uart_send_breaks(s); |
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} |
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} |
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static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) |
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{ |
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UartState *s = (UartState *)opaque; |
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uint64_t new_rx_time = qemu_get_clock_ns(vm_clock); |
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int i;
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if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
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return;
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} |
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s->r[R_SR] &= ~UART_SR_INTR_REMPTY; |
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if (s->rx_count == RX_FIFO_SIZE) {
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s->r[R_CISR] |= UART_INTR_ROVR; |
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} else {
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for (i = 0; i < size; i++) { |
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s->r_fifo[s->rx_wpos] = buf[i]; |
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s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
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s->rx_count++; |
278 |
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if (s->rx_count == RX_FIFO_SIZE) {
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s->r[R_SR] |= UART_SR_INTR_RFUL; |
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break;
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} |
283 |
|
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if (s->rx_count >= s->r[R_RTRIG]) {
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s->r[R_SR] |= UART_SR_INTR_RTRIG; |
286 |
} |
287 |
} |
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qemu_mod_timer(s->fifo_trigger_handle, new_rx_time + |
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(s->char_tx_time * 4));
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} |
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uart_update_status(s); |
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} |
293 |
|
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static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) |
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{ |
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if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
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return;
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} |
299 |
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while (size) {
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size -= qemu_chr_fe_write(s->chr, buf, size); |
302 |
} |
303 |
} |
304 |
|
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static void uart_receive(void *opaque, const uint8_t *buf, int size) |
306 |
{ |
307 |
UartState *s = (UartState *)opaque; |
308 |
uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; |
309 |
|
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if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
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uart_write_rx_fifo(opaque, buf, size); |
312 |
} |
313 |
if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
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uart_write_tx_fifo(s, buf, size); |
315 |
} |
316 |
} |
317 |
|
318 |
static void uart_event(void *opaque, int event) |
319 |
{ |
320 |
UartState *s = (UartState *)opaque; |
321 |
uint8_t buf = '\0';
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322 |
|
323 |
if (event == CHR_EVENT_BREAK) {
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uart_write_rx_fifo(opaque, &buf, 1);
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} |
326 |
|
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uart_update_status(s); |
328 |
} |
329 |
|
330 |
static void uart_read_rx_fifo(UartState *s, uint32_t *c) |
331 |
{ |
332 |
if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
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333 |
return;
|
334 |
} |
335 |
|
336 |
s->r[R_SR] &= ~UART_SR_INTR_RFUL; |
337 |
|
338 |
if (s->rx_count) {
|
339 |
uint32_t rx_rpos = |
340 |
(RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE; |
341 |
*c = s->r_fifo[rx_rpos]; |
342 |
s->rx_count--; |
343 |
|
344 |
if (!s->rx_count) {
|
345 |
s->r[R_SR] |= UART_SR_INTR_REMPTY; |
346 |
} |
347 |
qemu_chr_accept_input(s->chr); |
348 |
} else {
|
349 |
*c = 0;
|
350 |
s->r[R_SR] |= UART_SR_INTR_REMPTY; |
351 |
} |
352 |
|
353 |
if (s->rx_count < s->r[R_RTRIG]) {
|
354 |
s->r[R_SR] &= ~UART_SR_INTR_RTRIG; |
355 |
} |
356 |
uart_update_status(s); |
357 |
} |
358 |
|
359 |
static void uart_write(void *opaque, hwaddr offset, |
360 |
uint64_t value, unsigned size)
|
361 |
{ |
362 |
UartState *s = (UartState *)opaque; |
363 |
|
364 |
DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); |
365 |
offset >>= 2;
|
366 |
switch (offset) {
|
367 |
case R_IER: /* ier (wts imr) */ |
368 |
s->r[R_IMR] |= value; |
369 |
break;
|
370 |
case R_IDR: /* idr (wtc imr) */ |
371 |
s->r[R_IMR] &= ~value; |
372 |
break;
|
373 |
case R_IMR: /* imr (read only) */ |
374 |
break;
|
375 |
case R_CISR: /* cisr (wtc) */ |
376 |
s->r[R_CISR] &= ~value; |
377 |
break;
|
378 |
case R_TX_RX: /* UARTDR */ |
379 |
switch (s->r[R_MR] & UART_MR_CHMODE) {
|
380 |
case NORMAL_MODE:
|
381 |
uart_write_tx_fifo(s, (uint8_t *) &value, 1);
|
382 |
break;
|
383 |
case LOCAL_LOOPBACK:
|
384 |
uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
|
385 |
break;
|
386 |
} |
387 |
break;
|
388 |
default:
|
389 |
s->r[offset] = value; |
390 |
} |
391 |
|
392 |
switch (offset) {
|
393 |
case R_CR:
|
394 |
uart_ctrl_update(s); |
395 |
break;
|
396 |
case R_MR:
|
397 |
uart_parameters_setup(s); |
398 |
break;
|
399 |
} |
400 |
} |
401 |
|
402 |
static uint64_t uart_read(void *opaque, hwaddr offset, |
403 |
unsigned size)
|
404 |
{ |
405 |
UartState *s = (UartState *)opaque; |
406 |
uint32_t c = 0;
|
407 |
|
408 |
offset >>= 2;
|
409 |
if (offset >= R_MAX) {
|
410 |
c = 0;
|
411 |
} else if (offset == R_TX_RX) { |
412 |
uart_read_rx_fifo(s, &c); |
413 |
} else {
|
414 |
c = s->r[offset]; |
415 |
} |
416 |
|
417 |
DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); |
418 |
return c;
|
419 |
} |
420 |
|
421 |
static const MemoryRegionOps uart_ops = { |
422 |
.read = uart_read, |
423 |
.write = uart_write, |
424 |
.endianness = DEVICE_NATIVE_ENDIAN, |
425 |
}; |
426 |
|
427 |
static void cadence_uart_reset(UartState *s) |
428 |
{ |
429 |
s->r[R_CR] = 0x00000128;
|
430 |
s->r[R_IMR] = 0;
|
431 |
s->r[R_CISR] = 0;
|
432 |
s->r[R_RTRIG] = 0x00000020;
|
433 |
s->r[R_BRGR] = 0x0000000F;
|
434 |
s->r[R_TTRIG] = 0x00000020;
|
435 |
|
436 |
uart_rx_reset(s); |
437 |
uart_tx_reset(s); |
438 |
|
439 |
s->rx_count = 0;
|
440 |
s->rx_wpos = 0;
|
441 |
} |
442 |
|
443 |
static int cadence_uart_init(SysBusDevice *dev) |
444 |
{ |
445 |
UartState *s = FROM_SYSBUS(UartState, dev); |
446 |
|
447 |
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", 0x1000); |
448 |
sysbus_init_mmio(dev, &s->iomem); |
449 |
sysbus_init_irq(dev, &s->irq); |
450 |
|
451 |
s->fifo_trigger_handle = qemu_new_timer_ns(vm_clock, |
452 |
(QEMUTimerCB *)fifo_trigger_update, s); |
453 |
|
454 |
s->tx_time_handle = qemu_new_timer_ns(vm_clock, |
455 |
(QEMUTimerCB *)uart_tx_write, s); |
456 |
|
457 |
s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; |
458 |
|
459 |
s->chr = qemu_char_get_next_serial(); |
460 |
|
461 |
cadence_uart_reset(s); |
462 |
|
463 |
if (s->chr) {
|
464 |
qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive, |
465 |
uart_event, s); |
466 |
} |
467 |
|
468 |
return 0; |
469 |
} |
470 |
|
471 |
static int cadence_uart_post_load(void *opaque, int version_id) |
472 |
{ |
473 |
UartState *s = opaque; |
474 |
|
475 |
uart_parameters_setup(s); |
476 |
uart_update_status(s); |
477 |
return 0; |
478 |
} |
479 |
|
480 |
static const VMStateDescription vmstate_cadence_uart = { |
481 |
.name = "cadence_uart",
|
482 |
.version_id = 1,
|
483 |
.minimum_version_id = 1,
|
484 |
.minimum_version_id_old = 1,
|
485 |
.post_load = cadence_uart_post_load, |
486 |
.fields = (VMStateField[]) { |
487 |
VMSTATE_UINT32_ARRAY(r, UartState, R_MAX), |
488 |
VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE), |
489 |
VMSTATE_UINT32(rx_count, UartState), |
490 |
VMSTATE_UINT32(rx_wpos, UartState), |
491 |
VMSTATE_TIMER(fifo_trigger_handle, UartState), |
492 |
VMSTATE_TIMER(tx_time_handle, UartState), |
493 |
VMSTATE_END_OF_LIST() |
494 |
} |
495 |
}; |
496 |
|
497 |
static void cadence_uart_class_init(ObjectClass *klass, void *data) |
498 |
{ |
499 |
DeviceClass *dc = DEVICE_CLASS(klass); |
500 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
501 |
|
502 |
sdc->init = cadence_uart_init; |
503 |
dc->vmsd = &vmstate_cadence_uart; |
504 |
} |
505 |
|
506 |
static const TypeInfo cadence_uart_info = { |
507 |
.name = "cadence_uart",
|
508 |
.parent = TYPE_SYS_BUS_DEVICE, |
509 |
.instance_size = sizeof(UartState),
|
510 |
.class_init = cadence_uart_class_init, |
511 |
}; |
512 |
|
513 |
static void cadence_uart_register_types(void) |
514 |
{ |
515 |
type_register_static(&cadence_uart_info); |
516 |
} |
517 |
|
518 |
type_init(cadence_uart_register_types) |