root / hw / display / vmware_vga.c @ 49ab747f
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/*
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* QEMU VMware-SVGA "chipset".
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*
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* Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/loader.h" |
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#include "ui/console.h" |
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#include "hw/pci/pci.h" |
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#undef VERBOSE
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#define HW_RECT_ACCEL
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#define HW_FILL_ACCEL
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#define HW_MOUSE_ACCEL
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#include "hw/vga_int.h" |
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/* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
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struct vmsvga_state_s {
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VGACommonState vga; |
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int invalidated;
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int depth;
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int bypp;
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int enable;
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int config;
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struct {
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int id;
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int x;
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int y;
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int on;
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} cursor; |
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int index;
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int scratch_size;
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uint32_t *scratch; |
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int new_width;
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int new_height;
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uint32_t guest; |
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uint32_t svgaid; |
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int syncing;
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MemoryRegion fifo_ram; |
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uint8_t *fifo_ptr; |
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unsigned int fifo_size; |
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union {
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uint32_t *fifo; |
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struct QEMU_PACKED {
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uint32_t min; |
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uint32_t max; |
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uint32_t next_cmd; |
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uint32_t stop; |
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/* Add registers here when adding capabilities. */
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uint32_t fifo[0];
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} *cmd; |
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}; |
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#define REDRAW_FIFO_LEN 512 |
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struct vmsvga_rect_s {
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int x, y, w, h;
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} redraw_fifo[REDRAW_FIFO_LEN]; |
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int redraw_fifo_first, redraw_fifo_last;
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}; |
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struct pci_vmsvga_state_s {
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PCIDevice card; |
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struct vmsvga_state_s chip;
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MemoryRegion io_bar; |
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}; |
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#define SVGA_MAGIC 0x900000UL |
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#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
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#define SVGA_ID_0 SVGA_MAKE_ID(0) |
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#define SVGA_ID_1 SVGA_MAKE_ID(1) |
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#define SVGA_ID_2 SVGA_MAKE_ID(2) |
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#define SVGA_LEGACY_BASE_PORT 0x4560 |
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#define SVGA_INDEX_PORT 0x0 |
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#define SVGA_VALUE_PORT 0x1 |
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#define SVGA_BIOS_PORT 0x2 |
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#define SVGA_VERSION_2
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#ifdef SVGA_VERSION_2
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# define SVGA_ID SVGA_ID_2
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 1 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
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#else
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# define SVGA_ID SVGA_ID_1
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 4 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
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#endif
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enum {
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/* ID 0, 1 and 2 registers */
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SVGA_REG_ID = 0,
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SVGA_REG_ENABLE = 1,
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SVGA_REG_WIDTH = 2,
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SVGA_REG_HEIGHT = 3,
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SVGA_REG_MAX_WIDTH = 4,
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SVGA_REG_MAX_HEIGHT = 5,
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SVGA_REG_DEPTH = 6,
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SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
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SVGA_REG_PSEUDOCOLOR = 8,
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SVGA_REG_RED_MASK = 9,
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SVGA_REG_GREEN_MASK = 10,
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SVGA_REG_BLUE_MASK = 11,
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SVGA_REG_BYTES_PER_LINE = 12,
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SVGA_REG_FB_START = 13,
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SVGA_REG_FB_OFFSET = 14,
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SVGA_REG_VRAM_SIZE = 15,
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SVGA_REG_FB_SIZE = 16,
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/* ID 1 and 2 registers */
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SVGA_REG_CAPABILITIES = 17,
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SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
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SVGA_REG_MEM_SIZE = 19,
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SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
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SVGA_REG_SYNC = 21, /* Write to force synchronization */ |
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SVGA_REG_BUSY = 22, /* Read to check if sync is done */ |
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SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
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SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ |
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SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ |
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SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ |
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SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ |
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SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ |
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SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
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SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
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SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ |
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SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
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SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
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SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
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SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
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}; |
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#define SVGA_CAP_NONE 0 |
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#define SVGA_CAP_RECT_FILL (1 << 0) |
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#define SVGA_CAP_RECT_COPY (1 << 1) |
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#define SVGA_CAP_RECT_PAT_FILL (1 << 2) |
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#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) |
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#define SVGA_CAP_RASTER_OP (1 << 4) |
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#define SVGA_CAP_CURSOR (1 << 5) |
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#define SVGA_CAP_CURSOR_BYPASS (1 << 6) |
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#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) |
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#define SVGA_CAP_8BIT_EMULATION (1 << 8) |
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#define SVGA_CAP_ALPHA_CURSOR (1 << 9) |
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#define SVGA_CAP_GLYPH (1 << 10) |
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#define SVGA_CAP_GLYPH_CLIPPING (1 << 11) |
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#define SVGA_CAP_OFFSCREEN_1 (1 << 12) |
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#define SVGA_CAP_ALPHA_BLEND (1 << 13) |
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#define SVGA_CAP_3D (1 << 14) |
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#define SVGA_CAP_EXTENDED_FIFO (1 << 15) |
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#define SVGA_CAP_MULTIMON (1 << 16) |
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#define SVGA_CAP_PITCHLOCK (1 << 17) |
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/*
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* FIFO offsets (seen as an array of 32-bit words)
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*/
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enum {
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/*
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* The original defined FIFO offsets
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*/
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SVGA_FIFO_MIN = 0,
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SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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SVGA_FIFO_NEXT_CMD, |
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SVGA_FIFO_STOP, |
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/*
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* Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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*/
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SVGA_FIFO_CAPABILITIES = 4,
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SVGA_FIFO_FLAGS, |
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SVGA_FIFO_FENCE, |
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SVGA_FIFO_3D_HWVERSION, |
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SVGA_FIFO_PITCHLOCK, |
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}; |
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#define SVGA_FIFO_CAP_NONE 0 |
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#define SVGA_FIFO_CAP_FENCE (1 << 0) |
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#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) |
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#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) |
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#define SVGA_FIFO_FLAG_NONE 0 |
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#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) |
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/* These values can probably be changed arbitrarily. */
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#define SVGA_SCRATCH_SIZE 0x8000 |
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#define SVGA_MAX_WIDTH 2360 |
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#define SVGA_MAX_HEIGHT 1770 |
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#ifdef VERBOSE
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# define GUEST_OS_BASE 0x5001 |
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static const char *vmsvga_guest_id[] = { |
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[0x00] = "Dos", |
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[0x01] = "Windows 3.1", |
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[0x02] = "Windows 95", |
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[0x03] = "Windows 98", |
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[0x04] = "Windows ME", |
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[0x05] = "Windows NT", |
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[0x06] = "Windows 2000", |
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[0x07] = "Linux", |
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[0x08] = "OS/2", |
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[0x09] = "an unknown OS", |
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[0x0a] = "BSD", |
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[0x0b] = "Whistler", |
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[0x0c] = "an unknown OS", |
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[0x0d] = "an unknown OS", |
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[0x0e] = "an unknown OS", |
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[0x0f] = "an unknown OS", |
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[0x10] = "an unknown OS", |
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[0x11] = "an unknown OS", |
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[0x12] = "an unknown OS", |
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[0x13] = "an unknown OS", |
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[0x14] = "an unknown OS", |
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[0x15] = "Windows 2003", |
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}; |
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#endif
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enum {
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SVGA_CMD_INVALID_CMD = 0,
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SVGA_CMD_UPDATE = 1,
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SVGA_CMD_RECT_FILL = 2,
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SVGA_CMD_RECT_COPY = 3,
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SVGA_CMD_DEFINE_BITMAP = 4,
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SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
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SVGA_CMD_DEFINE_PIXMAP = 6,
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SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
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SVGA_CMD_RECT_BITMAP_FILL = 8,
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SVGA_CMD_RECT_PIXMAP_FILL = 9,
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SVGA_CMD_RECT_BITMAP_COPY = 10,
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SVGA_CMD_RECT_PIXMAP_COPY = 11,
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SVGA_CMD_FREE_OBJECT = 12,
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SVGA_CMD_RECT_ROP_FILL = 13,
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SVGA_CMD_RECT_ROP_COPY = 14,
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SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
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SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
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SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
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SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
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SVGA_CMD_DEFINE_CURSOR = 19,
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SVGA_CMD_DISPLAY_CURSOR = 20,
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SVGA_CMD_MOVE_CURSOR = 21,
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SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
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SVGA_CMD_DRAW_GLYPH = 23,
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SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
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SVGA_CMD_UPDATE_VERBOSE = 25,
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SVGA_CMD_SURFACE_FILL = 26,
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SVGA_CMD_SURFACE_COPY = 27,
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SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
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SVGA_CMD_FRONT_ROP_FILL = 29,
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SVGA_CMD_FENCE = 30,
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}; |
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/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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enum {
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SVGA_CURSOR_ON_HIDE = 0,
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SVGA_CURSOR_ON_SHOW = 1,
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SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
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SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
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}; |
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static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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DisplaySurface *surface = qemu_console_surface(s->vga.con); |
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int line;
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int bypl;
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int width;
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int start;
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uint8_t *src; |
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uint8_t *dst; |
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if (x < 0) { |
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fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x);
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w += x; |
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x = 0;
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} |
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if (w < 0) { |
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fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w);
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w = 0;
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} |
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if (x + w > surface_width(surface)) {
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fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
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__func__, x, w); |
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x = MIN(x, surface_width(surface)); |
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w = surface_width(surface) - x; |
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} |
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if (y < 0) { |
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fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y);
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h += y; |
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y = 0;
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} |
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if (h < 0) { |
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fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h);
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h = 0;
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} |
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if (y + h > surface_height(surface)) {
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fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
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__func__, y, h); |
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y = MIN(y, surface_height(surface)); |
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h = surface_height(surface) - y; |
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} |
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bypl = surface_stride(surface); |
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width = surface_bytes_per_pixel(surface) * w; |
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start = surface_bytes_per_pixel(surface) * x + bypl * y; |
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src = s->vga.vram_ptr + start; |
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dst = surface_data(surface) + start; |
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for (line = h; line > 0; line--, src += bypl, dst += bypl) { |
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memcpy(dst, src, width); |
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} |
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dpy_gfx_update(s->vga.con, x, y, w, h); |
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} |
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static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
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s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
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rect->x = x; |
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rect->y = y; |
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rect->w = w; |
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rect->h = h; |
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} |
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static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) |
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{ |
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struct vmsvga_rect_s *rect;
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if (s->invalidated) {
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s->redraw_fifo_first = s->redraw_fifo_last; |
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return;
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} |
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/* Overlapping region updates can be optimised out here - if someone
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* knows a smart algorithm to do that, please share. */
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while (s->redraw_fifo_first != s->redraw_fifo_last) {
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rect = &s->redraw_fifo[s->redraw_fifo_first++]; |
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s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
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vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); |
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} |
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} |
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|
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#ifdef HW_RECT_ACCEL
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static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, |
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int x0, int y0, int x1, int y1, int w, int h) |
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{ |
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DisplaySurface *surface = qemu_console_surface(s->vga.con); |
375 |
uint8_t *vram = s->vga.vram_ptr; |
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int bypl = surface_stride(surface);
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int bypp = surface_bytes_per_pixel(surface);
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int width = bypp * w;
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int line = h;
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uint8_t *ptr[2];
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|
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if (y1 > y0) {
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ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); |
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ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); |
385 |
for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { |
386 |
memmove(ptr[1], ptr[0], width); |
387 |
} |
388 |
} else {
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ptr[0] = vram + bypp * x0 + bypl * y0;
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ptr[1] = vram + bypp * x1 + bypl * y1;
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for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { |
392 |
memmove(ptr[1], ptr[0], width); |
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} |
394 |
} |
395 |
|
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vmsvga_update_rect_delayed(s, x1, y1, w, h); |
397 |
} |
398 |
#endif
|
399 |
|
400 |
#ifdef HW_FILL_ACCEL
|
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static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, |
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uint32_t c, int x, int y, int w, int h) |
403 |
{ |
404 |
DisplaySurface *surface = qemu_console_surface(s->vga.con); |
405 |
int bypl = surface_stride(surface);
|
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int width = surface_bytes_per_pixel(surface) * w;
|
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int line = h;
|
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int column;
|
409 |
uint8_t *fst; |
410 |
uint8_t *dst; |
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uint8_t *src; |
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uint8_t col[4];
|
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|
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col[0] = c;
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col[1] = c >> 8; |
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col[2] = c >> 16; |
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col[3] = c >> 24; |
418 |
|
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fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; |
420 |
|
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if (line--) {
|
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dst = fst; |
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src = col; |
424 |
for (column = width; column > 0; column--) { |
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*(dst++) = *(src++); |
426 |
if (src - col == surface_bytes_per_pixel(surface)) {
|
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src = col; |
428 |
} |
429 |
} |
430 |
dst = fst; |
431 |
for (; line > 0; line--) { |
432 |
dst += bypl; |
433 |
memcpy(dst, fst, width); |
434 |
} |
435 |
} |
436 |
|
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vmsvga_update_rect_delayed(s, x, y, w, h); |
438 |
} |
439 |
#endif
|
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|
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struct vmsvga_cursor_definition_s {
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int width;
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int height;
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int id;
|
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int bpp;
|
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int hot_x;
|
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int hot_y;
|
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uint32_t mask[1024];
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uint32_t image[4096];
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}; |
451 |
|
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#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
453 |
#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) |
454 |
|
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#ifdef HW_MOUSE_ACCEL
|
456 |
static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, |
457 |
struct vmsvga_cursor_definition_s *c)
|
458 |
{ |
459 |
QEMUCursor *qc; |
460 |
int i, pixels;
|
461 |
|
462 |
qc = cursor_alloc(c->width, c->height); |
463 |
qc->hot_x = c->hot_x; |
464 |
qc->hot_y = c->hot_y; |
465 |
switch (c->bpp) {
|
466 |
case 1: |
467 |
cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, |
468 |
1, (void *)c->mask); |
469 |
#ifdef DEBUG
|
470 |
cursor_print_ascii_art(qc, "vmware/mono");
|
471 |
#endif
|
472 |
break;
|
473 |
case 32: |
474 |
/* fill alpha channel from mask, set color to zero */
|
475 |
cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, |
476 |
1, (void *)c->mask); |
477 |
/* add in rgb values */
|
478 |
pixels = c->width * c->height; |
479 |
for (i = 0; i < pixels; i++) { |
480 |
qc->data[i] |= c->image[i] & 0xffffff;
|
481 |
} |
482 |
#ifdef DEBUG
|
483 |
cursor_print_ascii_art(qc, "vmware/32bit");
|
484 |
#endif
|
485 |
break;
|
486 |
default:
|
487 |
fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
|
488 |
__func__, c->bpp); |
489 |
cursor_put(qc); |
490 |
qc = cursor_builtin_left_ptr(); |
491 |
} |
492 |
|
493 |
dpy_cursor_define(s->vga.con, qc); |
494 |
cursor_put(qc); |
495 |
} |
496 |
#endif
|
497 |
|
498 |
#define CMD(f) le32_to_cpu(s->cmd->f)
|
499 |
|
500 |
static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) |
501 |
{ |
502 |
int num;
|
503 |
|
504 |
if (!s->config || !s->enable) {
|
505 |
return 0; |
506 |
} |
507 |
num = CMD(next_cmd) - CMD(stop); |
508 |
if (num < 0) { |
509 |
num += CMD(max) - CMD(min); |
510 |
} |
511 |
return num >> 2; |
512 |
} |
513 |
|
514 |
static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
515 |
{ |
516 |
uint32_t cmd = s->fifo[CMD(stop) >> 2];
|
517 |
|
518 |
s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
|
519 |
if (CMD(stop) >= CMD(max)) {
|
520 |
s->cmd->stop = s->cmd->min; |
521 |
} |
522 |
return cmd;
|
523 |
} |
524 |
|
525 |
static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
526 |
{ |
527 |
return le32_to_cpu(vmsvga_fifo_read_raw(s));
|
528 |
} |
529 |
|
530 |
static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
531 |
{ |
532 |
uint32_t cmd, colour; |
533 |
int args, len;
|
534 |
int x, y, dx, dy, width, height;
|
535 |
struct vmsvga_cursor_definition_s cursor;
|
536 |
uint32_t cmd_start; |
537 |
|
538 |
len = vmsvga_fifo_length(s); |
539 |
while (len > 0) { |
540 |
/* May need to go back to the start of the command if incomplete */
|
541 |
cmd_start = s->cmd->stop; |
542 |
|
543 |
switch (cmd = vmsvga_fifo_read(s)) {
|
544 |
case SVGA_CMD_UPDATE:
|
545 |
case SVGA_CMD_UPDATE_VERBOSE:
|
546 |
len -= 5;
|
547 |
if (len < 0) { |
548 |
goto rewind;
|
549 |
} |
550 |
|
551 |
x = vmsvga_fifo_read(s); |
552 |
y = vmsvga_fifo_read(s); |
553 |
width = vmsvga_fifo_read(s); |
554 |
height = vmsvga_fifo_read(s); |
555 |
vmsvga_update_rect_delayed(s, x, y, width, height); |
556 |
break;
|
557 |
|
558 |
case SVGA_CMD_RECT_FILL:
|
559 |
len -= 6;
|
560 |
if (len < 0) { |
561 |
goto rewind;
|
562 |
} |
563 |
|
564 |
colour = vmsvga_fifo_read(s); |
565 |
x = vmsvga_fifo_read(s); |
566 |
y = vmsvga_fifo_read(s); |
567 |
width = vmsvga_fifo_read(s); |
568 |
height = vmsvga_fifo_read(s); |
569 |
#ifdef HW_FILL_ACCEL
|
570 |
vmsvga_fill_rect(s, colour, x, y, width, height); |
571 |
break;
|
572 |
#else
|
573 |
args = 0;
|
574 |
goto badcmd;
|
575 |
#endif
|
576 |
|
577 |
case SVGA_CMD_RECT_COPY:
|
578 |
len -= 7;
|
579 |
if (len < 0) { |
580 |
goto rewind;
|
581 |
} |
582 |
|
583 |
x = vmsvga_fifo_read(s); |
584 |
y = vmsvga_fifo_read(s); |
585 |
dx = vmsvga_fifo_read(s); |
586 |
dy = vmsvga_fifo_read(s); |
587 |
width = vmsvga_fifo_read(s); |
588 |
height = vmsvga_fifo_read(s); |
589 |
#ifdef HW_RECT_ACCEL
|
590 |
vmsvga_copy_rect(s, x, y, dx, dy, width, height); |
591 |
break;
|
592 |
#else
|
593 |
args = 0;
|
594 |
goto badcmd;
|
595 |
#endif
|
596 |
|
597 |
case SVGA_CMD_DEFINE_CURSOR:
|
598 |
len -= 8;
|
599 |
if (len < 0) { |
600 |
goto rewind;
|
601 |
} |
602 |
|
603 |
cursor.id = vmsvga_fifo_read(s); |
604 |
cursor.hot_x = vmsvga_fifo_read(s); |
605 |
cursor.hot_y = vmsvga_fifo_read(s); |
606 |
cursor.width = x = vmsvga_fifo_read(s); |
607 |
cursor.height = y = vmsvga_fifo_read(s); |
608 |
vmsvga_fifo_read(s); |
609 |
cursor.bpp = vmsvga_fifo_read(s); |
610 |
|
611 |
args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); |
612 |
if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || |
613 |
SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
|
614 |
goto badcmd;
|
615 |
} |
616 |
|
617 |
len -= args; |
618 |
if (len < 0) { |
619 |
goto rewind;
|
620 |
} |
621 |
|
622 |
for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { |
623 |
cursor.mask[args] = vmsvga_fifo_read_raw(s); |
624 |
} |
625 |
for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { |
626 |
cursor.image[args] = vmsvga_fifo_read_raw(s); |
627 |
} |
628 |
#ifdef HW_MOUSE_ACCEL
|
629 |
vmsvga_cursor_define(s, &cursor); |
630 |
break;
|
631 |
#else
|
632 |
args = 0;
|
633 |
goto badcmd;
|
634 |
#endif
|
635 |
|
636 |
/*
|
637 |
* Other commands that we at least know the number of arguments
|
638 |
* for so we can avoid FIFO desync if driver uses them illegally.
|
639 |
*/
|
640 |
case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
641 |
len -= 6;
|
642 |
if (len < 0) { |
643 |
goto rewind;
|
644 |
} |
645 |
vmsvga_fifo_read(s); |
646 |
vmsvga_fifo_read(s); |
647 |
vmsvga_fifo_read(s); |
648 |
x = vmsvga_fifo_read(s); |
649 |
y = vmsvga_fifo_read(s); |
650 |
args = x * y; |
651 |
goto badcmd;
|
652 |
case SVGA_CMD_RECT_ROP_FILL:
|
653 |
args = 6;
|
654 |
goto badcmd;
|
655 |
case SVGA_CMD_RECT_ROP_COPY:
|
656 |
args = 7;
|
657 |
goto badcmd;
|
658 |
case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
659 |
len -= 4;
|
660 |
if (len < 0) { |
661 |
goto rewind;
|
662 |
} |
663 |
vmsvga_fifo_read(s); |
664 |
vmsvga_fifo_read(s); |
665 |
args = 7 + (vmsvga_fifo_read(s) >> 2); |
666 |
goto badcmd;
|
667 |
case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
668 |
args = 12;
|
669 |
goto badcmd;
|
670 |
|
671 |
/*
|
672 |
* Other commands that are not listed as depending on any
|
673 |
* CAPABILITIES bits, but are not described in the README either.
|
674 |
*/
|
675 |
case SVGA_CMD_SURFACE_FILL:
|
676 |
case SVGA_CMD_SURFACE_COPY:
|
677 |
case SVGA_CMD_FRONT_ROP_FILL:
|
678 |
case SVGA_CMD_FENCE:
|
679 |
case SVGA_CMD_INVALID_CMD:
|
680 |
break; /* Nop */ |
681 |
|
682 |
default:
|
683 |
args = 0;
|
684 |
badcmd:
|
685 |
len -= args; |
686 |
if (len < 0) { |
687 |
goto rewind;
|
688 |
} |
689 |
while (args--) {
|
690 |
vmsvga_fifo_read(s); |
691 |
} |
692 |
printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
693 |
__func__, cmd); |
694 |
break;
|
695 |
|
696 |
rewind:
|
697 |
s->cmd->stop = cmd_start; |
698 |
break;
|
699 |
} |
700 |
} |
701 |
|
702 |
s->syncing = 0;
|
703 |
} |
704 |
|
705 |
static uint32_t vmsvga_index_read(void *opaque, uint32_t address) |
706 |
{ |
707 |
struct vmsvga_state_s *s = opaque;
|
708 |
|
709 |
return s->index;
|
710 |
} |
711 |
|
712 |
static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) |
713 |
{ |
714 |
struct vmsvga_state_s *s = opaque;
|
715 |
|
716 |
s->index = index; |
717 |
} |
718 |
|
719 |
static uint32_t vmsvga_value_read(void *opaque, uint32_t address) |
720 |
{ |
721 |
uint32_t caps; |
722 |
struct vmsvga_state_s *s = opaque;
|
723 |
DisplaySurface *surface = qemu_console_surface(s->vga.con); |
724 |
|
725 |
switch (s->index) {
|
726 |
case SVGA_REG_ID:
|
727 |
return s->svgaid;
|
728 |
|
729 |
case SVGA_REG_ENABLE:
|
730 |
return s->enable;
|
731 |
|
732 |
case SVGA_REG_WIDTH:
|
733 |
return surface_width(surface);
|
734 |
|
735 |
case SVGA_REG_HEIGHT:
|
736 |
return surface_height(surface);
|
737 |
|
738 |
case SVGA_REG_MAX_WIDTH:
|
739 |
return SVGA_MAX_WIDTH;
|
740 |
|
741 |
case SVGA_REG_MAX_HEIGHT:
|
742 |
return SVGA_MAX_HEIGHT;
|
743 |
|
744 |
case SVGA_REG_DEPTH:
|
745 |
return s->depth;
|
746 |
|
747 |
case SVGA_REG_BITS_PER_PIXEL:
|
748 |
return (s->depth + 7) & ~7; |
749 |
|
750 |
case SVGA_REG_PSEUDOCOLOR:
|
751 |
return 0x0; |
752 |
|
753 |
case SVGA_REG_RED_MASK:
|
754 |
return surface->pf.rmask;
|
755 |
|
756 |
case SVGA_REG_GREEN_MASK:
|
757 |
return surface->pf.gmask;
|
758 |
|
759 |
case SVGA_REG_BLUE_MASK:
|
760 |
return surface->pf.bmask;
|
761 |
|
762 |
case SVGA_REG_BYTES_PER_LINE:
|
763 |
return s->bypp * s->new_width;
|
764 |
|
765 |
case SVGA_REG_FB_START: {
|
766 |
struct pci_vmsvga_state_s *pci_vmsvga
|
767 |
= container_of(s, struct pci_vmsvga_state_s, chip);
|
768 |
return pci_get_bar_addr(&pci_vmsvga->card, 1); |
769 |
} |
770 |
|
771 |
case SVGA_REG_FB_OFFSET:
|
772 |
return 0x0; |
773 |
|
774 |
case SVGA_REG_VRAM_SIZE:
|
775 |
return s->vga.vram_size; /* No physical VRAM besides the framebuffer */ |
776 |
|
777 |
case SVGA_REG_FB_SIZE:
|
778 |
return s->vga.vram_size;
|
779 |
|
780 |
case SVGA_REG_CAPABILITIES:
|
781 |
caps = SVGA_CAP_NONE; |
782 |
#ifdef HW_RECT_ACCEL
|
783 |
caps |= SVGA_CAP_RECT_COPY; |
784 |
#endif
|
785 |
#ifdef HW_FILL_ACCEL
|
786 |
caps |= SVGA_CAP_RECT_FILL; |
787 |
#endif
|
788 |
#ifdef HW_MOUSE_ACCEL
|
789 |
if (dpy_cursor_define_supported(s->vga.con)) {
|
790 |
caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
791 |
SVGA_CAP_CURSOR_BYPASS; |
792 |
} |
793 |
#endif
|
794 |
return caps;
|
795 |
|
796 |
case SVGA_REG_MEM_START: {
|
797 |
struct pci_vmsvga_state_s *pci_vmsvga
|
798 |
= container_of(s, struct pci_vmsvga_state_s, chip);
|
799 |
return pci_get_bar_addr(&pci_vmsvga->card, 2); |
800 |
} |
801 |
|
802 |
case SVGA_REG_MEM_SIZE:
|
803 |
return s->fifo_size;
|
804 |
|
805 |
case SVGA_REG_CONFIG_DONE:
|
806 |
return s->config;
|
807 |
|
808 |
case SVGA_REG_SYNC:
|
809 |
case SVGA_REG_BUSY:
|
810 |
return s->syncing;
|
811 |
|
812 |
case SVGA_REG_GUEST_ID:
|
813 |
return s->guest;
|
814 |
|
815 |
case SVGA_REG_CURSOR_ID:
|
816 |
return s->cursor.id;
|
817 |
|
818 |
case SVGA_REG_CURSOR_X:
|
819 |
return s->cursor.x;
|
820 |
|
821 |
case SVGA_REG_CURSOR_Y:
|
822 |
return s->cursor.x;
|
823 |
|
824 |
case SVGA_REG_CURSOR_ON:
|
825 |
return s->cursor.on;
|
826 |
|
827 |
case SVGA_REG_HOST_BITS_PER_PIXEL:
|
828 |
return (s->depth + 7) & ~7; |
829 |
|
830 |
case SVGA_REG_SCRATCH_SIZE:
|
831 |
return s->scratch_size;
|
832 |
|
833 |
case SVGA_REG_MEM_REGS:
|
834 |
case SVGA_REG_NUM_DISPLAYS:
|
835 |
case SVGA_REG_PITCHLOCK:
|
836 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
837 |
return 0; |
838 |
|
839 |
default:
|
840 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
841 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
842 |
return s->scratch[s->index - SVGA_SCRATCH_BASE];
|
843 |
} |
844 |
printf("%s: Bad register %02x\n", __func__, s->index);
|
845 |
} |
846 |
|
847 |
return 0; |
848 |
} |
849 |
|
850 |
static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) |
851 |
{ |
852 |
struct vmsvga_state_s *s = opaque;
|
853 |
|
854 |
switch (s->index) {
|
855 |
case SVGA_REG_ID:
|
856 |
if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
|
857 |
s->svgaid = value; |
858 |
} |
859 |
break;
|
860 |
|
861 |
case SVGA_REG_ENABLE:
|
862 |
s->enable = !!value; |
863 |
s->invalidated = 1;
|
864 |
s->vga.invalidate(&s->vga); |
865 |
if (s->enable && s->config) {
|
866 |
vga_dirty_log_stop(&s->vga); |
867 |
} else {
|
868 |
vga_dirty_log_start(&s->vga); |
869 |
} |
870 |
break;
|
871 |
|
872 |
case SVGA_REG_WIDTH:
|
873 |
if (value <= SVGA_MAX_WIDTH) {
|
874 |
s->new_width = value; |
875 |
s->invalidated = 1;
|
876 |
} else {
|
877 |
printf("%s: Bad width: %i\n", __func__, value);
|
878 |
} |
879 |
break;
|
880 |
|
881 |
case SVGA_REG_HEIGHT:
|
882 |
if (value <= SVGA_MAX_HEIGHT) {
|
883 |
s->new_height = value; |
884 |
s->invalidated = 1;
|
885 |
} else {
|
886 |
printf("%s: Bad height: %i\n", __func__, value);
|
887 |
} |
888 |
break;
|
889 |
|
890 |
case SVGA_REG_BITS_PER_PIXEL:
|
891 |
if (value != s->depth) {
|
892 |
printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
|
893 |
s->config = 0;
|
894 |
} |
895 |
break;
|
896 |
|
897 |
case SVGA_REG_CONFIG_DONE:
|
898 |
if (value) {
|
899 |
s->fifo = (uint32_t *) s->fifo_ptr; |
900 |
/* Check range and alignment. */
|
901 |
if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { |
902 |
break;
|
903 |
} |
904 |
if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
|
905 |
break;
|
906 |
} |
907 |
if (CMD(max) > SVGA_FIFO_SIZE) {
|
908 |
break;
|
909 |
} |
910 |
if (CMD(max) < CMD(min) + 10 * 1024) { |
911 |
break;
|
912 |
} |
913 |
vga_dirty_log_stop(&s->vga); |
914 |
} |
915 |
s->config = !!value; |
916 |
break;
|
917 |
|
918 |
case SVGA_REG_SYNC:
|
919 |
s->syncing = 1;
|
920 |
vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
921 |
break;
|
922 |
|
923 |
case SVGA_REG_GUEST_ID:
|
924 |
s->guest = value; |
925 |
#ifdef VERBOSE
|
926 |
if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
927 |
ARRAY_SIZE(vmsvga_guest_id)) { |
928 |
printf("%s: guest runs %s.\n", __func__,
|
929 |
vmsvga_guest_id[value - GUEST_OS_BASE]); |
930 |
} |
931 |
#endif
|
932 |
break;
|
933 |
|
934 |
case SVGA_REG_CURSOR_ID:
|
935 |
s->cursor.id = value; |
936 |
break;
|
937 |
|
938 |
case SVGA_REG_CURSOR_X:
|
939 |
s->cursor.x = value; |
940 |
break;
|
941 |
|
942 |
case SVGA_REG_CURSOR_Y:
|
943 |
s->cursor.y = value; |
944 |
break;
|
945 |
|
946 |
case SVGA_REG_CURSOR_ON:
|
947 |
s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); |
948 |
s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); |
949 |
#ifdef HW_MOUSE_ACCEL
|
950 |
if (value <= SVGA_CURSOR_ON_SHOW) {
|
951 |
dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); |
952 |
} |
953 |
#endif
|
954 |
break;
|
955 |
|
956 |
case SVGA_REG_DEPTH:
|
957 |
case SVGA_REG_MEM_REGS:
|
958 |
case SVGA_REG_NUM_DISPLAYS:
|
959 |
case SVGA_REG_PITCHLOCK:
|
960 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
961 |
break;
|
962 |
|
963 |
default:
|
964 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
965 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
966 |
s->scratch[s->index - SVGA_SCRATCH_BASE] = value; |
967 |
break;
|
968 |
} |
969 |
printf("%s: Bad register %02x\n", __func__, s->index);
|
970 |
} |
971 |
} |
972 |
|
973 |
static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) |
974 |
{ |
975 |
printf("%s: what are we supposed to return?\n", __func__);
|
976 |
return 0xcafe; |
977 |
} |
978 |
|
979 |
static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) |
980 |
{ |
981 |
printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
|
982 |
} |
983 |
|
984 |
static inline void vmsvga_check_size(struct vmsvga_state_s *s) |
985 |
{ |
986 |
DisplaySurface *surface = qemu_console_surface(s->vga.con); |
987 |
|
988 |
if (s->new_width != surface_width(surface) ||
|
989 |
s->new_height != surface_height(surface)) { |
990 |
qemu_console_resize(s->vga.con, s->new_width, s->new_height); |
991 |
s->invalidated = 1;
|
992 |
} |
993 |
} |
994 |
|
995 |
static void vmsvga_update_display(void *opaque) |
996 |
{ |
997 |
struct vmsvga_state_s *s = opaque;
|
998 |
DisplaySurface *surface = qemu_console_surface(s->vga.con); |
999 |
bool dirty = false; |
1000 |
|
1001 |
if (!s->enable) {
|
1002 |
s->vga.update(&s->vga); |
1003 |
return;
|
1004 |
} |
1005 |
|
1006 |
vmsvga_check_size(s); |
1007 |
|
1008 |
vmsvga_fifo_run(s); |
1009 |
vmsvga_update_rect_flush(s); |
1010 |
|
1011 |
/*
|
1012 |
* Is it more efficient to look at vram VGA-dirty bits or wait
|
1013 |
* for the driver to issue SVGA_CMD_UPDATE?
|
1014 |
*/
|
1015 |
if (memory_region_is_logging(&s->vga.vram)) {
|
1016 |
vga_sync_dirty_bitmap(&s->vga); |
1017 |
dirty = memory_region_get_dirty(&s->vga.vram, 0,
|
1018 |
surface_stride(surface) * surface_height(surface), |
1019 |
DIRTY_MEMORY_VGA); |
1020 |
} |
1021 |
if (s->invalidated || dirty) {
|
1022 |
s->invalidated = 0;
|
1023 |
memcpy(surface_data(surface), s->vga.vram_ptr, |
1024 |
surface_stride(surface) * surface_height(surface)); |
1025 |
dpy_gfx_update(s->vga.con, 0, 0, |
1026 |
surface_width(surface), surface_height(surface)); |
1027 |
} |
1028 |
if (dirty) {
|
1029 |
memory_region_reset_dirty(&s->vga.vram, 0,
|
1030 |
surface_stride(surface) * surface_height(surface), |
1031 |
DIRTY_MEMORY_VGA); |
1032 |
} |
1033 |
} |
1034 |
|
1035 |
static void vmsvga_reset(DeviceState *dev) |
1036 |
{ |
1037 |
struct pci_vmsvga_state_s *pci =
|
1038 |
DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
|
1039 |
struct vmsvga_state_s *s = &pci->chip;
|
1040 |
|
1041 |
s->index = 0;
|
1042 |
s->enable = 0;
|
1043 |
s->config = 0;
|
1044 |
s->svgaid = SVGA_ID; |
1045 |
s->cursor.on = 0;
|
1046 |
s->redraw_fifo_first = 0;
|
1047 |
s->redraw_fifo_last = 0;
|
1048 |
s->syncing = 0;
|
1049 |
|
1050 |
vga_dirty_log_start(&s->vga); |
1051 |
} |
1052 |
|
1053 |
static void vmsvga_invalidate_display(void *opaque) |
1054 |
{ |
1055 |
struct vmsvga_state_s *s = opaque;
|
1056 |
if (!s->enable) {
|
1057 |
s->vga.invalidate(&s->vga); |
1058 |
return;
|
1059 |
} |
1060 |
|
1061 |
s->invalidated = 1;
|
1062 |
} |
1063 |
|
1064 |
/* save the vga display in a PPM image even if no display is
|
1065 |
available */
|
1066 |
static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch, |
1067 |
Error **errp) |
1068 |
{ |
1069 |
struct vmsvga_state_s *s = opaque;
|
1070 |
DisplaySurface *surface = qemu_console_surface(s->vga.con); |
1071 |
|
1072 |
if (!s->enable) {
|
1073 |
s->vga.screen_dump(&s->vga, filename, cswitch, errp); |
1074 |
return;
|
1075 |
} |
1076 |
|
1077 |
if (surface_bits_per_pixel(surface) == 32) { |
1078 |
DisplaySurface *ds = qemu_create_displaysurface_from( |
1079 |
surface_width(surface), |
1080 |
surface_height(surface), |
1081 |
32,
|
1082 |
surface_stride(surface), |
1083 |
s->vga.vram_ptr, false);
|
1084 |
ppm_save(filename, ds, errp); |
1085 |
g_free(ds); |
1086 |
} |
1087 |
} |
1088 |
|
1089 |
static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
1090 |
{ |
1091 |
struct vmsvga_state_s *s = opaque;
|
1092 |
|
1093 |
if (s->vga.text_update) {
|
1094 |
s->vga.text_update(&s->vga, chardata); |
1095 |
} |
1096 |
} |
1097 |
|
1098 |
static int vmsvga_post_load(void *opaque, int version_id) |
1099 |
{ |
1100 |
struct vmsvga_state_s *s = opaque;
|
1101 |
|
1102 |
s->invalidated = 1;
|
1103 |
if (s->config) {
|
1104 |
s->fifo = (uint32_t *) s->fifo_ptr; |
1105 |
} |
1106 |
return 0; |
1107 |
} |
1108 |
|
1109 |
static const VMStateDescription vmstate_vmware_vga_internal = { |
1110 |
.name = "vmware_vga_internal",
|
1111 |
.version_id = 0,
|
1112 |
.minimum_version_id = 0,
|
1113 |
.minimum_version_id_old = 0,
|
1114 |
.post_load = vmsvga_post_load, |
1115 |
.fields = (VMStateField[]) { |
1116 |
VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
|
1117 |
VMSTATE_INT32(enable, struct vmsvga_state_s),
|
1118 |
VMSTATE_INT32(config, struct vmsvga_state_s),
|
1119 |
VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
|
1120 |
VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
|
1121 |
VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
|
1122 |
VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
|
1123 |
VMSTATE_INT32(index, struct vmsvga_state_s),
|
1124 |
VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
|
1125 |
scratch_size, 0, vmstate_info_uint32, uint32_t),
|
1126 |
VMSTATE_INT32(new_width, struct vmsvga_state_s),
|
1127 |
VMSTATE_INT32(new_height, struct vmsvga_state_s),
|
1128 |
VMSTATE_UINT32(guest, struct vmsvga_state_s),
|
1129 |
VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
|
1130 |
VMSTATE_INT32(syncing, struct vmsvga_state_s),
|
1131 |
VMSTATE_UNUSED(4), /* was fb_size */ |
1132 |
VMSTATE_END_OF_LIST() |
1133 |
} |
1134 |
}; |
1135 |
|
1136 |
static const VMStateDescription vmstate_vmware_vga = { |
1137 |
.name = "vmware_vga",
|
1138 |
.version_id = 0,
|
1139 |
.minimum_version_id = 0,
|
1140 |
.minimum_version_id_old = 0,
|
1141 |
.fields = (VMStateField[]) { |
1142 |
VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
|
1143 |
VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, |
1144 |
vmstate_vmware_vga_internal, struct vmsvga_state_s),
|
1145 |
VMSTATE_END_OF_LIST() |
1146 |
} |
1147 |
}; |
1148 |
|
1149 |
static void vmsvga_init(struct vmsvga_state_s *s, |
1150 |
MemoryRegion *address_space, MemoryRegion *io) |
1151 |
{ |
1152 |
DisplaySurface *surface; |
1153 |
|
1154 |
s->scratch_size = SVGA_SCRATCH_SIZE; |
1155 |
s->scratch = g_malloc(s->scratch_size * 4);
|
1156 |
|
1157 |
s->vga.con = graphic_console_init(vmsvga_update_display, |
1158 |
vmsvga_invalidate_display, |
1159 |
vmsvga_screen_dump, |
1160 |
vmsvga_text_update, s); |
1161 |
surface = qemu_console_surface(s->vga.con); |
1162 |
|
1163 |
s->fifo_size = SVGA_FIFO_SIZE; |
1164 |
memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
|
1165 |
vmstate_register_ram_global(&s->fifo_ram); |
1166 |
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); |
1167 |
|
1168 |
vga_common_init(&s->vga); |
1169 |
vga_init(&s->vga, address_space, io, true);
|
1170 |
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); |
1171 |
/* Save some values here in case they are changed later.
|
1172 |
* This is suspicious and needs more though why it is needed. */
|
1173 |
s->depth = surface_bits_per_pixel(surface); |
1174 |
s->bypp = surface_bytes_per_pixel(surface); |
1175 |
} |
1176 |
|
1177 |
static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) |
1178 |
{ |
1179 |
struct vmsvga_state_s *s = opaque;
|
1180 |
|
1181 |
switch (addr) {
|
1182 |
case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); |
1183 |
case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); |
1184 |
case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); |
1185 |
default: return -1u; |
1186 |
} |
1187 |
} |
1188 |
|
1189 |
static void vmsvga_io_write(void *opaque, hwaddr addr, |
1190 |
uint64_t data, unsigned size)
|
1191 |
{ |
1192 |
struct vmsvga_state_s *s = opaque;
|
1193 |
|
1194 |
switch (addr) {
|
1195 |
case SVGA_IO_MUL * SVGA_INDEX_PORT:
|
1196 |
vmsvga_index_write(s, addr, data); |
1197 |
break;
|
1198 |
case SVGA_IO_MUL * SVGA_VALUE_PORT:
|
1199 |
vmsvga_value_write(s, addr, data); |
1200 |
break;
|
1201 |
case SVGA_IO_MUL * SVGA_BIOS_PORT:
|
1202 |
vmsvga_bios_write(s, addr, data); |
1203 |
break;
|
1204 |
} |
1205 |
} |
1206 |
|
1207 |
static const MemoryRegionOps vmsvga_io_ops = { |
1208 |
.read = vmsvga_io_read, |
1209 |
.write = vmsvga_io_write, |
1210 |
.endianness = DEVICE_LITTLE_ENDIAN, |
1211 |
.valid = { |
1212 |
.min_access_size = 4,
|
1213 |
.max_access_size = 4,
|
1214 |
}, |
1215 |
}; |
1216 |
|
1217 |
static int pci_vmsvga_initfn(PCIDevice *dev) |
1218 |
{ |
1219 |
struct pci_vmsvga_state_s *s =
|
1220 |
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
|
1221 |
|
1222 |
s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ |
1223 |
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ |
1224 |
s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ |
1225 |
|
1226 |
memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip, |
1227 |
"vmsvga-io", 0x10); |
1228 |
memory_region_set_flush_coalesced(&s->io_bar); |
1229 |
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
1230 |
|
1231 |
vmsvga_init(&s->chip, pci_address_space(dev), pci_address_space_io(dev)); |
1232 |
|
1233 |
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
|
1234 |
&s->chip.vga.vram); |
1235 |
pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
|
1236 |
&s->chip.fifo_ram); |
1237 |
|
1238 |
if (!dev->rom_bar) {
|
1239 |
/* compatibility with pc-0.13 and older */
|
1240 |
vga_init_vbe(&s->chip.vga, pci_address_space(dev)); |
1241 |
} |
1242 |
|
1243 |
return 0; |
1244 |
} |
1245 |
|
1246 |
static Property vga_vmware_properties[] = {
|
1247 |
DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, |
1248 |
chip.vga.vram_size_mb, 16),
|
1249 |
DEFINE_PROP_END_OF_LIST(), |
1250 |
}; |
1251 |
|
1252 |
static void vmsvga_class_init(ObjectClass *klass, void *data) |
1253 |
{ |
1254 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1255 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1256 |
|
1257 |
k->no_hotplug = 1;
|
1258 |
k->init = pci_vmsvga_initfn; |
1259 |
k->romfile = "vgabios-vmware.bin";
|
1260 |
k->vendor_id = PCI_VENDOR_ID_VMWARE; |
1261 |
k->device_id = SVGA_PCI_DEVICE_ID; |
1262 |
k->class_id = PCI_CLASS_DISPLAY_VGA; |
1263 |
k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; |
1264 |
k->subsystem_id = SVGA_PCI_DEVICE_ID; |
1265 |
dc->reset = vmsvga_reset; |
1266 |
dc->vmsd = &vmstate_vmware_vga; |
1267 |
dc->props = vga_vmware_properties; |
1268 |
} |
1269 |
|
1270 |
static const TypeInfo vmsvga_info = { |
1271 |
.name = "vmware-svga",
|
1272 |
.parent = TYPE_PCI_DEVICE, |
1273 |
.instance_size = sizeof(struct pci_vmsvga_state_s), |
1274 |
.class_init = vmsvga_class_init, |
1275 |
}; |
1276 |
|
1277 |
static void vmsvga_register_types(void) |
1278 |
{ |
1279 |
type_register_static(&vmsvga_info); |
1280 |
} |
1281 |
|
1282 |
type_init(vmsvga_register_types) |