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/*
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* QEMU model of Xilinx AXI-Ethernet.
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*
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* Copyright (c) 2011 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h" |
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#include "qemu/log.h" |
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#include "net/net.h" |
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#include "net/checksum.h" |
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#include "qapi/qmp/qerror.h" |
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#include "hw/stream.h" |
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#define DPHY(x)
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/* Advertisement control register. */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
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struct PHY {
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uint32_t regs[32];
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|
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int link;
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unsigned int (*read)(struct PHY *phy, unsigned int req); |
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void (*write)(struct PHY *phy, unsigned int req, |
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unsigned int data); |
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}; |
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|
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static unsigned int tdk_read(struct PHY *phy, unsigned int req) |
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{ |
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int regnum;
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unsigned r = 0; |
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regnum = req & 0x1f;
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switch (regnum) {
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case 1: |
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if (!phy->link) {
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break;
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} |
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14); |
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r |= (1 << 11) | (1 << 12); |
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r |= (1 << 5); /* Autoneg complete. */ |
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r |= (1 << 3); /* Autoneg able. */ |
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r |= (1 << 2); /* link. */ |
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r |= (1 << 1); /* link. */ |
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break;
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case 5: |
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/* Link partner ability.
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We are kind; always agree with whatever best mode
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the guest advertises. */
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r = 1 << 14; /* Success. */ |
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/* Copy advertised modes. */
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r |= phy->regs[4] & (15 << 5); |
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/* Autoneg support. */
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r |= 1;
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break;
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case 17: |
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/* Marvel PHY on many xilinx boards. */
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r = 0x8000; /* 1000Mb */ |
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break;
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case 18: |
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{ |
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/* Diagnostics reg. */
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int duplex = 0; |
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int speed_100 = 0; |
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if (!phy->link) {
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break;
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} |
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/* Are we advertising 100 half or 100 duplex ? */
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speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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/* Are we advertising 10 duplex or 100 duplex ? */
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duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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r = (speed_100 << 10) | (duplex << 11); |
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} |
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break;
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default:
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r = phy->regs[regnum]; |
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break;
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} |
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DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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} |
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static void |
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tdk_write(struct PHY *phy, unsigned int req, unsigned int data) |
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{ |
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int regnum;
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regnum = req & 0x1f;
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DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data; |
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break;
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} |
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} |
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static void |
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tdk_init(struct PHY *phy)
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{ |
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phy->regs[0] = 0x3100; |
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/* PHY Id. */
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phy->regs[2] = 0x0300; |
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phy->regs[3] = 0xe400; |
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/* Autonegotiation advertisement reg. */
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phy->regs[4] = 0x01E1; |
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phy->link = 1;
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phy->read = tdk_read; |
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phy->write = tdk_write; |
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} |
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struct MDIOBus {
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE, |
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SOF, |
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OPC, |
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ADDR, |
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REQ, |
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TURNAROUND, |
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DATA |
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} state; |
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unsigned int drive; |
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unsigned int cnt; |
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unsigned int addr; |
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unsigned int opc; |
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unsigned int req; |
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unsigned int data; |
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struct PHY *devs[32]; |
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}; |
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static void |
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mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
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{ |
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bus->devs[addr & 0x1f] = phy;
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void |
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mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
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{ |
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bus->devs[addr & 0x1f] = NULL; |
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} |
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#endif
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static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, |
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unsigned int reg) |
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{ |
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struct PHY *phy;
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uint16_t data; |
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phy = bus->devs[addr]; |
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if (phy && phy->read) {
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data = phy->read(phy, reg); |
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} else {
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data = 0xffff;
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} |
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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return data;
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} |
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static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, |
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unsigned int reg, uint16_t data) |
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{ |
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struct PHY *phy;
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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phy = bus->devs[addr]; |
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if (phy && phy->write) {
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phy->write(phy, reg, data); |
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} |
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} |
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#define DENET(x)
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#define R_RAF (0x000 / 4) |
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enum {
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RAF_MCAST_REJ = (1 << 1), |
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RAF_BCAST_REJ = (1 << 2), |
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RAF_EMCF_EN = (1 << 12), |
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RAF_NEWFUNC_EN = (1 << 11) |
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}; |
221 |
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#define R_IS (0x00C / 4) |
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enum {
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IS_HARD_ACCESS_COMPLETE = 1,
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IS_AUTONEG = (1 << 1), |
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IS_RX_COMPLETE = (1 << 2), |
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IS_RX_REJECT = (1 << 3), |
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IS_TX_COMPLETE = (1 << 5), |
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IS_RX_DCM_LOCK = (1 << 6), |
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IS_MGM_RDY = (1 << 7), |
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IS_PHY_RST_DONE = (1 << 8), |
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}; |
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#define R_IP (0x010 / 4) |
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#define R_IE (0x014 / 4) |
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#define R_UAWL (0x020 / 4) |
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#define R_UAWU (0x024 / 4) |
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#define R_PPST (0x030 / 4) |
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enum {
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PPST_LINKSTATUS = (1 << 0), |
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PPST_PHY_LINKSTATUS = (1 << 7), |
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}; |
243 |
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#define R_STATS_RX_BYTESL (0x200 / 4) |
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#define R_STATS_RX_BYTESH (0x204 / 4) |
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#define R_STATS_TX_BYTESL (0x208 / 4) |
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#define R_STATS_TX_BYTESH (0x20C / 4) |
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#define R_STATS_RXL (0x290 / 4) |
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#define R_STATS_RXH (0x294 / 4) |
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#define R_STATS_RX_BCASTL (0x2a0 / 4) |
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#define R_STATS_RX_BCASTH (0x2a4 / 4) |
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#define R_STATS_RX_MCASTL (0x2a8 / 4) |
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#define R_STATS_RX_MCASTH (0x2ac / 4) |
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#define R_RCW0 (0x400 / 4) |
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#define R_RCW1 (0x404 / 4) |
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enum {
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RCW1_VLAN = (1 << 27), |
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RCW1_RX = (1 << 28), |
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RCW1_FCS = (1 << 29), |
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RCW1_JUM = (1 << 30), |
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RCW1_RST = (1 << 31), |
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}; |
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#define R_TC (0x408 / 4) |
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enum {
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TC_VLAN = (1 << 27), |
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TC_TX = (1 << 28), |
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TC_FCS = (1 << 29), |
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TC_JUM = (1 << 30), |
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TC_RST = (1 << 31), |
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}; |
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#define R_EMMC (0x410 / 4) |
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enum {
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EMMC_LINKSPEED_10MB = (0 << 30), |
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EMMC_LINKSPEED_100MB = (1 << 30), |
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EMMC_LINKSPEED_1000MB = (2 << 30), |
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}; |
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#define R_PHYC (0x414 / 4) |
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|
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#define R_MC (0x500 / 4) |
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#define MC_EN (1 << 6) |
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|
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#define R_MCR (0x504 / 4) |
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#define R_MWD (0x508 / 4) |
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#define R_MRD (0x50c / 4) |
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#define R_MIS (0x600 / 4) |
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#define R_MIP (0x620 / 4) |
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#define R_MIE (0x640 / 4) |
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#define R_MIC (0x640 / 4) |
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|
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#define R_UAW0 (0x700 / 4) |
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#define R_UAW1 (0x704 / 4) |
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#define R_FMI (0x708 / 4) |
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#define R_AF0 (0x710 / 4) |
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#define R_AF1 (0x714 / 4) |
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#define R_MAX (0x34 / 4) |
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/* Indirect registers. */
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struct TEMAC {
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struct MDIOBus mdio_bus;
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struct PHY phy;
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void *parent;
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}; |
308 |
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struct XilinxAXIEnet {
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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qemu_irq irq; |
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StreamSlave *tx_dev; |
314 |
NICState *nic; |
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NICConf conf; |
316 |
|
317 |
|
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uint32_t c_rxmem; |
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uint32_t c_txmem; |
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uint32_t c_phyaddr; |
321 |
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struct TEMAC TEMAC;
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/* MII regs. */
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union {
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uint32_t regs[4];
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struct {
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328 |
uint32_t mc; |
329 |
uint32_t mcr; |
330 |
uint32_t mwd; |
331 |
uint32_t mrd; |
332 |
}; |
333 |
} mii; |
334 |
|
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struct {
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336 |
uint64_t rx_bytes; |
337 |
uint64_t tx_bytes; |
338 |
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uint64_t rx; |
340 |
uint64_t rx_bcast; |
341 |
uint64_t rx_mcast; |
342 |
} stats; |
343 |
|
344 |
/* Receive configuration words. */
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uint32_t rcw[2];
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/* Transmit config. */
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347 |
uint32_t tc; |
348 |
uint32_t emmc; |
349 |
uint32_t phyc; |
350 |
|
351 |
/* Unicast Address Word. */
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352 |
uint32_t uaw[2];
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353 |
/* Unicast address filter used with extended mcast. */
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354 |
uint32_t ext_uaw[2];
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uint32_t fmi; |
356 |
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357 |
uint32_t regs[R_MAX]; |
358 |
|
359 |
/* Multicast filter addrs. */
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360 |
uint32_t maddr[4][2]; |
361 |
/* 32K x 1 lookup filter. */
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362 |
uint32_t ext_mtable[1024];
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363 |
|
364 |
|
365 |
uint8_t *rxmem; |
366 |
}; |
367 |
|
368 |
static void axienet_rx_reset(struct XilinxAXIEnet *s) |
369 |
{ |
370 |
s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
|
371 |
} |
372 |
|
373 |
static void axienet_tx_reset(struct XilinxAXIEnet *s) |
374 |
{ |
375 |
s->tc = TC_JUM | TC_TX | TC_VLAN; |
376 |
} |
377 |
|
378 |
static inline int axienet_rx_resetting(struct XilinxAXIEnet *s) |
379 |
{ |
380 |
return s->rcw[1] & RCW1_RST; |
381 |
} |
382 |
|
383 |
static inline int axienet_rx_enabled(struct XilinxAXIEnet *s) |
384 |
{ |
385 |
return s->rcw[1] & RCW1_RX; |
386 |
} |
387 |
|
388 |
static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s) |
389 |
{ |
390 |
return !!(s->regs[R_RAF] & RAF_EMCF_EN);
|
391 |
} |
392 |
|
393 |
static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s) |
394 |
{ |
395 |
return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
|
396 |
} |
397 |
|
398 |
static void axienet_reset(struct XilinxAXIEnet *s) |
399 |
{ |
400 |
axienet_rx_reset(s); |
401 |
axienet_tx_reset(s); |
402 |
|
403 |
s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; |
404 |
s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; |
405 |
|
406 |
s->emmc = EMMC_LINKSPEED_100MB; |
407 |
} |
408 |
|
409 |
static void enet_update_irq(struct XilinxAXIEnet *s) |
410 |
{ |
411 |
s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; |
412 |
qemu_set_irq(s->irq, !!s->regs[R_IP]); |
413 |
} |
414 |
|
415 |
static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) |
416 |
{ |
417 |
struct XilinxAXIEnet *s = opaque;
|
418 |
uint32_t r = 0;
|
419 |
addr >>= 2;
|
420 |
|
421 |
switch (addr) {
|
422 |
case R_RCW0:
|
423 |
case R_RCW1:
|
424 |
r = s->rcw[addr & 1];
|
425 |
break;
|
426 |
|
427 |
case R_TC:
|
428 |
r = s->tc; |
429 |
break;
|
430 |
|
431 |
case R_EMMC:
|
432 |
r = s->emmc; |
433 |
break;
|
434 |
|
435 |
case R_PHYC:
|
436 |
r = s->phyc; |
437 |
break;
|
438 |
|
439 |
case R_MCR:
|
440 |
r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ |
441 |
break;
|
442 |
|
443 |
case R_STATS_RX_BYTESL:
|
444 |
case R_STATS_RX_BYTESH:
|
445 |
r = s->stats.rx_bytes >> (32 * (addr & 1)); |
446 |
break;
|
447 |
|
448 |
case R_STATS_TX_BYTESL:
|
449 |
case R_STATS_TX_BYTESH:
|
450 |
r = s->stats.tx_bytes >> (32 * (addr & 1)); |
451 |
break;
|
452 |
|
453 |
case R_STATS_RXL:
|
454 |
case R_STATS_RXH:
|
455 |
r = s->stats.rx >> (32 * (addr & 1)); |
456 |
break;
|
457 |
case R_STATS_RX_BCASTL:
|
458 |
case R_STATS_RX_BCASTH:
|
459 |
r = s->stats.rx_bcast >> (32 * (addr & 1)); |
460 |
break;
|
461 |
case R_STATS_RX_MCASTL:
|
462 |
case R_STATS_RX_MCASTH:
|
463 |
r = s->stats.rx_mcast >> (32 * (addr & 1)); |
464 |
break;
|
465 |
|
466 |
case R_MC:
|
467 |
case R_MWD:
|
468 |
case R_MRD:
|
469 |
r = s->mii.regs[addr & 3];
|
470 |
break;
|
471 |
|
472 |
case R_UAW0:
|
473 |
case R_UAW1:
|
474 |
r = s->uaw[addr & 1];
|
475 |
break;
|
476 |
|
477 |
case R_UAWU:
|
478 |
case R_UAWL:
|
479 |
r = s->ext_uaw[addr & 1];
|
480 |
break;
|
481 |
|
482 |
case R_FMI:
|
483 |
r = s->fmi; |
484 |
break;
|
485 |
|
486 |
case R_AF0:
|
487 |
case R_AF1:
|
488 |
r = s->maddr[s->fmi & 3][addr & 1]; |
489 |
break;
|
490 |
|
491 |
case 0x8000 ... 0x83ff: |
492 |
r = s->ext_mtable[addr - 0x8000];
|
493 |
break;
|
494 |
|
495 |
default:
|
496 |
if (addr < ARRAY_SIZE(s->regs)) {
|
497 |
r = s->regs[addr]; |
498 |
} |
499 |
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", |
500 |
__func__, addr * 4, r));
|
501 |
break;
|
502 |
} |
503 |
return r;
|
504 |
} |
505 |
|
506 |
static void enet_write(void *opaque, hwaddr addr, |
507 |
uint64_t value, unsigned size)
|
508 |
{ |
509 |
struct XilinxAXIEnet *s = opaque;
|
510 |
struct TEMAC *t = &s->TEMAC;
|
511 |
|
512 |
addr >>= 2;
|
513 |
switch (addr) {
|
514 |
case R_RCW0:
|
515 |
case R_RCW1:
|
516 |
s->rcw[addr & 1] = value;
|
517 |
if ((addr & 1) && value & RCW1_RST) { |
518 |
axienet_rx_reset(s); |
519 |
} else {
|
520 |
qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
521 |
} |
522 |
break;
|
523 |
|
524 |
case R_TC:
|
525 |
s->tc = value; |
526 |
if (value & TC_RST) {
|
527 |
axienet_tx_reset(s); |
528 |
} |
529 |
break;
|
530 |
|
531 |
case R_EMMC:
|
532 |
s->emmc = value; |
533 |
break;
|
534 |
|
535 |
case R_PHYC:
|
536 |
s->phyc = value; |
537 |
break;
|
538 |
|
539 |
case R_MC:
|
540 |
value &= ((1 < 7) - 1); |
541 |
|
542 |
/* Enable the MII. */
|
543 |
if (value & MC_EN) {
|
544 |
unsigned int miiclkdiv = value & ((1 << 6) - 1); |
545 |
if (!miiclkdiv) {
|
546 |
qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
|
547 |
} |
548 |
} |
549 |
s->mii.mc = value; |
550 |
break;
|
551 |
|
552 |
case R_MCR: {
|
553 |
unsigned int phyaddr = (value >> 24) & 0x1f; |
554 |
unsigned int regaddr = (value >> 16) & 0x1f; |
555 |
unsigned int op = (value >> 14) & 3; |
556 |
unsigned int initiate = (value >> 11) & 1; |
557 |
|
558 |
if (initiate) {
|
559 |
if (op == 1) { |
560 |
mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); |
561 |
} else if (op == 2) { |
562 |
s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); |
563 |
} else {
|
564 |
qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
|
565 |
} |
566 |
} |
567 |
s->mii.mcr = value; |
568 |
break;
|
569 |
} |
570 |
|
571 |
case R_MWD:
|
572 |
case R_MRD:
|
573 |
s->mii.regs[addr & 3] = value;
|
574 |
break;
|
575 |
|
576 |
|
577 |
case R_UAW0:
|
578 |
case R_UAW1:
|
579 |
s->uaw[addr & 1] = value;
|
580 |
break;
|
581 |
|
582 |
case R_UAWL:
|
583 |
case R_UAWU:
|
584 |
s->ext_uaw[addr & 1] = value;
|
585 |
break;
|
586 |
|
587 |
case R_FMI:
|
588 |
s->fmi = value; |
589 |
break;
|
590 |
|
591 |
case R_AF0:
|
592 |
case R_AF1:
|
593 |
s->maddr[s->fmi & 3][addr & 1] = value; |
594 |
break;
|
595 |
|
596 |
case R_IS:
|
597 |
s->regs[addr] &= ~value; |
598 |
break;
|
599 |
|
600 |
case 0x8000 ... 0x83ff: |
601 |
s->ext_mtable[addr - 0x8000] = value;
|
602 |
break;
|
603 |
|
604 |
default:
|
605 |
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", |
606 |
__func__, addr * 4, (unsigned)value)); |
607 |
if (addr < ARRAY_SIZE(s->regs)) {
|
608 |
s->regs[addr] = value; |
609 |
} |
610 |
break;
|
611 |
} |
612 |
enet_update_irq(s); |
613 |
} |
614 |
|
615 |
static const MemoryRegionOps enet_ops = { |
616 |
.read = enet_read, |
617 |
.write = enet_write, |
618 |
.endianness = DEVICE_LITTLE_ENDIAN, |
619 |
}; |
620 |
|
621 |
static int eth_can_rx(NetClientState *nc) |
622 |
{ |
623 |
struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
|
624 |
|
625 |
/* RX enabled? */
|
626 |
return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
|
627 |
} |
628 |
|
629 |
static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) |
630 |
{ |
631 |
int match = 1; |
632 |
|
633 |
if (memcmp(buf, &f0, 4)) { |
634 |
match = 0;
|
635 |
} |
636 |
|
637 |
if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { |
638 |
match = 0;
|
639 |
} |
640 |
|
641 |
return match;
|
642 |
} |
643 |
|
644 |
static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
645 |
{ |
646 |
struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
|
647 |
static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, |
648 |
0xff, 0xff, 0xff}; |
649 |
static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; |
650 |
uint32_t app[6] = {0}; |
651 |
int promisc = s->fmi & (1 << 31); |
652 |
int unicast, broadcast, multicast, ip_multicast = 0; |
653 |
uint32_t csum32; |
654 |
uint16_t csum16; |
655 |
int i;
|
656 |
|
657 |
DENET(qemu_log("%s: %zd bytes\n", __func__, size));
|
658 |
|
659 |
unicast = ~buf[0] & 0x1; |
660 |
broadcast = memcmp(buf, sa_bcast, 6) == 0; |
661 |
multicast = !unicast && !broadcast; |
662 |
if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { |
663 |
ip_multicast = 1;
|
664 |
} |
665 |
|
666 |
/* Jumbo or vlan sizes ? */
|
667 |
if (!(s->rcw[1] & RCW1_JUM)) { |
668 |
if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { |
669 |
return size;
|
670 |
} |
671 |
} |
672 |
|
673 |
/* Basic Address filters. If you want to use the extended filters
|
674 |
you'll generally have to place the ethernet mac into promiscuous mode
|
675 |
to avoid the basic filtering from dropping most frames. */
|
676 |
if (!promisc) {
|
677 |
if (unicast) {
|
678 |
if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { |
679 |
return size;
|
680 |
} |
681 |
} else {
|
682 |
if (broadcast) {
|
683 |
/* Broadcast. */
|
684 |
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
685 |
return size;
|
686 |
} |
687 |
} else {
|
688 |
int drop = 1; |
689 |
|
690 |
/* Multicast. */
|
691 |
if (s->regs[R_RAF] & RAF_MCAST_REJ) {
|
692 |
return size;
|
693 |
} |
694 |
|
695 |
for (i = 0; i < 4; i++) { |
696 |
if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { |
697 |
drop = 0;
|
698 |
break;
|
699 |
} |
700 |
} |
701 |
|
702 |
if (drop) {
|
703 |
return size;
|
704 |
} |
705 |
} |
706 |
} |
707 |
} |
708 |
|
709 |
/* Extended mcast filtering enabled? */
|
710 |
if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
|
711 |
if (unicast) {
|
712 |
if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { |
713 |
return size;
|
714 |
} |
715 |
} else {
|
716 |
if (broadcast) {
|
717 |
/* Broadcast. ??? */
|
718 |
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
719 |
return size;
|
720 |
} |
721 |
} else {
|
722 |
int idx, bit;
|
723 |
|
724 |
/* Multicast. */
|
725 |
if (!memcmp(buf, sa_ipmcast, 3)) { |
726 |
return size;
|
727 |
} |
728 |
|
729 |
idx = (buf[4] & 0x7f) << 8; |
730 |
idx |= buf[5];
|
731 |
|
732 |
bit = 1 << (idx & 0x1f); |
733 |
idx >>= 5;
|
734 |
|
735 |
if (!(s->ext_mtable[idx] & bit)) {
|
736 |
return size;
|
737 |
} |
738 |
} |
739 |
} |
740 |
} |
741 |
|
742 |
if (size < 12) { |
743 |
s->regs[R_IS] |= IS_RX_REJECT; |
744 |
enet_update_irq(s); |
745 |
return -1; |
746 |
} |
747 |
|
748 |
if (size > (s->c_rxmem - 4)) { |
749 |
size = s->c_rxmem - 4;
|
750 |
} |
751 |
|
752 |
memcpy(s->rxmem, buf, size); |
753 |
memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ |
754 |
|
755 |
if (s->rcw[1] & RCW1_FCS) { |
756 |
size += 4; /* fcs is inband. */ |
757 |
} |
758 |
|
759 |
app[0] = 5 << 28; |
760 |
csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); |
761 |
/* Fold it once. */
|
762 |
csum32 = (csum32 & 0xffff) + (csum32 >> 16); |
763 |
/* And twice to get rid of possible carries. */
|
764 |
csum16 = (csum32 & 0xffff) + (csum32 >> 16); |
765 |
app[3] = csum16;
|
766 |
app[4] = size & 0xffff; |
767 |
|
768 |
s->stats.rx_bytes += size; |
769 |
s->stats.rx++; |
770 |
if (multicast) {
|
771 |
s->stats.rx_mcast++; |
772 |
app[2] |= 1 | (ip_multicast << 1); |
773 |
} else if (broadcast) { |
774 |
s->stats.rx_bcast++; |
775 |
app[2] |= 1 << 3; |
776 |
} |
777 |
|
778 |
/* Good frame. */
|
779 |
app[2] |= 1 << 6; |
780 |
|
781 |
stream_push(s->tx_dev, (void *)s->rxmem, size, app);
|
782 |
|
783 |
s->regs[R_IS] |= IS_RX_COMPLETE; |
784 |
enet_update_irq(s); |
785 |
return size;
|
786 |
} |
787 |
|
788 |
static void eth_cleanup(NetClientState *nc) |
789 |
{ |
790 |
/* FIXME. */
|
791 |
struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
|
792 |
g_free(s->rxmem); |
793 |
g_free(s); |
794 |
} |
795 |
|
796 |
static void |
797 |
axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr) |
798 |
{ |
799 |
struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
|
800 |
|
801 |
/* TX enable ? */
|
802 |
if (!(s->tc & TC_TX)) {
|
803 |
return;
|
804 |
} |
805 |
|
806 |
/* Jumbo or vlan sizes ? */
|
807 |
if (!(s->tc & TC_JUM)) {
|
808 |
if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { |
809 |
return;
|
810 |
} |
811 |
} |
812 |
|
813 |
if (hdr[0] & 1) { |
814 |
unsigned int start_off = hdr[1] >> 16; |
815 |
unsigned int write_off = hdr[1] & 0xffff; |
816 |
uint32_t tmp_csum; |
817 |
uint16_t csum; |
818 |
|
819 |
tmp_csum = net_checksum_add(size - start_off, |
820 |
(uint8_t *)buf + start_off); |
821 |
/* Accumulate the seed. */
|
822 |
tmp_csum += hdr[2] & 0xffff; |
823 |
|
824 |
/* Fold the 32bit partial checksum. */
|
825 |
csum = net_checksum_finish(tmp_csum); |
826 |
|
827 |
/* Writeback. */
|
828 |
buf[write_off] = csum >> 8;
|
829 |
buf[write_off + 1] = csum & 0xff; |
830 |
} |
831 |
|
832 |
qemu_send_packet(qemu_get_queue(s->nic), buf, size); |
833 |
|
834 |
s->stats.tx_bytes += size; |
835 |
s->regs[R_IS] |= IS_TX_COMPLETE; |
836 |
enet_update_irq(s); |
837 |
} |
838 |
|
839 |
static NetClientInfo net_xilinx_enet_info = {
|
840 |
.type = NET_CLIENT_OPTIONS_KIND_NIC, |
841 |
.size = sizeof(NICState),
|
842 |
.can_receive = eth_can_rx, |
843 |
.receive = eth_rx, |
844 |
.cleanup = eth_cleanup, |
845 |
}; |
846 |
|
847 |
static int xilinx_enet_init(SysBusDevice *dev) |
848 |
{ |
849 |
struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
|
850 |
|
851 |
sysbus_init_irq(dev, &s->irq); |
852 |
|
853 |
memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000); |
854 |
sysbus_init_mmio(dev, &s->iomem); |
855 |
|
856 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
857 |
s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, |
858 |
object_get_typename(OBJECT(dev)), dev->qdev.id, s); |
859 |
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
860 |
|
861 |
tdk_init(&s->TEMAC.phy); |
862 |
mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); |
863 |
|
864 |
s->TEMAC.parent = s; |
865 |
|
866 |
s->rxmem = g_malloc(s->c_rxmem); |
867 |
axienet_reset(s); |
868 |
|
869 |
return 0; |
870 |
} |
871 |
|
872 |
static void xilinx_enet_initfn(Object *obj) |
873 |
{ |
874 |
struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
|
875 |
Error *errp = NULL;
|
876 |
|
877 |
object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
|
878 |
(Object **) &s->tx_dev, &errp); |
879 |
assert_no_error(errp); |
880 |
} |
881 |
|
882 |
static Property xilinx_enet_properties[] = {
|
883 |
DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7), |
884 |
DEFINE_PROP_UINT32("rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000), |
885 |
DEFINE_PROP_UINT32("txmem", struct XilinxAXIEnet, c_txmem, 0x1000), |
886 |
DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf),
|
887 |
DEFINE_PROP_END_OF_LIST(), |
888 |
}; |
889 |
|
890 |
static void xilinx_enet_class_init(ObjectClass *klass, void *data) |
891 |
{ |
892 |
DeviceClass *dc = DEVICE_CLASS(klass); |
893 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
894 |
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); |
895 |
|
896 |
k->init = xilinx_enet_init; |
897 |
dc->props = xilinx_enet_properties; |
898 |
ssc->push = axienet_stream_push; |
899 |
} |
900 |
|
901 |
static const TypeInfo xilinx_enet_info = { |
902 |
.name = "xlnx.axi-ethernet",
|
903 |
.parent = TYPE_SYS_BUS_DEVICE, |
904 |
.instance_size = sizeof(struct XilinxAXIEnet), |
905 |
.class_init = xilinx_enet_class_init, |
906 |
.instance_init = xilinx_enet_initfn, |
907 |
.interfaces = (InterfaceInfo[]) { |
908 |
{ TYPE_STREAM_SLAVE }, |
909 |
{ } |
910 |
} |
911 |
}; |
912 |
|
913 |
static void xilinx_enet_register_types(void) |
914 |
{ |
915 |
type_register_static(&xilinx_enet_info); |
916 |
} |
917 |
|
918 |
type_init(xilinx_enet_register_types) |