root / hw / sd / pl181.c @ 49ab747f
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/*
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* Arm PrimeCell PL181 MultiMedia Card Interface
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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|
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#include "sysemu/blockdev.h" |
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#include "hw/sysbus.h" |
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#include "hw/sd.h" |
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|
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//#define DEBUG_PL181 1
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|
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#ifdef DEBUG_PL181
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#define DPRINTF(fmt, ...) \
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do { printf("pl181: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) do {} while(0) |
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#endif
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|
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#define PL181_FIFO_LEN 16 |
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|
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typedef struct { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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SDState *card; |
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uint32_t clock; |
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uint32_t power; |
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uint32_t cmdarg; |
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uint32_t cmd; |
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uint32_t datatimer; |
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uint32_t datalength; |
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uint32_t respcmd; |
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uint32_t response[4];
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uint32_t datactrl; |
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uint32_t datacnt; |
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uint32_t status; |
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uint32_t mask[2];
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int32_t fifo_pos; |
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int32_t fifo_len; |
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/* The linux 2.6.21 driver is buggy, and misbehaves if new data arrives
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while it is reading the FIFO. We hack around this be defering
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subsequent transfers until after the driver polls the status word.
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http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=4446/1
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*/
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int32_t linux_hack; |
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uint32_t fifo[PL181_FIFO_LEN]; |
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qemu_irq irq[2];
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/* GPIO outputs for 'card is readonly' and 'card inserted' */
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qemu_irq cardstatus[2];
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} pl181_state; |
54 |
|
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static const VMStateDescription vmstate_pl181 = { |
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.name = "pl181",
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.version_id = 1,
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.minimum_version_id = 1,
|
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32(clock, pl181_state), |
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VMSTATE_UINT32(power, pl181_state), |
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VMSTATE_UINT32(cmdarg, pl181_state), |
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VMSTATE_UINT32(cmd, pl181_state), |
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VMSTATE_UINT32(datatimer, pl181_state), |
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VMSTATE_UINT32(datalength, pl181_state), |
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VMSTATE_UINT32(respcmd, pl181_state), |
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VMSTATE_UINT32_ARRAY(response, pl181_state, 4),
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VMSTATE_UINT32(datactrl, pl181_state), |
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VMSTATE_UINT32(datacnt, pl181_state), |
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VMSTATE_UINT32(status, pl181_state), |
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VMSTATE_UINT32_ARRAY(mask, pl181_state, 2),
|
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VMSTATE_INT32(fifo_pos, pl181_state), |
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VMSTATE_INT32(fifo_len, pl181_state), |
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VMSTATE_INT32(linux_hack, pl181_state), |
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VMSTATE_UINT32_ARRAY(fifo, pl181_state, PL181_FIFO_LEN), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define PL181_CMD_INDEX 0x3f |
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#define PL181_CMD_RESPONSE (1 << 6) |
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#define PL181_CMD_LONGRESP (1 << 7) |
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#define PL181_CMD_INTERRUPT (1 << 8) |
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#define PL181_CMD_PENDING (1 << 9) |
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#define PL181_CMD_ENABLE (1 << 10) |
86 |
|
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#define PL181_DATA_ENABLE (1 << 0) |
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#define PL181_DATA_DIRECTION (1 << 1) |
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#define PL181_DATA_MODE (1 << 2) |
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#define PL181_DATA_DMAENABLE (1 << 3) |
91 |
|
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#define PL181_STATUS_CMDCRCFAIL (1 << 0) |
93 |
#define PL181_STATUS_DATACRCFAIL (1 << 1) |
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#define PL181_STATUS_CMDTIMEOUT (1 << 2) |
95 |
#define PL181_STATUS_DATATIMEOUT (1 << 3) |
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#define PL181_STATUS_TXUNDERRUN (1 << 4) |
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#define PL181_STATUS_RXOVERRUN (1 << 5) |
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#define PL181_STATUS_CMDRESPEND (1 << 6) |
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#define PL181_STATUS_CMDSENT (1 << 7) |
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#define PL181_STATUS_DATAEND (1 << 8) |
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#define PL181_STATUS_DATABLOCKEND (1 << 10) |
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#define PL181_STATUS_CMDACTIVE (1 << 11) |
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#define PL181_STATUS_TXACTIVE (1 << 12) |
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#define PL181_STATUS_RXACTIVE (1 << 13) |
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#define PL181_STATUS_TXFIFOHALFEMPTY (1 << 14) |
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#define PL181_STATUS_RXFIFOHALFFULL (1 << 15) |
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#define PL181_STATUS_TXFIFOFULL (1 << 16) |
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#define PL181_STATUS_RXFIFOFULL (1 << 17) |
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#define PL181_STATUS_TXFIFOEMPTY (1 << 18) |
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#define PL181_STATUS_RXFIFOEMPTY (1 << 19) |
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#define PL181_STATUS_TXDATAAVLBL (1 << 20) |
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#define PL181_STATUS_RXDATAAVLBL (1 << 21) |
113 |
|
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#define PL181_STATUS_TX_FIFO (PL181_STATUS_TXACTIVE \
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|PL181_STATUS_TXFIFOHALFEMPTY \ |
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|PL181_STATUS_TXFIFOFULL \ |
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|PL181_STATUS_TXFIFOEMPTY \ |
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|PL181_STATUS_TXDATAAVLBL) |
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#define PL181_STATUS_RX_FIFO (PL181_STATUS_RXACTIVE \
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|PL181_STATUS_RXFIFOHALFFULL \ |
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|PL181_STATUS_RXFIFOFULL \ |
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|PL181_STATUS_RXFIFOEMPTY \ |
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|PL181_STATUS_RXDATAAVLBL) |
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|
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static const unsigned char pl181_id[] = |
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{ 0x81, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
127 |
|
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static void pl181_update(pl181_state *s) |
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{ |
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int i;
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for (i = 0; i < 2; i++) { |
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qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0);
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} |
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} |
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|
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static void pl181_fifo_push(pl181_state *s, uint32_t value) |
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{ |
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int n;
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|
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if (s->fifo_len == PL181_FIFO_LEN) {
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fprintf(stderr, "pl181: FIFO overflow\n");
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return;
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} |
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n = (s->fifo_pos + s->fifo_len) & (PL181_FIFO_LEN - 1);
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s->fifo_len++; |
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s->fifo[n] = value; |
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DPRINTF("FIFO push %08x\n", (int)value); |
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} |
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|
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static uint32_t pl181_fifo_pop(pl181_state *s)
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{ |
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uint32_t value; |
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|
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if (s->fifo_len == 0) { |
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fprintf(stderr, "pl181: FIFO underflow\n");
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return 0; |
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} |
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value = s->fifo[s->fifo_pos]; |
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s->fifo_len--; |
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s->fifo_pos = (s->fifo_pos + 1) & (PL181_FIFO_LEN - 1); |
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DPRINTF("FIFO pop %08x\n", (int)value); |
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return value;
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} |
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|
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static void pl181_send_command(pl181_state *s) |
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{ |
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SDRequest request; |
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uint8_t response[16];
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int rlen;
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|
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request.cmd = s->cmd & PL181_CMD_INDEX; |
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request.arg = s->cmdarg; |
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DPRINTF("Command %d %08x\n", request.cmd, request.arg);
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rlen = sd_do_command(s->card, &request, response); |
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if (rlen < 0) |
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goto error;
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if (s->cmd & PL181_CMD_RESPONSE) {
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#define RWORD(n) ((response[n] << 24) | (response[n + 1] << 16) \ |
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| (response[n + 2] << 8) | response[n + 3]) |
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if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP))) |
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goto error;
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if (rlen != 4 && rlen != 16) |
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goto error;
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s->response[0] = RWORD(0); |
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if (rlen == 4) { |
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s->response[1] = s->response[2] = s->response[3] = 0; |
187 |
} else {
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s->response[1] = RWORD(4); |
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s->response[2] = RWORD(8); |
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s->response[3] = RWORD(12) & ~1; |
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} |
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DPRINTF("Response received\n");
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s->status |= PL181_STATUS_CMDRESPEND; |
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#undef RWORD
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} else {
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DPRINTF("Command sent\n");
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s->status |= PL181_STATUS_CMDSENT; |
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} |
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return;
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error:
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DPRINTF("Timeout\n");
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s->status |= PL181_STATUS_CMDTIMEOUT; |
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} |
205 |
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/* Transfer data between the card and the FIFO. This is complicated by
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the FIFO holding 32-bit words and the card taking data in single byte
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chunks. FIFO bytes are transferred in little-endian order. */
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static void pl181_fifo_run(pl181_state *s) |
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{ |
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uint32_t bits; |
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uint32_t value = 0;
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int n;
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int is_read;
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is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0;
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if (s->datacnt != 0 && (!is_read || sd_data_ready(s->card)) |
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&& !s->linux_hack) { |
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if (is_read) {
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n = 0;
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while (s->datacnt && s->fifo_len < PL181_FIFO_LEN) {
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value |= (uint32_t)sd_read_data(s->card) << (n * 8);
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s->datacnt--; |
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n++; |
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if (n == 4) { |
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pl181_fifo_push(s, value); |
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n = 0;
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value = 0;
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} |
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} |
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if (n != 0) { |
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pl181_fifo_push(s, value); |
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} |
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} else { /* write */ |
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n = 0;
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while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { |
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if (n == 0) { |
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value = pl181_fifo_pop(s); |
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n = 4;
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} |
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n--; |
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s->datacnt--; |
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sd_write_data(s->card, value & 0xff);
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value >>= 8;
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} |
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} |
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} |
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s->status &= ~(PL181_STATUS_RX_FIFO | PL181_STATUS_TX_FIFO); |
250 |
if (s->datacnt == 0) { |
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s->status |= PL181_STATUS_DATAEND; |
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/* HACK: */
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s->status |= PL181_STATUS_DATABLOCKEND; |
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DPRINTF("Transfer Complete\n");
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} |
256 |
if (s->datacnt == 0 && s->fifo_len == 0) { |
257 |
s->datactrl &= ~PL181_DATA_ENABLE; |
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DPRINTF("Data engine idle\n");
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} else {
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/* Update FIFO bits. */
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bits = PL181_STATUS_TXACTIVE | PL181_STATUS_RXACTIVE; |
262 |
if (s->fifo_len == 0) { |
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bits |= PL181_STATUS_TXFIFOEMPTY; |
264 |
bits |= PL181_STATUS_RXFIFOEMPTY; |
265 |
} else {
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bits |= PL181_STATUS_TXDATAAVLBL; |
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bits |= PL181_STATUS_RXDATAAVLBL; |
268 |
} |
269 |
if (s->fifo_len == 16) { |
270 |
bits |= PL181_STATUS_TXFIFOFULL; |
271 |
bits |= PL181_STATUS_RXFIFOFULL; |
272 |
} |
273 |
if (s->fifo_len <= 8) { |
274 |
bits |= PL181_STATUS_TXFIFOHALFEMPTY; |
275 |
} |
276 |
if (s->fifo_len >= 8) { |
277 |
bits |= PL181_STATUS_RXFIFOHALFFULL; |
278 |
} |
279 |
if (s->datactrl & PL181_DATA_DIRECTION) {
|
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bits &= PL181_STATUS_RX_FIFO; |
281 |
} else {
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bits &= PL181_STATUS_TX_FIFO; |
283 |
} |
284 |
s->status |= bits; |
285 |
} |
286 |
} |
287 |
|
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static uint64_t pl181_read(void *opaque, hwaddr offset, |
289 |
unsigned size)
|
290 |
{ |
291 |
pl181_state *s = (pl181_state *)opaque; |
292 |
uint32_t tmp; |
293 |
|
294 |
if (offset >= 0xfe0 && offset < 0x1000) { |
295 |
return pl181_id[(offset - 0xfe0) >> 2]; |
296 |
} |
297 |
switch (offset) {
|
298 |
case 0x00: /* Power */ |
299 |
return s->power;
|
300 |
case 0x04: /* Clock */ |
301 |
return s->clock;
|
302 |
case 0x08: /* Argument */ |
303 |
return s->cmdarg;
|
304 |
case 0x0c: /* Command */ |
305 |
return s->cmd;
|
306 |
case 0x10: /* RespCmd */ |
307 |
return s->respcmd;
|
308 |
case 0x14: /* Response0 */ |
309 |
return s->response[0]; |
310 |
case 0x18: /* Response1 */ |
311 |
return s->response[1]; |
312 |
case 0x1c: /* Response2 */ |
313 |
return s->response[2]; |
314 |
case 0x20: /* Response3 */ |
315 |
return s->response[3]; |
316 |
case 0x24: /* DataTimer */ |
317 |
return s->datatimer;
|
318 |
case 0x28: /* DataLength */ |
319 |
return s->datalength;
|
320 |
case 0x2c: /* DataCtrl */ |
321 |
return s->datactrl;
|
322 |
case 0x30: /* DataCnt */ |
323 |
return s->datacnt;
|
324 |
case 0x34: /* Status */ |
325 |
tmp = s->status; |
326 |
if (s->linux_hack) {
|
327 |
s->linux_hack = 0;
|
328 |
pl181_fifo_run(s); |
329 |
pl181_update(s); |
330 |
} |
331 |
return tmp;
|
332 |
case 0x3c: /* Mask0 */ |
333 |
return s->mask[0]; |
334 |
case 0x40: /* Mask1 */ |
335 |
return s->mask[1]; |
336 |
case 0x48: /* FifoCnt */ |
337 |
/* The documentation is somewhat vague about exactly what FifoCnt
|
338 |
does. On real hardware it appears to be when decrememnted
|
339 |
when a word is transferred between the FIFO and the serial
|
340 |
data engine. DataCnt is decremented after each byte is
|
341 |
transferred between the serial engine and the card.
|
342 |
We don't emulate this level of detail, so both can be the same. */
|
343 |
tmp = (s->datacnt + 3) >> 2; |
344 |
if (s->linux_hack) {
|
345 |
s->linux_hack = 0;
|
346 |
pl181_fifo_run(s); |
347 |
pl181_update(s); |
348 |
} |
349 |
return tmp;
|
350 |
case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ |
351 |
case 0x90: case 0x94: case 0x98: case 0x9c: |
352 |
case 0xa0: case 0xa4: case 0xa8: case 0xac: |
353 |
case 0xb0: case 0xb4: case 0xb8: case 0xbc: |
354 |
if (s->fifo_len == 0) { |
355 |
qemu_log_mask(LOG_GUEST_ERROR, "pl181: Unexpected FIFO read\n");
|
356 |
return 0; |
357 |
} else {
|
358 |
uint32_t value; |
359 |
value = pl181_fifo_pop(s); |
360 |
s->linux_hack = 1;
|
361 |
pl181_fifo_run(s); |
362 |
pl181_update(s); |
363 |
return value;
|
364 |
} |
365 |
default:
|
366 |
qemu_log_mask(LOG_GUEST_ERROR, |
367 |
"pl181_read: Bad offset %x\n", (int)offset); |
368 |
return 0; |
369 |
} |
370 |
} |
371 |
|
372 |
static void pl181_write(void *opaque, hwaddr offset, |
373 |
uint64_t value, unsigned size)
|
374 |
{ |
375 |
pl181_state *s = (pl181_state *)opaque; |
376 |
|
377 |
switch (offset) {
|
378 |
case 0x00: /* Power */ |
379 |
s->power = value & 0xff;
|
380 |
break;
|
381 |
case 0x04: /* Clock */ |
382 |
s->clock = value & 0xff;
|
383 |
break;
|
384 |
case 0x08: /* Argument */ |
385 |
s->cmdarg = value; |
386 |
break;
|
387 |
case 0x0c: /* Command */ |
388 |
s->cmd = value; |
389 |
if (s->cmd & PL181_CMD_ENABLE) {
|
390 |
if (s->cmd & PL181_CMD_INTERRUPT) {
|
391 |
qemu_log_mask(LOG_UNIMP, |
392 |
"pl181: Interrupt mode not implemented\n");
|
393 |
} if (s->cmd & PL181_CMD_PENDING) {
|
394 |
qemu_log_mask(LOG_UNIMP, |
395 |
"pl181: Pending commands not implemented\n");
|
396 |
} else {
|
397 |
pl181_send_command(s); |
398 |
pl181_fifo_run(s); |
399 |
} |
400 |
/* The command has completed one way or the other. */
|
401 |
s->cmd &= ~PL181_CMD_ENABLE; |
402 |
} |
403 |
break;
|
404 |
case 0x24: /* DataTimer */ |
405 |
s->datatimer = value; |
406 |
break;
|
407 |
case 0x28: /* DataLength */ |
408 |
s->datalength = value & 0xffff;
|
409 |
break;
|
410 |
case 0x2c: /* DataCtrl */ |
411 |
s->datactrl = value & 0xff;
|
412 |
if (value & PL181_DATA_ENABLE) {
|
413 |
s->datacnt = s->datalength; |
414 |
pl181_fifo_run(s); |
415 |
} |
416 |
break;
|
417 |
case 0x38: /* Clear */ |
418 |
s->status &= ~(value & 0x7ff);
|
419 |
break;
|
420 |
case 0x3c: /* Mask0 */ |
421 |
s->mask[0] = value;
|
422 |
break;
|
423 |
case 0x40: /* Mask1 */ |
424 |
s->mask[1] = value;
|
425 |
break;
|
426 |
case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ |
427 |
case 0x90: case 0x94: case 0x98: case 0x9c: |
428 |
case 0xa0: case 0xa4: case 0xa8: case 0xac: |
429 |
case 0xb0: case 0xb4: case 0xb8: case 0xbc: |
430 |
if (s->datacnt == 0) { |
431 |
qemu_log_mask(LOG_GUEST_ERROR, "pl181: Unexpected FIFO write\n");
|
432 |
} else {
|
433 |
pl181_fifo_push(s, value); |
434 |
pl181_fifo_run(s); |
435 |
} |
436 |
break;
|
437 |
default:
|
438 |
qemu_log_mask(LOG_GUEST_ERROR, |
439 |
"pl181_write: Bad offset %x\n", (int)offset); |
440 |
} |
441 |
pl181_update(s); |
442 |
} |
443 |
|
444 |
static const MemoryRegionOps pl181_ops = { |
445 |
.read = pl181_read, |
446 |
.write = pl181_write, |
447 |
.endianness = DEVICE_NATIVE_ENDIAN, |
448 |
}; |
449 |
|
450 |
static void pl181_reset(DeviceState *d) |
451 |
{ |
452 |
pl181_state *s = DO_UPCAST(pl181_state, busdev.qdev, d); |
453 |
|
454 |
s->power = 0;
|
455 |
s->cmdarg = 0;
|
456 |
s->cmd = 0;
|
457 |
s->datatimer = 0;
|
458 |
s->datalength = 0;
|
459 |
s->respcmd = 0;
|
460 |
s->response[0] = 0; |
461 |
s->response[1] = 0; |
462 |
s->response[2] = 0; |
463 |
s->response[3] = 0; |
464 |
s->datatimer = 0;
|
465 |
s->datalength = 0;
|
466 |
s->datactrl = 0;
|
467 |
s->datacnt = 0;
|
468 |
s->status = 0;
|
469 |
s->linux_hack = 0;
|
470 |
s->mask[0] = 0; |
471 |
s->mask[1] = 0; |
472 |
|
473 |
/* We can assume our GPIO outputs have been wired up now */
|
474 |
sd_set_cb(s->card, s->cardstatus[0], s->cardstatus[1]); |
475 |
} |
476 |
|
477 |
static int pl181_init(SysBusDevice *dev) |
478 |
{ |
479 |
pl181_state *s = FROM_SYSBUS(pl181_state, dev); |
480 |
DriveInfo *dinfo; |
481 |
|
482 |
memory_region_init_io(&s->iomem, &pl181_ops, s, "pl181", 0x1000); |
483 |
sysbus_init_mmio(dev, &s->iomem); |
484 |
sysbus_init_irq(dev, &s->irq[0]);
|
485 |
sysbus_init_irq(dev, &s->irq[1]);
|
486 |
qdev_init_gpio_out(&s->busdev.qdev, s->cardstatus, 2);
|
487 |
dinfo = drive_get_next(IF_SD); |
488 |
s->card = sd_init(dinfo ? dinfo->bdrv : NULL, 0); |
489 |
return 0; |
490 |
} |
491 |
|
492 |
static void pl181_class_init(ObjectClass *klass, void *data) |
493 |
{ |
494 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
495 |
DeviceClass *k = DEVICE_CLASS(klass); |
496 |
|
497 |
sdc->init = pl181_init; |
498 |
k->vmsd = &vmstate_pl181; |
499 |
k->reset = pl181_reset; |
500 |
k->no_user = 1;
|
501 |
} |
502 |
|
503 |
static const TypeInfo pl181_info = { |
504 |
.name = "pl181",
|
505 |
.parent = TYPE_SYS_BUS_DEVICE, |
506 |
.instance_size = sizeof(pl181_state),
|
507 |
.class_init = pl181_class_init, |
508 |
}; |
509 |
|
510 |
static void pl181_register_types(void) |
511 |
{ |
512 |
type_register_static(&pl181_info); |
513 |
} |
514 |
|
515 |
type_init(pl181_register_types) |