root / hw / timer / m48t59.c @ 49ab747f
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/*
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/timer/m48t59.h" |
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#include "qemu/timer.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/sysbus.h" |
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#include "hw/isa/isa.h" |
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#include "exec/address-spaces.h" |
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define NVRAM_PRINTF(fmt, ...) do { } while (0) |
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#endif
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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/*
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* Chipset docs:
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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*/
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struct M48t59State {
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/* Hardware parameters */
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qemu_irq IRQ; |
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MemoryRegion iomem; |
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uint32_t io_base; |
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uint32_t size; |
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/* RTC management */
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time_t time_offset; |
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time_t stop_time; |
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/* Alarm & watchdog */
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struct tm alarm;
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struct QEMUTimer *alrm_timer;
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struct QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint8_t *buffer; |
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/* Model parameters */
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uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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/* NVRAM storage */
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uint16_t addr; |
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uint8_t lock; |
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}; |
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typedef struct M48t59ISAState { |
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ISADevice busdev; |
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M48t59State state; |
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MemoryRegion io; |
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} M48t59ISAState; |
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typedef struct M48t59SysBusState { |
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SysBusDevice busdev; |
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M48t59State state; |
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MemoryRegion io; |
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} M48t59SysBusState; |
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/* Fake timer functions */
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/* Alarm management */
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static void alarm_cb (void *opaque) |
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{ |
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struct tm tm;
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uint64_t next_time; |
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M48t59State *NVRAM = opaque; |
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset); |
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tm.tm_mon++; |
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if (tm.tm_mon == 13) { |
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tm.tm_mon = 1;
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tm.tm_year++; |
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} |
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next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a day */
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next_time = 24 * 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once an hour */
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next_time = 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a minute */
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next_time = 60;
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} else {
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/* Repeat once a second */
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next_time = 1;
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} |
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qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + |
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next_time * 1000);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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static void set_alarm(M48t59State *NVRAM) |
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{ |
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int diff;
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if (NVRAM->alrm_timer != NULL) { |
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qemu_del_timer(NVRAM->alrm_timer); |
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
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if (diff > 0) |
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qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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} |
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} |
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/* RTC management helpers */
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static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
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{ |
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qemu_get_timedate(tm, NVRAM->time_offset); |
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} |
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static void set_time(M48t59State *NVRAM, struct tm *tm) |
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{ |
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NVRAM->time_offset = qemu_timedate_diff(tm); |
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set_alarm(NVRAM); |
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} |
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/* Watchdog management */
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static void watchdog_cb (void *opaque) |
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{ |
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M48t59State *NVRAM = opaque; |
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NVRAM->buffer[0x1FF0] |= 0x80; |
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if (NVRAM->buffer[0x1FF7] & 0x80) { |
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NVRAM->buffer[0x1FF7] = 0x00; |
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NVRAM->buffer[0x1FFC] &= ~0x40; |
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request(); |
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} else {
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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} |
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static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
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{ |
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80; |
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if (NVRAM->wd_timer != NULL) { |
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qemu_del_timer(NVRAM->wd_timer); |
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if (value != 0) { |
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
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qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
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((interval * 1000) >> 4)); |
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} |
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} |
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} |
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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M48t59State *NVRAM = opaque; |
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struct tm tm;
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int tmp;
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if (addr > 0x1FF8 && addr < 0x2000) |
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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/* check for NVRAM access */
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if ((NVRAM->model == 2 && addr < 0x7f8) || |
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(NVRAM->model == 8 && addr < 0x1ff8) || |
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(NVRAM->model == 59 && addr < 0x1ff0)) { |
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goto do_write;
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} |
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/* TOD access */
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switch (addr) {
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case 0x1FF0: |
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/* flags register : read-only */
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break;
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case 0x1FF1: |
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/* unused */
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break;
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case 0x1FF2: |
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/* alarm seconds */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_sec = tmp; |
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF3: |
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/* alarm minutes */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_min = tmp; |
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF4: |
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/* alarm hours */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
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NVRAM->alarm.tm_hour = tmp; |
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NVRAM->buffer[0x1FF4] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF5: |
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/* alarm date */
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tmp = from_bcd(val & 0x3F);
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if (tmp != 0) { |
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NVRAM->alarm.tm_mday = tmp; |
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NVRAM->buffer[0x1FF5] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF6: |
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/* interrupts */
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NVRAM->buffer[0x1FF6] = val;
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break;
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case 0x1FF7: |
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/* watchdog */
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val); |
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break;
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case 0x1FF8: |
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case 0x07F8: |
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/* control */
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
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break;
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case 0x1FF9: |
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case 0x07F9: |
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/* seconds (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
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tm.tm_sec = tmp; |
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set_time(NVRAM, &tm); |
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} |
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if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
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if (val & 0x80) { |
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NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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} |
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} |
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NVRAM->buffer[addr] = val & 0x80;
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break;
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case 0x1FFA: |
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case 0x07FA: |
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/* minutes (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
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tm.tm_min = tmp; |
292 |
set_time(NVRAM, &tm); |
293 |
} |
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break;
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case 0x1FFB: |
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case 0x07FB: |
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/* hours (BCD) */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
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get_time(NVRAM, &tm); |
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tm.tm_hour = tmp; |
302 |
set_time(NVRAM, &tm); |
303 |
} |
304 |
break;
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case 0x1FFC: |
306 |
case 0x07FC: |
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/* day of the week / century */
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tmp = from_bcd(val & 0x07);
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get_time(NVRAM, &tm); |
310 |
tm.tm_wday = tmp; |
311 |
set_time(NVRAM, &tm); |
312 |
NVRAM->buffer[addr] = val & 0x40;
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break;
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case 0x1FFD: |
315 |
case 0x07FD: |
316 |
/* date (BCD) */
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317 |
tmp = from_bcd(val & 0x3F);
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318 |
if (tmp != 0) { |
319 |
get_time(NVRAM, &tm); |
320 |
tm.tm_mday = tmp; |
321 |
set_time(NVRAM, &tm); |
322 |
} |
323 |
break;
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324 |
case 0x1FFE: |
325 |
case 0x07FE: |
326 |
/* month */
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327 |
tmp = from_bcd(val & 0x1F);
|
328 |
if (tmp >= 1 && tmp <= 12) { |
329 |
get_time(NVRAM, &tm); |
330 |
tm.tm_mon = tmp - 1;
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331 |
set_time(NVRAM, &tm); |
332 |
} |
333 |
break;
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334 |
case 0x1FFF: |
335 |
case 0x07FF: |
336 |
/* year */
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337 |
tmp = from_bcd(val); |
338 |
if (tmp >= 0 && tmp <= 99) { |
339 |
get_time(NVRAM, &tm); |
340 |
if (NVRAM->model == 8) { |
341 |
tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
342 |
} else {
|
343 |
tm.tm_year = from_bcd(val); |
344 |
} |
345 |
set_time(NVRAM, &tm); |
346 |
} |
347 |
break;
|
348 |
default:
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349 |
/* Check lock registers state */
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350 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
351 |
break;
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352 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
353 |
break;
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354 |
do_write:
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355 |
if (addr < NVRAM->size) {
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356 |
NVRAM->buffer[addr] = val & 0xFF;
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357 |
} |
358 |
break;
|
359 |
} |
360 |
} |
361 |
|
362 |
uint32_t m48t59_read (void *opaque, uint32_t addr)
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363 |
{ |
364 |
M48t59State *NVRAM = opaque; |
365 |
struct tm tm;
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366 |
uint32_t retval = 0xFF;
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367 |
|
368 |
/* check for NVRAM access */
|
369 |
if ((NVRAM->model == 2 && addr < 0x078f) || |
370 |
(NVRAM->model == 8 && addr < 0x1ff8) || |
371 |
(NVRAM->model == 59 && addr < 0x1ff0)) { |
372 |
goto do_read;
|
373 |
} |
374 |
|
375 |
/* TOD access */
|
376 |
switch (addr) {
|
377 |
case 0x1FF0: |
378 |
/* flags register */
|
379 |
goto do_read;
|
380 |
case 0x1FF1: |
381 |
/* unused */
|
382 |
retval = 0;
|
383 |
break;
|
384 |
case 0x1FF2: |
385 |
/* alarm seconds */
|
386 |
goto do_read;
|
387 |
case 0x1FF3: |
388 |
/* alarm minutes */
|
389 |
goto do_read;
|
390 |
case 0x1FF4: |
391 |
/* alarm hours */
|
392 |
goto do_read;
|
393 |
case 0x1FF5: |
394 |
/* alarm date */
|
395 |
goto do_read;
|
396 |
case 0x1FF6: |
397 |
/* interrupts */
|
398 |
goto do_read;
|
399 |
case 0x1FF7: |
400 |
/* A read resets the watchdog */
|
401 |
set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
402 |
goto do_read;
|
403 |
case 0x1FF8: |
404 |
case 0x07F8: |
405 |
/* control */
|
406 |
goto do_read;
|
407 |
case 0x1FF9: |
408 |
case 0x07F9: |
409 |
/* seconds (BCD) */
|
410 |
get_time(NVRAM, &tm); |
411 |
retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
|
412 |
break;
|
413 |
case 0x1FFA: |
414 |
case 0x07FA: |
415 |
/* minutes (BCD) */
|
416 |
get_time(NVRAM, &tm); |
417 |
retval = to_bcd(tm.tm_min); |
418 |
break;
|
419 |
case 0x1FFB: |
420 |
case 0x07FB: |
421 |
/* hours (BCD) */
|
422 |
get_time(NVRAM, &tm); |
423 |
retval = to_bcd(tm.tm_hour); |
424 |
break;
|
425 |
case 0x1FFC: |
426 |
case 0x07FC: |
427 |
/* day of the week / century */
|
428 |
get_time(NVRAM, &tm); |
429 |
retval = NVRAM->buffer[addr] | tm.tm_wday; |
430 |
break;
|
431 |
case 0x1FFD: |
432 |
case 0x07FD: |
433 |
/* date */
|
434 |
get_time(NVRAM, &tm); |
435 |
retval = to_bcd(tm.tm_mday); |
436 |
break;
|
437 |
case 0x1FFE: |
438 |
case 0x07FE: |
439 |
/* month */
|
440 |
get_time(NVRAM, &tm); |
441 |
retval = to_bcd(tm.tm_mon + 1);
|
442 |
break;
|
443 |
case 0x1FFF: |
444 |
case 0x07FF: |
445 |
/* year */
|
446 |
get_time(NVRAM, &tm); |
447 |
if (NVRAM->model == 8) { |
448 |
retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
449 |
} else {
|
450 |
retval = to_bcd(tm.tm_year); |
451 |
} |
452 |
break;
|
453 |
default:
|
454 |
/* Check lock registers state */
|
455 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
456 |
break;
|
457 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
458 |
break;
|
459 |
do_read:
|
460 |
if (addr < NVRAM->size) {
|
461 |
retval = NVRAM->buffer[addr]; |
462 |
} |
463 |
break;
|
464 |
} |
465 |
if (addr > 0x1FF9 && addr < 0x2000) |
466 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
467 |
|
468 |
return retval;
|
469 |
} |
470 |
|
471 |
void m48t59_toggle_lock (void *opaque, int lock) |
472 |
{ |
473 |
M48t59State *NVRAM = opaque; |
474 |
|
475 |
NVRAM->lock ^= 1 << lock;
|
476 |
} |
477 |
|
478 |
/* IO access to NVRAM */
|
479 |
static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, |
480 |
unsigned size)
|
481 |
{ |
482 |
M48t59State *NVRAM = opaque; |
483 |
|
484 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
485 |
switch (addr) {
|
486 |
case 0: |
487 |
NVRAM->addr &= ~0x00FF;
|
488 |
NVRAM->addr |= val; |
489 |
break;
|
490 |
case 1: |
491 |
NVRAM->addr &= ~0xFF00;
|
492 |
NVRAM->addr |= val << 8;
|
493 |
break;
|
494 |
case 3: |
495 |
m48t59_write(NVRAM, NVRAM->addr, val); |
496 |
NVRAM->addr = 0x0000;
|
497 |
break;
|
498 |
default:
|
499 |
break;
|
500 |
} |
501 |
} |
502 |
|
503 |
static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) |
504 |
{ |
505 |
M48t59State *NVRAM = opaque; |
506 |
uint32_t retval; |
507 |
|
508 |
switch (addr) {
|
509 |
case 3: |
510 |
retval = m48t59_read(NVRAM, NVRAM->addr); |
511 |
break;
|
512 |
default:
|
513 |
retval = -1;
|
514 |
break;
|
515 |
} |
516 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
517 |
|
518 |
return retval;
|
519 |
} |
520 |
|
521 |
static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) |
522 |
{ |
523 |
M48t59State *NVRAM = opaque; |
524 |
|
525 |
m48t59_write(NVRAM, addr, value & 0xff);
|
526 |
} |
527 |
|
528 |
static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) |
529 |
{ |
530 |
M48t59State *NVRAM = opaque; |
531 |
|
532 |
m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
533 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
534 |
} |
535 |
|
536 |
static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) |
537 |
{ |
538 |
M48t59State *NVRAM = opaque; |
539 |
|
540 |
m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
541 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
542 |
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
543 |
m48t59_write(NVRAM, addr + 3, value & 0xff); |
544 |
} |
545 |
|
546 |
static uint32_t nvram_readb (void *opaque, hwaddr addr) |
547 |
{ |
548 |
M48t59State *NVRAM = opaque; |
549 |
uint32_t retval; |
550 |
|
551 |
retval = m48t59_read(NVRAM, addr); |
552 |
return retval;
|
553 |
} |
554 |
|
555 |
static uint32_t nvram_readw (void *opaque, hwaddr addr) |
556 |
{ |
557 |
M48t59State *NVRAM = opaque; |
558 |
uint32_t retval; |
559 |
|
560 |
retval = m48t59_read(NVRAM, addr) << 8;
|
561 |
retval |= m48t59_read(NVRAM, addr + 1);
|
562 |
return retval;
|
563 |
} |
564 |
|
565 |
static uint32_t nvram_readl (void *opaque, hwaddr addr) |
566 |
{ |
567 |
M48t59State *NVRAM = opaque; |
568 |
uint32_t retval; |
569 |
|
570 |
retval = m48t59_read(NVRAM, addr) << 24;
|
571 |
retval |= m48t59_read(NVRAM, addr + 1) << 16; |
572 |
retval |= m48t59_read(NVRAM, addr + 2) << 8; |
573 |
retval |= m48t59_read(NVRAM, addr + 3);
|
574 |
return retval;
|
575 |
} |
576 |
|
577 |
static const MemoryRegionOps nvram_ops = { |
578 |
.old_mmio = { |
579 |
.read = { nvram_readb, nvram_readw, nvram_readl, }, |
580 |
.write = { nvram_writeb, nvram_writew, nvram_writel, }, |
581 |
}, |
582 |
.endianness = DEVICE_NATIVE_ENDIAN, |
583 |
}; |
584 |
|
585 |
static const VMStateDescription vmstate_m48t59 = { |
586 |
.name = "m48t59",
|
587 |
.version_id = 1,
|
588 |
.minimum_version_id = 1,
|
589 |
.minimum_version_id_old = 1,
|
590 |
.fields = (VMStateField[]) { |
591 |
VMSTATE_UINT8(lock, M48t59State), |
592 |
VMSTATE_UINT16(addr, M48t59State), |
593 |
VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), |
594 |
VMSTATE_END_OF_LIST() |
595 |
} |
596 |
}; |
597 |
|
598 |
static void m48t59_reset_common(M48t59State *NVRAM) |
599 |
{ |
600 |
NVRAM->addr = 0;
|
601 |
NVRAM->lock = 0;
|
602 |
if (NVRAM->alrm_timer != NULL) |
603 |
qemu_del_timer(NVRAM->alrm_timer); |
604 |
|
605 |
if (NVRAM->wd_timer != NULL) |
606 |
qemu_del_timer(NVRAM->wd_timer); |
607 |
} |
608 |
|
609 |
static void m48t59_reset_isa(DeviceState *d) |
610 |
{ |
611 |
M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); |
612 |
M48t59State *NVRAM = &isa->state; |
613 |
|
614 |
m48t59_reset_common(NVRAM); |
615 |
} |
616 |
|
617 |
static void m48t59_reset_sysbus(DeviceState *d) |
618 |
{ |
619 |
M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); |
620 |
M48t59State *NVRAM = &sys->state; |
621 |
|
622 |
m48t59_reset_common(NVRAM); |
623 |
} |
624 |
|
625 |
static const MemoryRegionOps m48t59_io_ops = { |
626 |
.read = NVRAM_readb, |
627 |
.write = NVRAM_writeb, |
628 |
.impl = { |
629 |
.min_access_size = 1,
|
630 |
.max_access_size = 1,
|
631 |
}, |
632 |
.endianness = DEVICE_LITTLE_ENDIAN, |
633 |
}; |
634 |
|
635 |
/* Initialisation routine */
|
636 |
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, |
637 |
uint32_t io_base, uint16_t size, int model)
|
638 |
{ |
639 |
DeviceState *dev; |
640 |
SysBusDevice *s; |
641 |
M48t59SysBusState *d; |
642 |
M48t59State *state; |
643 |
|
644 |
dev = qdev_create(NULL, "m48t59"); |
645 |
qdev_prop_set_uint32(dev, "model", model);
|
646 |
qdev_prop_set_uint32(dev, "size", size);
|
647 |
qdev_prop_set_uint32(dev, "io_base", io_base);
|
648 |
qdev_init_nofail(dev); |
649 |
s = SYS_BUS_DEVICE(dev); |
650 |
d = FROM_SYSBUS(M48t59SysBusState, s); |
651 |
state = &d->state; |
652 |
sysbus_connect_irq(s, 0, IRQ);
|
653 |
memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); |
654 |
if (io_base != 0) { |
655 |
memory_region_add_subregion(get_system_io(), io_base, &d->io); |
656 |
} |
657 |
if (mem_base != 0) { |
658 |
sysbus_mmio_map(s, 0, mem_base);
|
659 |
} |
660 |
|
661 |
return state;
|
662 |
} |
663 |
|
664 |
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
665 |
int model)
|
666 |
{ |
667 |
M48t59ISAState *d; |
668 |
ISADevice *dev; |
669 |
M48t59State *s; |
670 |
|
671 |
dev = isa_create(bus, "m48t59_isa");
|
672 |
qdev_prop_set_uint32(&dev->qdev, "model", model);
|
673 |
qdev_prop_set_uint32(&dev->qdev, "size", size);
|
674 |
qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
|
675 |
qdev_init_nofail(&dev->qdev); |
676 |
d = DO_UPCAST(M48t59ISAState, busdev, dev); |
677 |
s = &d->state; |
678 |
|
679 |
memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); |
680 |
if (io_base != 0) { |
681 |
isa_register_ioport(dev, &d->io, io_base); |
682 |
} |
683 |
|
684 |
return s;
|
685 |
} |
686 |
|
687 |
static void m48t59_init_common(M48t59State *s) |
688 |
{ |
689 |
s->buffer = g_malloc0(s->size); |
690 |
if (s->model == 59) { |
691 |
s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); |
692 |
s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); |
693 |
} |
694 |
qemu_get_timedate(&s->alarm, 0);
|
695 |
|
696 |
vmstate_register(NULL, -1, &vmstate_m48t59, s); |
697 |
} |
698 |
|
699 |
static int m48t59_init_isa1(ISADevice *dev) |
700 |
{ |
701 |
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); |
702 |
M48t59State *s = &d->state; |
703 |
|
704 |
isa_init_irq(dev, &s->IRQ, 8);
|
705 |
m48t59_init_common(s); |
706 |
|
707 |
return 0; |
708 |
} |
709 |
|
710 |
static int m48t59_init1(SysBusDevice *dev) |
711 |
{ |
712 |
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
713 |
M48t59State *s = &d->state; |
714 |
|
715 |
sysbus_init_irq(dev, &s->IRQ); |
716 |
|
717 |
memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size);
|
718 |
sysbus_init_mmio(dev, &s->iomem); |
719 |
m48t59_init_common(s); |
720 |
|
721 |
return 0; |
722 |
} |
723 |
|
724 |
static Property m48t59_isa_properties[] = {
|
725 |
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
726 |
DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), |
727 |
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
728 |
DEFINE_PROP_END_OF_LIST(), |
729 |
}; |
730 |
|
731 |
static void m48t59_init_class_isa1(ObjectClass *klass, void *data) |
732 |
{ |
733 |
DeviceClass *dc = DEVICE_CLASS(klass); |
734 |
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
735 |
ic->init = m48t59_init_isa1; |
736 |
dc->no_user = 1;
|
737 |
dc->reset = m48t59_reset_isa; |
738 |
dc->props = m48t59_isa_properties; |
739 |
} |
740 |
|
741 |
static const TypeInfo m48t59_isa_info = { |
742 |
.name = "m48t59_isa",
|
743 |
.parent = TYPE_ISA_DEVICE, |
744 |
.instance_size = sizeof(M48t59ISAState),
|
745 |
.class_init = m48t59_init_class_isa1, |
746 |
}; |
747 |
|
748 |
static Property m48t59_properties[] = {
|
749 |
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
750 |
DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), |
751 |
DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
752 |
DEFINE_PROP_END_OF_LIST(), |
753 |
}; |
754 |
|
755 |
static void m48t59_class_init(ObjectClass *klass, void *data) |
756 |
{ |
757 |
DeviceClass *dc = DEVICE_CLASS(klass); |
758 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
759 |
|
760 |
k->init = m48t59_init1; |
761 |
dc->reset = m48t59_reset_sysbus; |
762 |
dc->props = m48t59_properties; |
763 |
} |
764 |
|
765 |
static const TypeInfo m48t59_info = { |
766 |
.name = "m48t59",
|
767 |
.parent = TYPE_SYS_BUS_DEVICE, |
768 |
.instance_size = sizeof(M48t59SysBusState),
|
769 |
.class_init = m48t59_class_init, |
770 |
}; |
771 |
|
772 |
static void m48t59_register_types(void) |
773 |
{ |
774 |
type_register_static(&m48t59_info); |
775 |
type_register_static(&m48t59_isa_info); |
776 |
} |
777 |
|
778 |
type_init(m48t59_register_types) |