Revision 4a057712
| b/hw/ppc405.h | ||
|---|---|---|
| 59 | 59 |
uint32_t sysclk); |
| 60 | 60 |
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd); |
| 61 | 61 |
|
| 62 |
void ppc40x_core_reset (CPUState *env); |
|
| 63 |
void ppc40x_chip_reset (CPUState *env); |
|
| 64 |
void ppc40x_system_reset (CPUState *env); |
|
| 65 | 62 |
/* */ |
| 66 | 63 |
typedef struct ppc4xx_mmio_t ppc4xx_mmio_t; |
| 67 | 64 |
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio, |
| b/hw/ppc_chrp.c | ||
|---|---|---|
| 349 | 349 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
| 350 | 350 |
bios_size = load_image(buf, phys_ram_base + bios_offset); |
| 351 | 351 |
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
| 352 |
fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
|
|
| 352 |
cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
|
|
| 353 | 353 |
exit(1); |
| 354 | 354 |
} |
| 355 | 355 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
| 356 |
cpu_register_physical_memory((uint32_t)(-bios_size),
|
|
| 356 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
|
| 357 | 357 |
bios_size, bios_offset | IO_MEM_ROM); |
| 358 | 358 |
|
| 359 | 359 |
/* allocate and load VGA BIOS */ |
| ... | ... | |
| 382 | 382 |
/* now we can load the kernel */ |
| 383 | 383 |
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
| 384 | 384 |
if (kernel_size < 0) {
|
| 385 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
|
| 386 |
kernel_filename); |
|
| 385 |
cpu_abort(env, "qemu: could not load kernel '%s'\n",
|
|
| 386 |
kernel_filename);
|
|
| 387 | 387 |
exit(1); |
| 388 | 388 |
} |
| 389 | 389 |
/* load initrd */ |
| ... | ... | |
| 392 | 392 |
initrd_size = load_image(initrd_filename, |
| 393 | 393 |
phys_ram_base + initrd_base); |
| 394 | 394 |
if (initrd_size < 0) {
|
| 395 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
|
| 396 |
initrd_filename); |
|
| 395 |
cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
|
|
| 396 |
initrd_filename);
|
|
| 397 | 397 |
exit(1); |
| 398 | 398 |
} |
| 399 | 399 |
} else {
|
| b/hw/ppc_prep.c | ||
|---|---|---|
| 560 | 560 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
| 561 | 561 |
bios_size = load_image(buf, phys_ram_base + bios_offset); |
| 562 | 562 |
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
| 563 |
fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
|
| 563 |
cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
|
| 564 | 564 |
exit(1); |
| 565 | 565 |
} |
| 566 | 566 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
| 567 |
cpu_register_physical_memory((uint32_t)(-bios_size),
|
|
| 567 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
|
| 568 | 568 |
bios_size, bios_offset | IO_MEM_ROM); |
| 569 | 569 |
|
| 570 | 570 |
if (linux_boot) {
|
| ... | ... | |
| 572 | 572 |
/* now we can load the kernel */ |
| 573 | 573 |
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
| 574 | 574 |
if (kernel_size < 0) {
|
| 575 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
|
| 576 |
kernel_filename); |
|
| 575 |
cpu_abort(env, "qemu: could not load kernel '%s'\n",
|
|
| 576 |
kernel_filename);
|
|
| 577 | 577 |
exit(1); |
| 578 | 578 |
} |
| 579 | 579 |
/* load initrd */ |
| ... | ... | |
| 582 | 582 |
initrd_size = load_image(initrd_filename, |
| 583 | 583 |
phys_ram_base + initrd_base); |
| 584 | 584 |
if (initrd_size < 0) {
|
| 585 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
|
| 586 |
initrd_filename); |
|
| 585 |
cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
|
|
| 586 |
initrd_filename);
|
|
| 587 | 587 |
exit(1); |
| 588 | 588 |
} |
| 589 | 589 |
} else {
|
| ... | ... | |
| 627 | 627 |
|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
|
| 628 | 628 |
isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); |
| 629 | 629 |
} else {
|
| 630 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
|
| 630 |
/* Why ? */ |
|
| 631 |
cpu_abort(env, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
|
| 631 | 632 |
exit (1); |
| 632 | 633 |
} |
| 633 | 634 |
} |
| b/target-ppc/helper.c | ||
|---|---|---|
| 124 | 124 |
(rw == 1 && (access & PAGE_WRITE))) {
|
| 125 | 125 |
/* Access granted */ |
| 126 | 126 |
#if defined (DEBUG_MMU) |
| 127 |
if (loglevel > 0)
|
|
| 127 |
if (loglevel != 0)
|
|
| 128 | 128 |
fprintf(logfile, "PTE access granted !\n"); |
| 129 | 129 |
#endif |
| 130 | 130 |
ret = 0; |
| 131 | 131 |
} else {
|
| 132 | 132 |
/* Access right violation */ |
| 133 | 133 |
#if defined (DEBUG_MMU) |
| 134 |
if (loglevel > 0)
|
|
| 134 |
if (loglevel != 0)
|
|
| 135 | 135 |
fprintf(logfile, "PTE access rejected\n"); |
| 136 | 136 |
#endif |
| 137 | 137 |
ret = -2; |
| ... | ... | |
| 214 | 214 |
target_ulong eaddr, |
| 215 | 215 |
int is_code, int match_epn) |
| 216 | 216 |
{
|
| 217 |
#if !defined(FLUSH_ALL_TLBS) |
|
| 217 | 218 |
ppc6xx_tlb_t *tlb; |
| 218 | 219 |
int way, nr; |
| 219 | 220 |
|
| 220 |
#if !defined(FLUSH_ALL_TLBS) |
|
| 221 | 221 |
/* Invalidate ITLB + DTLB, all ways */ |
| 222 | 222 |
for (way = 0; way < env->nb_ways; way++) {
|
| 223 | 223 |
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
| ... | ... | |
| 331 | 331 |
if (best != -1) {
|
| 332 | 332 |
done: |
| 333 | 333 |
#if defined (DEBUG_SOFTWARE_TLB) |
| 334 |
if (loglevel > 0) {
|
|
| 334 |
if (loglevel != 0) {
|
|
| 335 | 335 |
fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n", |
| 336 | 336 |
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
| 337 | 337 |
} |
| ... | ... | |
| 353 | 353 |
int ret = -1; |
| 354 | 354 |
|
| 355 | 355 |
#if defined (DEBUG_BATS) |
| 356 |
if (loglevel > 0) {
|
|
| 356 |
if (loglevel != 0) {
|
|
| 357 | 357 |
fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
| 358 | 358 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
| 359 | 359 |
} |
| ... | ... | |
| 369 | 369 |
break; |
| 370 | 370 |
} |
| 371 | 371 |
#if defined (DEBUG_BATS) |
| 372 |
if (loglevel > 0) {
|
|
| 372 |
if (loglevel != 0) {
|
|
| 373 | 373 |
fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
| 374 | 374 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
| 375 | 375 |
} |
| ... | ... | |
| 382 | 382 |
BEPIl = *BATu & 0x0FFE0000; |
| 383 | 383 |
bl = (*BATu & 0x00001FFC) << 15; |
| 384 | 384 |
#if defined (DEBUG_BATS) |
| 385 |
if (loglevel > 0) {
|
|
| 385 |
if (loglevel != 0) {
|
|
| 386 | 386 |
fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
| 387 | 387 |
" BATl 0x" ADDRX "\n", |
| 388 | 388 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
| ... | ... | |
| 403 | 403 |
if (*BATl & 0x00000002) |
| 404 | 404 |
ctx->prot = PAGE_WRITE | PAGE_READ; |
| 405 | 405 |
#if defined (DEBUG_BATS) |
| 406 |
if (loglevel > 0) {
|
|
| 407 |
fprintf(logfile, "BAT %d match: r 0x" ADDRX |
|
| 406 |
if (loglevel != 0) {
|
|
| 407 |
fprintf(logfile, "BAT %d match: r 0x" PADDRX
|
|
| 408 | 408 |
" prot=%c%c\n", |
| 409 | 409 |
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
| 410 | 410 |
ctx->prot & PAGE_WRITE ? 'W' : '-'); |
| ... | ... | |
| 417 | 417 |
} |
| 418 | 418 |
if (ret < 0) {
|
| 419 | 419 |
#if defined (DEBUG_BATS) |
| 420 |
printf("no BAT match for 0x" ADDRX ":\n", virtual);
|
|
| 421 |
for (i = 0; i < 4; i++) {
|
|
| 422 |
BATu = &BATut[i]; |
|
| 423 |
BATl = &BATlt[i]; |
|
| 424 |
BEPIu = *BATu & 0xF0000000; |
|
| 425 |
BEPIl = *BATu & 0x0FFE0000; |
|
| 426 |
bl = (*BATu & 0x00001FFC) << 15; |
|
| 427 |
printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
|
|
| 428 |
" BATl 0x" ADDRX " \n\t" |
|
| 429 |
"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", |
|
| 430 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
|
| 431 |
*BATu, *BATl, BEPIu, BEPIl, bl); |
|
| 420 |
if (loglevel != 0) {
|
|
| 421 |
fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual); |
|
| 422 |
for (i = 0; i < 4; i++) {
|
|
| 423 |
BATu = &BATut[i]; |
|
| 424 |
BATl = &BATlt[i]; |
|
| 425 |
BEPIu = *BATu & 0xF0000000; |
|
| 426 |
BEPIl = *BATu & 0x0FFE0000; |
|
| 427 |
bl = (*BATu & 0x00001FFC) << 15; |
|
| 428 |
fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
|
| 429 |
" BATl 0x" ADDRX " \n\t" |
|
| 430 |
"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", |
|
| 431 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
|
| 432 |
*BATu, *BATl, BEPIu, BEPIl, bl); |
|
| 433 |
} |
|
| 432 | 434 |
} |
| 433 | 435 |
#endif |
| 434 | 436 |
} |
| ... | ... | |
| 483 | 485 |
if (good != -1) {
|
| 484 | 486 |
done: |
| 485 | 487 |
#if defined (DEBUG_MMU) |
| 486 |
if (loglevel > 0) {
|
|
| 487 |
fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x " |
|
| 488 |
if (loglevel != 0) {
|
|
| 489 |
fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
|
|
| 488 | 490 |
"ret=%d\n", |
| 489 | 491 |
ctx->raddr, ctx->prot, ret); |
| 490 | 492 |
} |
| ... | ... | |
| 551 | 553 |
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
| 552 | 554 |
} else {
|
| 553 | 555 |
#if defined (DEBUG_MMU) |
| 554 |
if (loglevel > 0) {
|
|
| 555 |
fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x " |
|
| 556 |
"api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n", |
|
| 557 |
sdr, vsid, pgidx, hash, ctx->pg_addr[0]); |
|
| 556 |
if (loglevel != 0) {
|
|
| 557 |
fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x " |
|
| 558 |
"api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n", |
|
| 559 |
sdr, (uint32_t)vsid, (uint32_t)pgidx, |
|
| 560 |
(uint32_t)hash, ctx->pg_addr[0]); |
|
| 558 | 561 |
} |
| 559 | 562 |
#endif |
| 560 | 563 |
/* Primary table lookup */ |
| ... | ... | |
| 562 | 565 |
if (ret < 0) {
|
| 563 | 566 |
/* Secondary table lookup */ |
| 564 | 567 |
#if defined (DEBUG_MMU) |
| 565 |
if (eaddr != 0xEFFFFFFF && loglevel > 0) {
|
|
| 568 |
if (eaddr != 0xEFFFFFFF && loglevel != 0) {
|
|
| 566 | 569 |
fprintf(logfile, |
| 567 |
"1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x " |
|
| 568 |
"hash=0x%05x pg_addr=0x" ADDRX "\n", |
|
| 569 |
sdr, vsid, pgidx, hash, ctx->pg_addr[1]); |
|
| 570 |
"1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x " |
|
| 571 |
"hash=0x%05x pg_addr=0x" PADDRX "\n", |
|
| 572 |
sdr, (uint32_t)vsid, (uint32_t)pgidx, |
|
| 573 |
(uint32_t)hash, ctx->pg_addr[1]); |
|
| 570 | 574 |
} |
| 571 | 575 |
#endif |
| 572 | 576 |
ret2 = find_pte(ctx, 1, rw); |
| ... | ... | |
| 576 | 580 |
} |
| 577 | 581 |
} else {
|
| 578 | 582 |
#if defined (DEBUG_MMU) |
| 579 |
if (loglevel > 0)
|
|
| 583 |
if (loglevel != 0)
|
|
| 580 | 584 |
fprintf(logfile, "No access allowed\n"); |
| 581 | 585 |
#endif |
| 582 | 586 |
ret = -3; |
| 583 | 587 |
} |
| 584 | 588 |
} else {
|
| 585 | 589 |
#if defined (DEBUG_MMU) |
| 586 |
if (loglevel > 0)
|
|
| 590 |
if (loglevel != 0)
|
|
| 587 | 591 |
fprintf(logfile, "direct store...\n"); |
| 588 | 592 |
#endif |
| 589 | 593 |
/* Direct-store segment : absolutely *BUGGY* for now */ |
| ... | ... | |
| 615 | 619 |
fprintf(logfile, "ERROR: instruction should not need " |
| 616 | 620 |
"address translation\n"); |
| 617 | 621 |
} |
| 618 |
printf("ERROR: instruction should not need "
|
|
| 619 |
"address translation\n"); |
|
| 620 | 622 |
return -4; |
| 621 | 623 |
} |
| 622 | 624 |
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
|
| ... | ... | |
| 663 | 665 |
tlb = &env->tlb[i].tlbe; |
| 664 | 666 |
/* Check valid flag */ |
| 665 | 667 |
if (!(tlb->prot & PAGE_VALID)) {
|
| 666 |
if (loglevel) |
|
| 668 |
if (loglevel != 0)
|
|
| 667 | 669 |
fprintf(logfile, "%s: TLB %d not valid\n", __func__, i); |
| 668 | 670 |
continue; |
| 669 | 671 |
} |
| 670 | 672 |
mask = ~(tlb->size - 1); |
| 671 |
if (loglevel) {
|
|
| 673 |
if (loglevel != 0) {
|
|
| 672 | 674 |
fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> " |
| 673 | 675 |
ADDRX " " ADDRX " %d\n", |
| 674 | 676 |
__func__, i, address, (int)env->spr[SPR_40x_PID], |
| ... | ... | |
| 683 | 685 |
raddr = (tlb->RPN & mask) | (address & ~mask); |
| 684 | 686 |
zsel = (tlb->attr >> 4) & 0xF; |
| 685 | 687 |
zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
| 686 |
if (loglevel) {
|
|
| 688 |
if (loglevel != 0) {
|
|
| 687 | 689 |
fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n", |
| 688 | 690 |
__func__, i, zsel, zpr, rw, tlb->attr); |
| 689 | 691 |
} |
| ... | ... | |
| 750 | 752 |
} |
| 751 | 753 |
if (ret >= 0) {
|
| 752 | 754 |
ctx->raddr = raddr; |
| 753 |
if (loglevel) {
|
|
| 755 |
if (loglevel != 0) {
|
|
| 754 | 756 |
fprintf(logfile, "%s: access granted " ADDRX " => " REGX |
| 755 | 757 |
" %d %d\n", __func__, address, ctx->raddr, ctx->prot, |
| 756 | 758 |
ret); |
| ... | ... | |
| 758 | 760 |
return 0; |
| 759 | 761 |
} |
| 760 | 762 |
} |
| 761 |
if (loglevel) {
|
|
| 763 |
if (loglevel != 0) {
|
|
| 762 | 764 |
fprintf(logfile, "%s: access refused " ADDRX " => " REGX |
| 763 | 765 |
" %d %d\n", __func__, address, raddr, ctx->prot, |
| 764 | 766 |
ret); |
| ... | ... | |
| 808 | 810 |
{
|
| 809 | 811 |
int ret; |
| 810 | 812 |
#if 0 |
| 811 |
if (loglevel > 0) {
|
|
| 813 |
if (loglevel != 0) {
|
|
| 812 | 814 |
fprintf(logfile, "%s\n", __func__); |
| 813 | 815 |
} |
| 814 | 816 |
#endif |
| ... | ... | |
| 857 | 859 |
} |
| 858 | 860 |
} |
| 859 | 861 |
#if 0 |
| 860 |
if (loglevel > 0) {
|
|
| 861 |
fprintf(logfile, "%s address " ADDRX " => %d " ADDRX "\n", |
|
| 862 |
if (loglevel != 0) {
|
|
| 863 |
fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
|
| 862 | 864 |
__func__, eaddr, ret, ctx->raddr); |
| 863 | 865 |
} |
| 864 | 866 |
#endif |
| ... | ... | |
| 903 | 905 |
is_user, is_softmmu); |
| 904 | 906 |
} else if (ret < 0) {
|
| 905 | 907 |
#if defined (DEBUG_MMU) |
| 906 |
if (loglevel > 0)
|
|
| 908 |
if (loglevel != 0)
|
|
| 907 | 909 |
cpu_dump_state(env, logfile, fprintf, 0); |
| 908 | 910 |
#endif |
| 909 | 911 |
if (access_type == ACCESS_CODE) {
|
| ... | ... | |
| 1564 | 1566 |
idx = 2; |
| 1565 | 1567 |
msr &= ~0xFFFF0000; |
| 1566 | 1568 |
#if defined (DEBUG_EXCEPTIONS) |
| 1567 |
if (loglevel) {
|
|
| 1569 |
if (loglevel != 0) {
|
|
| 1568 | 1570 |
fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
| 1569 | 1571 |
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); |
| 1570 | 1572 |
} |
| ... | ... | |
| 1609 | 1611 |
case EXCP_FP: |
| 1610 | 1612 |
if (msr_fe0 == 0 && msr_fe1 == 0) {
|
| 1611 | 1613 |
#if defined (DEBUG_EXCEPTIONS) |
| 1612 |
if (loglevel) {
|
|
| 1614 |
if (loglevel != 0) {
|
|
| 1613 | 1615 |
fprintf(logfile, "Ignore floating point exception\n"); |
| 1614 | 1616 |
} |
| 1615 | 1617 |
#endif |
| ... | ... | |
| 1625 | 1627 |
break; |
| 1626 | 1628 |
case EXCP_INVAL: |
| 1627 | 1629 |
#if defined (DEBUG_EXCEPTIONS) |
| 1628 |
if (loglevel) {
|
|
| 1630 |
if (loglevel != 0) {
|
|
| 1629 | 1631 |
fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n", |
| 1630 | 1632 |
env->nip); |
| 1631 | 1633 |
} |
| ... | ... | |
| 1836 | 1838 |
cmp = &env->spr[SPR_DCMP]; |
| 1837 | 1839 |
} |
| 1838 | 1840 |
fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
| 1839 |
" H1 " ADDRX " H2 " ADDRX " " ADDRX "\n",
|
|
| 1841 |
" H1 " ADDRX " H2 " ADDRX " %08x\n",
|
|
| 1840 | 1842 |
es, en, *miss, en, *cmp, |
| 1841 | 1843 |
env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
| 1842 | 1844 |
env->error_code); |
| ... | ... | |
| 2153 | 2155 |
f = stdout; |
| 2154 | 2156 |
return; |
| 2155 | 2157 |
} |
| 2156 |
fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA); |
|
| 2158 |
fprintf(f, "Memory access at address " ADDRX "\n", EA); |
|
| 2159 |
} |
|
| 2160 |
|
|
| 2161 |
void cpu_dump_rfi (target_ulong RA, target_ulong msr) |
|
| 2162 |
{
|
|
| 2163 |
FILE *f; |
|
| 2164 |
|
|
| 2165 |
if (logfile) {
|
|
| 2166 |
f = logfile; |
|
| 2167 |
} else {
|
|
| 2168 |
f = stdout; |
|
| 2169 |
return; |
|
| 2170 |
} |
|
| 2171 |
fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", |
|
| 2172 |
RA, msr); |
|
| 2157 | 2173 |
} |
| 2158 | 2174 |
|
| 2159 | 2175 |
void cpu_ppc_reset (void *opaque) |
| b/target-ppc/translate.c | ||
|---|---|---|
| 3025 | 3025 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
| 3026 | 3026 |
} else {
|
| 3027 | 3027 |
/* Privilege exception */ |
| 3028 |
if (loglevel) {
|
|
| 3028 |
if (loglevel != 0) {
|
|
| 3029 | 3029 |
fprintf(logfile, "Trying to read priviledged spr %d %03x\n", |
| 3030 | 3030 |
sprn, sprn); |
| 3031 | 3031 |
} |
| ... | ... | |
| 3034 | 3034 |
} |
| 3035 | 3035 |
} else {
|
| 3036 | 3036 |
/* Not defined */ |
| 3037 |
if (loglevel) {
|
|
| 3037 |
if (loglevel != 0) {
|
|
| 3038 | 3038 |
fprintf(logfile, "Trying to read invalid spr %d %03x\n", |
| 3039 | 3039 |
sprn, sprn); |
| 3040 | 3040 |
} |
| ... | ... | |
| 3131 | 3131 |
(*write_cb)(ctx, sprn); |
| 3132 | 3132 |
} else {
|
| 3133 | 3133 |
/* Privilege exception */ |
| 3134 |
if (loglevel) {
|
|
| 3134 |
if (loglevel != 0) {
|
|
| 3135 | 3135 |
fprintf(logfile, "Trying to write priviledged spr %d %03x\n", |
| 3136 | 3136 |
sprn, sprn); |
| 3137 | 3137 |
} |
| ... | ... | |
| 3140 | 3140 |
} |
| 3141 | 3141 |
} else {
|
| 3142 | 3142 |
/* Not defined */ |
| 3143 |
if (loglevel) {
|
|
| 3143 |
if (loglevel != 0) {
|
|
| 3144 | 3144 |
fprintf(logfile, "Trying to write invalid spr %d %03x\n", |
| 3145 | 3145 |
sprn, sprn); |
| 3146 | 3146 |
} |
| ... | ... | |
| 3378 | 3378 |
RET_PRIVOPC(ctx); |
| 3379 | 3379 |
#else |
| 3380 | 3380 |
if (unlikely(!ctx->supervisor)) {
|
| 3381 |
if (loglevel) |
|
| 3381 |
if (loglevel != 0)
|
|
| 3382 | 3382 |
fprintf(logfile, "%s: ! supervisor\n", __func__); |
| 3383 | 3383 |
RET_PRIVOPC(ctx); |
| 3384 | 3384 |
return; |
| ... | ... | |
| 3434 | 3434 |
RET_PRIVOPC(ctx); |
| 3435 | 3435 |
#else |
| 3436 | 3436 |
if (unlikely(!ctx->supervisor)) {
|
| 3437 |
if (loglevel) |
|
| 3437 |
if (loglevel != 0)
|
|
| 3438 | 3438 |
fprintf(logfile, "%s: ! supervisor\n", __func__); |
| 3439 | 3439 |
RET_PRIVOPC(ctx); |
| 3440 | 3440 |
return; |
| ... | ... | |
| 5803 | 5803 |
} |
| 5804 | 5804 |
/* Is opcode *REALLY* valid ? */ |
| 5805 | 5805 |
if (unlikely(handler->handler == &gen_invalid)) {
|
| 5806 |
if (loglevel > 0) {
|
|
| 5806 |
if (loglevel != 0) {
|
|
| 5807 | 5807 |
fprintf(logfile, "invalid/unsupported opcode: " |
| 5808 | 5808 |
"%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n", |
| 5809 | 5809 |
opc1(ctx.opcode), opc2(ctx.opcode), |
| ... | ... | |
| 5816 | 5816 |
} |
| 5817 | 5817 |
} else {
|
| 5818 | 5818 |
if (unlikely((ctx.opcode & handler->inval) != 0)) {
|
| 5819 |
if (loglevel > 0) {
|
|
| 5819 |
if (loglevel != 0) {
|
|
| 5820 | 5820 |
fprintf(logfile, "invalid bits: %08x for opcode: " |
| 5821 | 5821 |
"%02x -%02x - %02x (%08x) 0x" ADDRX "\n", |
| 5822 | 5822 |
ctx.opcode & handler->inval, opc1(ctx.opcode), |
| b/vl.h | ||
|---|---|---|
| 1172 | 1172 |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
| 1173 | 1173 |
dcr_read_cb drc_read, dcr_write_cb dcr_write); |
| 1174 | 1174 |
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
| 1175 |
/* Embedded PowerPC reset */ |
|
| 1176 |
void ppc40x_core_reset (CPUState *env); |
|
| 1177 |
void ppc40x_chip_reset (CPUState *env); |
|
| 1178 |
void ppc40x_system_reset (CPUState *env); |
|
| 1175 | 1179 |
#endif |
| 1176 | 1180 |
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
| 1177 | 1181 |
|
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