Revision 4a942cea hw/apic.c
b/hw/apic.c | ||
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trigger_mode); |
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} |
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void cpu_set_apic_base(CPUState *env, uint64_t val)
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void cpu_set_apic_base(APICState *s, uint64_t val)
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{ |
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APICState *s = env->apic_state; |
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DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val); |
318 | 316 |
if (!s) |
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return; |
... | ... | |
322 | 320 |
/* if disabled, cannot be enabled again */ |
323 | 321 |
if (!(val & MSR_IA32_APICBASE_ENABLE)) { |
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
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env->cpuid_features &= ~CPUID_APIC; |
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s->cpu_env->cpuid_features &= ~CPUID_APIC;
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s->spurious_vec &= ~APIC_SV_ENABLE; |
327 | 325 |
} |
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} |
329 | 327 |
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uint64_t cpu_get_apic_base(CPUState *env)
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uint64_t cpu_get_apic_base(APICState *s)
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{ |
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APICState *s = env->apic_state; |
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DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n", |
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s ? (uint64_t)s->apicbase: 0); |
336 | 332 |
return s ? s->apicbase : 0; |
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} |
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void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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void cpu_set_apic_tpr(APICState *s, uint8_t val)
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{ |
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APICState *s = env->apic_state; |
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if (!s) |
343 | 338 |
return; |
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s->tpr = (val & 0x0f) << 4; |
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apic_update_irq(s); |
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} |
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uint8_t cpu_get_apic_tpr(CPUX86State *env)
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uint8_t cpu_get_apic_tpr(APICState *s)
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{ |
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APICState *s = env->apic_state; |
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351 | 345 |
return s ? s->tpr >> 4 : 0; |
352 | 346 |
} |
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|
... | ... | |
490 | 484 |
} |
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void apic_init_reset(CPUState *env)
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void apic_init_reset(APICState *s)
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{ |
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APICState *s = env->apic_state; |
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496 | 489 |
int i; |
497 | 490 |
|
498 | 491 |
if (!s) |
... | ... | |
516 | 509 |
s->next_time = 0; |
517 | 510 |
s->wait_for_sipi = 1; |
518 | 511 |
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env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); |
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s->cpu_env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
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520 | 513 |
} |
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static void apic_startup(APICState *s, int vector_num) |
... | ... | |
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
526 | 519 |
} |
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void apic_sipi(CPUState *env)
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void apic_sipi(APICState *s)
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{ |
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APICState *s = env->apic_state; |
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cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI); |
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
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534 | 525 |
if (!s->wait_for_sipi) |
535 | 526 |
return; |
536 | 527 |
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env->eip = 0; |
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cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12, |
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env->segs[R_CS].limit, env->segs[R_CS].flags); |
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env->halted = 0; |
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s->cpu_env->eip = 0; |
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cpu_x86_load_seg_cache(s->cpu_env, R_CS, s->sipi_vector << 8, |
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s->sipi_vector << 12, |
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s->cpu_env->segs[R_CS].limit, |
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s->cpu_env->segs[R_CS].flags); |
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s->cpu_env->halted = 0; |
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s->wait_for_sipi = 0; |
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} |
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|
... | ... | |
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(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; |
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|
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cpu_reset(s->cpu_env); |
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apic_init_reset(s->cpu_env);
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apic_init_reset(s); |
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if (bsp) { |
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/* |
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